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REJ09B0286-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2158 Group, H8S/2158 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2158 HD64F2158 Rev. 3.00 Revision Date: Jan 25, 2006 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Jan 25, 2006 page ii of lii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Jan 25, 2006 page iii of lii Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6 Overview 7. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. List of Registers 9. Electrical Characteristics 10. Appendix 11. Index Rev. 3.00 Jan 25, 2006 page iv of lii Preface The H8S/2158 is a microcomputer made up of the H8S/2000 CPU employing Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system, such as a notebook PC and portable information appliance products. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2600 CPU maintains upward compatibility at the object level with the H8/300 CPU and H8/300H CPU. This allows the H8/300, H8/300L, or H8/300H user to easily utilize the H8S/2600 CPU. This LSI is equipped with ROM, RAM, two PWM timers (PWM and PWMX), a 16-bit freerunning timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI), an I2C bus interface (IIC), a D/A converter, an A/D converter, and I/O ports as onchip peripheral modules required for system configuration. In particular, this LSI incorporates a universal serial bus interface (USB) and a multimedia card (MultiMediaCardTM*1) interface (MCIF) for system configuration using a flash memory card as the recording media. In addition, the serial communication interface (SCI) has a smart card interface function. Auxiliary hardware for encryption operation (DES, GF) conforming to the "Keitaide-Music*2" standard is necessary to protect music copyright. Thus, it is easy to interface to the secure multimedia card (Secure-MultiMediaCardTM*1). Further, a data transfer controller (DTC), and a RAM-FIFO unit (RFU) that can operate FIFOs such as the USB and MCIF together are incorporated as a bus master. The on-chip ROM is flash memory (F-ZTATTM*3) with a capacity of 256 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Two operating modes, modes 2 and 3, are provided, and there is a choice of address spaces and modes, single-chip mode and external extended mode. Other unique operating modes, such as writing the boot program to the flash memory, on-chip emulation, and boundary scan, are also available. Notes: 1. MultiMediaCardTM is a trademark of Infineon Technologies AG. Secure-MultiMediaCardTM is a multimedia card with a content protection function. 2. Technology standards for systems that deliver digital contents, such as music over mobile phones. These standards were put together by five companies: SANYO Electric Co., Ltd., Fujitsu Limited, Nippon Columbia Co., Ltd., PFU Limited, and Hitachi, Ltd. These standards consist of a security guideline, a protocol standard, a secure Rev. 3.00 Jan 25, 2006 page v of lii multimedia card standard, and a download and playback system standard. URL: http://www.keitaide-music.org/ 3. F-ZTATTM is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2158 in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2158 to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 28, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 3.00 Jan 25, 2006 page vi of lii H8S/2158 manuals: Document Title H8S/2158 Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-037 ADE-702-231 ADE-702-201 Rev. 3.00 Jan 25, 2006 page vii of lii Rev. 3.00 Jan 25, 2006 page viii of lii Main Revisions in This Edition Item All Page -- Revision (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from "series" to "group" Package TQFP (TFP-100B) deleted (Before) TFBGA (TBP-112) (After) TFBGA (TBP-112A) 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) 6.3.1 Bus Control Register (BCR) 79 Description added The ISCR registers ... or pins ExIRQ15 to ExIRQ2. Switching between pins IRQ15 to IRQ2 and pins ExIRQ15 to ExIRQ2 is performed by means of IRQ sense port select register 16 (ISSR16) and the IRQ sense port select register (ISSR). 107 Bit table amended Bit 1 0 Bit Name IOS1 IOS0 Initial Value 1 1 R/W R/W R/W Description IOS Select 1, 0 Select the address range where the IOS signal is output. For details, refer to table 6.8. 8.2.15 Data Transfer 179 ID Read/Write Select Register B (DTIDSRB) 9.9.2 Port 9 Data Register (P9DR) 251 Bit table amended 0: RAM Peripheral modules (write) 1: Peripheral modules (read) RAM Table amended (Before) R/W (After) R 13.1 Features 315 Description amended * Cascading of two channels -- Cascading of TMR_0 and TMR_1 ... TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel ... Rev. 3.00 Jan 25, 2006 page ix of lii Item 13.3.4 Time Control Register (TCR) Table 13.2 Clock Input to TCNT and Count Condition Page 322 Revision (See Manual for Details) Table 13.2 amended TMR_Y when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before) Increments at overflow signal from TCNT_X* (After) Setting prohibited TMR_X when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before) Increments at compare-match A from TCNT_Y (After) Setting prohibited Note * amended Note: * If the TMR_0 clock input is ... , a count-up clock cannot be generated. Simultaneous setting of this condition should therefore be avoided. -- 13.7 Input Capture Operation 13.9.6 Mode Setting with Cascaded Connection 15.3 Register Descriptions -- 336 344 Description of "TMR_Y and TMR_X Cascaded Connection" deleted Section number amended Description amended If the 16-bit count mode ... , the input clock pulses for TCNT_0 and TCNT_1 are not generated, 378 * TCSR_1 Notes amended 1 R/(W)* [Setting conditions] ... * When TCSR is read when OVF = 1* , then 0 is written to OVF ... 2 16.3.7 Serial Status Register (SSR) 402 Description amended Bit Functions in Smart card Interface Mode (when SMIF in SCMR = 1) Bit 6 [Clearing conditions] ... * When RFU is activated by RDRF = 1 allowing data to be read from RDR (only for SCI_0 and SCI_2) Rev. 3.00 Jan 25, 2006 page x of lii Item 16.3.9 Bit Rate Register (BRR) Table 16.2 Relationship between N Setting in BRR and Bit Rate B 16.3.10 Serial Interface Control Register (SCICR) Page 405 Revision (See Manual for Details) Table 16.2 amended Mode Smart card interface mode Bit Rate B= Error x 10 6 Error (%) = x 10 6 B x S x 22n+1 x (N + 1) S x 22n+1 x (N + 1) - 1 x 100 412 Table amended Bit 3, 2 1, 0 Bit Name -- -- Initial Value All 0 All 0 R/W R/W R Description Reserved The initial value should not be changed. Reserved These bits are always read as 0 and cannot be modified. 16.7.8 Clock Output Control 455 Description amended At Transition from Smart Card Interface Mode to Software Standby Mode: 1. Set the port data register (DR) ... At Transition from Software Standby Mode to Smart Card Interface Mode: 1. Cancel software standby mode. ... 16.8 IrDA Operation Figure 16.36 IrDA Block Diagram 456 Figure 16.36 amended IrDA TxD1 TxD1/IrTxD RxD1/IrRxD Pulse encoder Pulse decoder RxD1 SCI_1 SCICR Description amended Transmission: ... The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in SCICR. 457 Description amended Reception: ... IR frames are converted to UART frames using the IrDA interface before inputting to SCI_1. Data of level 0 is ... Rev. 3.00 Jan 25, 2006 page xi of lii Item Page Revision (See Manual for Details) Bit table amended ACKXE (Before) R/W (After) R Description amended Bit 0 [Clearing conditions] * When ICDRX is read from with no receive data in the shift register (SDRF = 0) in receive mode ... Figure 17.3 amended (b) Receive mode (Before) TDRE (After) SDRE (Before) SDRF (After) RDRF Description amended 9. Clear the IRIC flag in ICCR to cancel wait state. The master device outputs the 9th clock and drives SDA low at 9th receive clock pulse ... 17.3.8 IIC Operation 498 Reservation Adapter Status Register A (ICSRA) 17.3.10 IIC 506 Operation Reservation Adapter Status Register C (ICSRC) Figure 17.3 State 507 Transitions of TDRE, SDRF, and RDRF Bits 17.5.3 Master Receive Operation 520 17.7 Usage Notes Table 17.12 Permissible SCL Rise Time (tsr) Values 542 Table 17.12 amended Time Indication[ns] IICX1, tcyc IICX0 Indication 1 17.5 tcyc Standard mode I2C Bus Specification = = = = = = (Max.) 5 MHz 8 MHz 10 MHz 16 MHz 20 MHz 25 MHz 1000 1000 1000 1000 1000 875 700 Rev. 3.00 Jan 25, 2006 page xii of lii Item 17.7 Usage Notes Page 549, 550 Revision (See Manual for Details) Description added 15. Notes on WAIT function (a) Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall. (1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode (2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. (b) Error phenomenon Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the 7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally. Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall. (c) Restrictions Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2 through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th clock. If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC counter is turned to 1 or 0, please confirm the SCL pins are in L' state after the counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 17.28.) ASD SCL BC2 to BC0 IRIC (operation example) A 9 0 1 7 2 6 Transmit/receive data A 7 2 1 8 SCL = `L' confirm 0 IRIC clear 9 Transmit/receive data 1 7 2 6 3 5 When BC2-0 2 IRIC clear 3 5 4 4 5 3 6 IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 17.28 IRIC Flag Clear Timing on WAIT Operation Rev. 3.00 Jan 25, 2006 page xiii of lii Item 17.7 Usage Notes Page 550, 551 Revision (See Manual for Details) 16. Notes on Arbitration Lost The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the 2 address in the SAR or SARX register, the I C bus interface erroneously recognizes that the address call has occurred. (See figure 17.29.) In multi-master mode, a bus conflict could happen. When The 2 I C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match DATA2 A DATA3 A 2 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device Figure 17.29 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. 2 Rev. 3.00 Jan 25, 2006 page xiv of lii Item 17.7 Usage Notes Page 551 Revision (See Manual for Details) (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Note: Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register. 18.3.1 USB Data FIFO Table 18.2 FIFO Configuration 25.4.1 TAP Controller State Transitions Figure 25.2 TAP Controller State Transitions 28.1 Register Addresses (Address Order) 557 Table 18.2 amended Endpoint Endpoint 4 Endpoint 5 EP4 EP5 Transfer Direction IN OUT FIFO Size Max. 2048 bytes Max. 2048 bytes Configuration Max. 64 bytes x 32 Max. 64 bytes x 32 Description RAM-FIFO (RFU) 755 Figure 25.2 replaced 792 Table amended Number of Bits 8 8 8 Data Bus Width 8 8 8 Number of Access States 3 3 3 Register Name Command register 5 Command start register Operation control register Abbreviation CMDR5 CMDSTRT OPCR Address H'FBC5 H'FBC6 H'FBCA Module MCIF MCIF MCIF 793 Table amended Number of Bits 8 8 8 Data Bus Width 8 8 8 Number of Access States 3 3 3 Register Name Response register 16 Response register D Data timeout register H Abbreviation RSPR16 RSPRD DTOUTRH Address H'FBF0 H'FBF1 H'FBF2 Module MCIF MCIF MCIF 28.1 Register Bits 804 Table amended Register Abbreviation Bit 7 CMDR5 CMDSTRT OPCR CRC -- CMDOFF Bit 6 CRC -- -- Bit 5 CRC -- Bit 4 CRC -- Bit 3 CRC -- -- Bit 2 CRC -- -- Bit 1 CRC -- -- Bit 0 End START -- Module MCIF RD_CONTI DATAEN 805 Table amended Register Abbreviation Bit 7 RSPR16 PSPRD DTOUTRH Bit 7 Bit 7 DTOUT15 Bit 6 Bit 6 Bit 6 DTOUT14 Bit 5 Bit 5 Bit 5 DTOUT13 Bit 4 Bit 4 Bit 4 DTOUT12 Bit 3 Bit 3 Bit 3 DTOUT11 Bit 2 Bit 2 Bit 2 DTOUT10 Bit 1 Bit 1 Bit 1 DTOUT9 Bit 0 Bit 0 Bit 0 DTOUT8 Module MCIF Rev. 3.00 Jan 25, 2006 page xv of lii Item 28.1 Register Bits Page 808 Revision (See Manual for Details) Table amended Register Abbreviation Bit 7 KBCOMP -- Bit 6 -- Bit 5 -- Bit 4 SCANE Bit 3 KBADE Bit 2 KBCH2 Bit 1 KBCH1 Bit 0 KBCH0 Module A/D converter SCI_1 SCICR IrE IrCKS2 IrCKS1 IrCKS0 -- -- -- -- 28.2 Register Bits 808 Bits 2 and 3 in SCICR description amended (Before) IrTxINV (After) -- (Before) IrRxINV (After) -- 28.3 Register States 815 in Each Operating Mode Table amended Register Abbreviation CMDR5 CMDSTRT OPCR Reset Initialized Initialized Initialized High-Speed/ MediumSpeed Watch -- -- -- Initialized Initialized Initialized Sleep -- -- -- Module Sub-Active Sub-Sleep Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Hardware Standby Initialized Initialized Initialized Module MCIF 816 Table amended Register Abbreviation RSPR16 PSPRD DTOUTRH Reset Initialized Initialized Initialized High-Speed/ MediumSpeed Watch -- -- -- Initialized Initialized Initialized Sleep -- -- -- Module Sub-Active Sub-Sleep Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Hardware Standby Initialized Initialized Initialized Module MCIF 29.6 Flash Memory Characteristics Table 29.18 Flash Memory Characteristics 859 Table 29.18 amended Item Reprogramming count Data retention time*10 Symbol NWEC tDRP Min 100*8 10 Typ 9 Max -- Unit Times Years Test Conditions 10,000* -- -- 860 Notes *8*9*10 added Notes: 8. Minimum number of times for which all characteristics are guaranteed after rewriting. (Guarantee range is 1 to minimum value.) 9. Reference value for 25C (as a guide line, rewriting should normally function up to this value). 10. Data retention characteristics when rewriting is performed within the specification range, including the minimum value. B. Product Lineup C. Package Dimensions Figure C.1 Package Dimensions (TBP112A) 863 864 Product type amended (Before) F2158VBP25 (After) F2158VBQ25 Figure of TFP-100B deleted Figure C.1 replaced Rev. 3.00 Jan 25, 2006 page xvi of lii Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Features ............................................................................................................................. Internal Block Diagram..................................................................................................... Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement in Each Operating Mode .......................................................... 1.3.3 Pin Functions ....................................................................................................... 1 1 2 3 3 4 8 Section 2 CPU ...................................................................................................................... 17 2.1 Features ............................................................................................................................. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode ................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 General Registers ................................................................................................. 2.4.2 Program Counter (PC) ......................................................................................... 2.4.3 Extended Control Register (EXR) ....................................................................... 2.4.4 Condition-Code Register (CCR) .......................................................................... 2.4.5 Initial Register Values.......................................................................................... Data Formats ..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Table of Instructions Classified by Function ....................................................... 2.6.2 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Register Direct--Rn............................................................................................. 2.7.2 Register Indirect--@ERn .................................................................................... 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn).............. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn .. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32.................................... 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 ................................................................. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC).................................... 2.7.8 Memory Indirect--@@aa:8 ................................................................................ 17 18 19 19 20 20 22 24 25 26 27 27 28 29 30 30 32 33 34 43 44 45 45 45 45 46 46 47 47 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 3.00 Jan 25, 2006 page xvii of lii 2.8 2.9 2.7.9 Effective Address Calculation.............................................................................. Processing States............................................................................................................... Usage Notes ...................................................................................................................... 2.9.1 Note on TAS Instruction Usage ........................................................................... 2.9.2 Note on Bit Manipulation Instructions................................................................. 2.9.3 EEPMOV Instruction........................................................................................... 48 50 52 52 52 54 Section 3 MCU Operating Modes .................................................................................. 55 3.1 3.2 Operating Mode Selection................................................................................................. Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Serial Timer Control Register (STCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 2 ................................................................................................................. 3.3.2 Mode 3 ................................................................................................................. 3.3.3 Pin Functions ....................................................................................................... Address Map in Each Operating Mode ............................................................................. 55 55 56 57 59 60 60 61 61 62 3.3 3.4 Section 4 Exception Handling ......................................................................................... 65 4.1 4.2 4.3 Exception Handling Types and Priority ............................................................................ Exception Sources and Exception Vector Table ............................................................... Reset.................................................................................................................................. 4.3.1 Reset Exception Handling.................................................................................... 4.3.2 Interrupts after Reset............................................................................................ 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled ........................................ Interrupt Exception Handling............................................................................................ Trap Instruction Exception Handling................................................................................ Stack Status after Exception Handling.............................................................................. Usage Note........................................................................................................................ 65 66 67 68 69 69 69 69 70 71 4.4 4.5 4.6 4.7 Section 5 Interrupt Controller .......................................................................................... 73 5.1 5.2 5.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) ........................................... 5.3.2 Address Break Control Register (ABRKCR)....................................................... 5.3.3 Break Address Registers A to C (BARA to BARC) ............................................ 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) ................ 5.3.5 IRQ Enable Registers (IER16, IER) .................................................................... 5.3.6 IRQ Status Registers (ISR16, ISR) ...................................................................... 73 75 75 76 77 78 79 81 82 Rev. 3.00 Jan 25, 2006 page xviii of lii 5.4 5.5 5.6 5.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) ........................................ Interrupt Sources ............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts................................................................................................. Interrupt Exception Handling Vector Table...................................................................... Interrupt Control Modes and Interrupt Operation ............................................................. 5.6.1 Interrupt Control Mode 0 ..................................................................................... 5.6.2 Interrupt Control Mode 1 ..................................................................................... 5.6.3 Interrupt Exception Handling Sequence .............................................................. 5.6.4 Interrupt Response Times .................................................................................... 5.6.5 DTC Activation by Interrupt................................................................................ Usage Notes ...................................................................................................................... 5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 5.7.2 Instructions that Disable Interrupts ...................................................................... 5.7.3 Interrupts during Execution of EEPMOV Instruction.......................................... 5.3.7 83 84 84 86 86 90 92 94 96 98 99 101 101 102 102 Section 6 Bus Controller.................................................................................................... 103 6.1 6.2 6.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 6.3.1 Bus Control Register (BCR) ................................................................................ 6.3.2 Bus Control Register 2 (BCR2) ........................................................................... 6.3.3 Wait State Control Register (WSCR) .................................................................. 6.3.4 Wait State Control Register 2 (WSCR2) ............................................................. Bus Control ....................................................................................................................... 6.4.1 Bus Specifications................................................................................................ 6.4.2 Advanced Mode ................................................................................................... 6.4.3 Normal Mode....................................................................................................... 6.4.4 I/O Select Signals................................................................................................. Basic Bus Interface ........................................................................................................... 6.5.1 Data Size and Data Alignment............................................................................. 6.5.2 Valid Strobes........................................................................................................ 6.5.3 Basic Operation Timing ....................................................................................... 6.5.4 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 6.6.1 Basic Operation Timing ....................................................................................... 6.6.2 Wait Control ........................................................................................................ Memory Card Interface ..................................................................................................... 6.7.1 Data Size and Data Alignment............................................................................. 6.7.2 Valid Strobes........................................................................................................ 103 105 106 106 108 110 112 113 113 121 122 122 123 123 124 125 133 134 135 136 137 137 138 6.4 6.5 6.6 6.7 Rev. 3.00 Jan 25, 2006 page xix of lii 6.8 6.9 6.7.3 Basic Operation Timing ....................................................................................... 6.7.4 Wait Control ........................................................................................................ Idle Cycle .......................................................................................................................... Bus Arbitration.................................................................................................................. 6.9.1 Bus Master Priority .............................................................................................. 6.9.2 Bus Transfer Timing ............................................................................................ 138 140 141 142 142 143 Section 7 Data Transfer Controller (DTC)................................................................... 145 7.1 7.2 Features ............................................................................................................................. Register Descriptions ........................................................................................................ 7.2.1 DTC Mode Register A (MRA) ............................................................................ 7.2.2 DTC Mode Register B (MRB)............................................................................. 7.2.3 DTC Source Address Register (SAR).................................................................. 7.2.4 DTC Destination Address Register (DAR).......................................................... 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 7.2.6 DTC Transfer Count Register B (CRB)............................................................... 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 7.2.8 DTC Vector Register (DTVECR)........................................................................ Activation Sources ............................................................................................................ Location of Register Information and DTC Vector Table ................................................ Operation........................................................................................................................... 7.5.1 Normal Mode....................................................................................................... 7.5.2 Repeat Mode ........................................................................................................ 7.5.3 Block Transfer Mode ........................................................................................... 7.5.4 Chain Transfer ..................................................................................................... 7.5.5 Interrupts.............................................................................................................. 7.5.6 Operation Timing................................................................................................. 7.5.7 Number of DTC Execution States........................................................................ Procedures for Using DTC................................................................................................ 7.6.1 Activation by Interrupt......................................................................................... 7.6.2 Activation by Software ........................................................................................ Examples of Use of the DTC ............................................................................................ 7.7.1 Normal Mode....................................................................................................... 7.7.2 Software Activation ............................................................................................. Usage Notes ...................................................................................................................... 7.8.1 Module Stop Mode Setting .................................................................................. 7.8.2 On-Chip RAM ..................................................................................................... 7.8.3 DTCE Bit Setting................................................................................................. 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode .......................... 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter.................. 7.8.6 DTC Activation by Interrupt Sources of USB or MCIF ...................................... 145 146 147 148 149 149 149 149 150 151 152 153 156 157 158 159 160 161 161 163 164 164 164 164 164 165 166 166 166 166 166 166 166 7.3 7.4 7.5 7.6 7.7 7.8 Rev. 3.00 Jan 25, 2006 page xx of lii Section 8 RAM-FIFO Unit (RFU).................................................................................. 167 8.1 8.2 Features ............................................................................................................................. Register Descriptions ........................................................................................................ 8.2.1 FIFO Status/Register/Pointer (FSTR) .................................................................. 8.2.2 Base Address Register (BAR).............................................................................. 8.2.3 Read Address Pointer (RAR) ............................................................................... 8.2.4 Write Address Pointer (WAR) ............................................................................. 8.2.5 Temporary Pointer (TMP) ................................................................................... 8.2.6 Valid Data Byte Number (DATAN) .................................................................... 8.2.7 Free Area Byte Number (FREEN)....................................................................... 8.2.8 Read Start Address (NRA)................................................................................... 8.2.9 Write Start Address (NWA)................................................................................. 8.2.10 Data Transfer Control Register A (DTCRA) ....................................................... 8.2.11 Data Transfer Control Register B (DTCRB) ....................................................... 8.2.12 Data Transfer Status Register C (DTSTRC) ........................................................ 8.2.13 Data Transfer ID Register (DTIDR) .................................................................... 8.2.14 Data Transfer ID Read/Write Select Register A (DTIDSRA) ............................. 8.2.15 Data Transfer ID Read/Write Select Register B (DTIDSRB).............................. 8.2.16 Data Transfer Status Register A (DTSTRA)........................................................ 8.2.17 Data Transfer Status Register B (DTSTRB) ........................................................ 8.2.18 Data Transfer Control Register C (DTCRC)........................................................ 8.2.19 Data Transfer Control Register D (DTCRD) ....................................................... 8.2.20 Data Transfer Interrupt Enable Register (DTIER) ............................................... 8.2.21 Data Transfer Register Select Register (DTRSR)................................................ 8.3 Activation Source and Priority.......................................................................................... 8.4 RAM-FIFO Location ........................................................................................................ 8.5 RAM-FIFO Pointer ........................................................................................................... 8.6 RAM-FIFO Manipulation and RFU Bus Cycles............................................................... 8.7 RFU Bus Cycle ................................................................................................................. 8.7.1 Clock Division ..................................................................................................... 8.7.2 RFU Bus Cycle Insertion ..................................................................................... 8.7.3 RFU Response Time ............................................................................................ 8.8 Operation........................................................................................................................... 8.8.1 Transmission/Reception of Single Data Block .................................................... 8.8.2 Transmission/Reception of Consecutive Data Blocks ......................................... 8.8.3 RFU Manipulation by USB.................................................................................. 8.8.4 RFU Manipulation by SCI ................................................................................... 8.8.5 RFU Manipulation by MCIF................................................................................ 8.9 Interrupt Sources ............................................................................................................... 8.10 RFU Initialization ............................................................................................................. 8.11 Usage Notes ...................................................................................................................... 167 169 169 170 170 171 171 172 172 172 173 173 175 176 178 178 179 179 180 180 181 181 181 183 184 184 184 188 188 189 189 191 191 192 193 197 200 202 203 204 Rev. 3.00 Jan 25, 2006 page xxi of lii Section 9 I/O Ports .............................................................................................................. 205 9.1 Port 1................................................................................................................................. 9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 9.1.2 Port 1 Data Register (P1DR)................................................................................ 9.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 9.1.4 Pin Functions ....................................................................................................... 9.1.5 Port 1 Input Pull-Up MOS ................................................................................... Port 2................................................................................................................................. 9.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 9.2.2 Port 2 Data Register (P2DR)................................................................................ 9.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 9.2.4 Pin Functions ....................................................................................................... 9.2.5 Port 2 Input Pull-Up MOS ................................................................................... Port 3................................................................................................................................. 9.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 9.3.2 Port 3 Data Register (P3DR)................................................................................ 9.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 9.3.4 Pin Functions ....................................................................................................... 9.3.5 Port 3 Input Pull-Up MOS ................................................................................... Port 4................................................................................................................................. 9.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 9.4.2 Port 4 Data Register (P4DR)................................................................................ 9.4.3 Pin Functions ....................................................................................................... Port 5................................................................................................................................. 9.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 9.5.2 Port 5 Data Register (P5DR)................................................................................ 9.5.3 Pin Functions ....................................................................................................... Port 6................................................................................................................................. 9.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 9.6.2 Port 6 Data Register (P6DR)................................................................................ 9.6.3 Port 6 Pull-Up MOS Control Register (KMPCR6).............................................. 9.6.4 System Control Register 2 (SYSCR2) ................................................................. 9.6.5 Pin Functions ....................................................................................................... 9.6.6 Port 6 Input Pull-Up MOS ................................................................................... Port 7................................................................................................................................. 9.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... Port 8................................................................................................................................. 9.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 9.8.2 Port 8 Data Register (P8DR)................................................................................ 9.8.3 Pin Functions ....................................................................................................... Port 9................................................................................................................................. 209 209 210 210 211 211 212 212 213 213 214 215 215 216 216 217 217 222 222 223 223 224 228 228 229 229 232 233 233 234 235 236 244 244 244 245 245 246 246 250 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Rev. 3.00 Jan 25, 2006 page xxii of lii 9.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 9.9.2 Port 9 Data Register (P9DR)................................................................................ 9.9.3 Pin Functions ....................................................................................................... 9.10 Port A................................................................................................................................ 9.10.1 Port A Data Direction Register (PADDR) ........................................................... 9.10.2 Port A Output Data Register (PAODR) ............................................................... 9.10.3 Port A Input Data Register (PAPIN).................................................................... 9.10.4 Pin Functions ....................................................................................................... 9.10.5 Input Pull-Up MOS.............................................................................................. 9.11 Change of Peripheral Function Pins.................................................................................. 9.11.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) .................................................................................................... 9.11.2 Port Control Register 0 (PTCNT0) ...................................................................... 250 251 251 254 254 254 255 255 257 258 258 260 261 261 263 263 264 266 266 267 269 270 Section 10 8-Bit PWM Timer (PWM) .......................................................................... 10.1 Features ............................................................................................................................. 10.2 Input/Output Pins .............................................................................................................. 10.3 Register Descriptions ........................................................................................................ 10.3.1 PWM Register Select (PWSL)............................................................................. 10.3.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 10.3.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 10.3.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 10.3.5 Peripheral Clock Select Register (PCSR) ............................................................ 10.4 Operation........................................................................................................................... 11.1 Features ............................................................................................................................. 11.2 Input/Output Pins .............................................................................................................. 11.3 Register Descriptions ........................................................................................................ 11.3.1 PWM D/A Counter H, L (DACNTH, DACNTL)................................................ 11.3.2 PWM (D/A) Data Registers A and B (DADRA and DADRB)............................ 11.3.3 PWM (D/A) Control Register (DACR) ............................................................... 11.3.4 Peripheral Clock Select Register (PCSR) ............................................................ 11.4 Bus Master Interface ......................................................................................................... 11.5 Operation........................................................................................................................... Section 11 14-Bit PWM Timer (PWMX)..................................................................... 273 273 274 274 275 276 277 279 280 281 Section 12 16-Bit Free-Running Timer (FRT)............................................................ 287 12.1 Features ............................................................................................................................. 12.2 Input/Output Pins .............................................................................................................. 12.3 Register Descriptions ........................................................................................................ 12.3.1 Free-Running Counter (FRC) .............................................................................. 287 289 289 290 Rev. 3.00 Jan 25, 2006 page xxiii of lii 12.4 12.5 12.6 12.7 12.3.2 Output Compare Registers A and B (OCRA and OCRB).................................... 12.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ......................... 12.3.5 Output Compare Register DM (OCRDM) ........................................................... 12.3.6 Timer Interrupt Enable Register (TIER) .............................................................. 12.3.7 Timer Control/Status Register (TCSR) ................................................................ 12.3.8 Timer Control Register (TCR) ............................................................................. 12.3.9 Timer Output Compare Control Register (TOCR) .............................................. Operation........................................................................................................................... 12.4.1 Pulse Output......................................................................................................... Operation Timing.............................................................................................................. 12.5.1 FRC Increment Timing ........................................................................................ 12.5.2 Output Compare Output Timing .......................................................................... 12.5.3 FRC Clear Timing................................................................................................ 12.5.4 Input Capture Input Timing ................................................................................. 12.5.5 Buffered Input Capture Input Timing .................................................................. 12.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 12.5.7 Timing of Output Compare Flag (OCF) setting................................................... 12.5.8 Timing of FRC Overflow Flag Setting ................................................................ 12.5.9 Automatic Addition Timing................................................................................. 12.5.10 Mask Signal Generation Timing .......................................................................... Interrupt Sources ............................................................................................................... Usage Notes ...................................................................................................................... 12.7.1 Conflict between FRC Write and Clear ............................................................... 12.7.2 Conflict between FRC Write and Increment........................................................ 12.7.3 Conflict between OCR Write and Compare-Match ............................................. 12.7.4 Switching of Internal Clock and FRC Operation ................................................. 290 290 291 291 292 293 296 297 299 299 300 300 301 301 302 303 304 305 305 306 307 308 309 309 310 311 312 Section 13 8-Bit Timer (TMR) ........................................................................................ 315 13.1 Features ............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Descriptions ........................................................................................................ 13.3.1 Timer Counter (TCNT)........................................................................................ 13.3.2 Time Constant Register A (TCORA)................................................................... 13.3.3 Time Constant Register B (TCORB) ................................................................... 13.3.4 Timer Control Register (TCR) ............................................................................. 13.3.5 Timer Control/Status Register (TCSR) ................................................................ 13.3.6 Input Capture Register (TICR) ............................................................................ 13.3.7 Time Constant Register (TCORC)....................................................................... 13.3.8 Input Capture Registers R and F (TICRR and TICRF)........................................ 13.3.9 Timer Input Select Register (TISR) ..................................................................... Rev. 3.00 Jan 25, 2006 page xxiv of lii 315 318 318 320 320 320 321 323 328 328 329 329 13.4 Operation........................................................................................................................... 13.4.1 Pulse Output......................................................................................................... 13.5 Operation Timing.............................................................................................................. 13.5.1 TCNT Count Timing............................................................................................ 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 13.5.3 Timing of Timer Output at Compare-Match........................................................ 13.5.4 Timing of Counter Clear at Compare-Match ....................................................... 13.5.5 TCNT External Reset Timing .............................................................................. 13.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 13.6 TMR_0 and TMR_1 Cascaded Connection ...................................................................... 13.6.1 16-Bit Count Mode .............................................................................................. 13.6.2 Compare-Match Count Mode .............................................................................. 13.7 Input Capture Operation.................................................................................................... 13.8 Interrupt Sources ............................................................................................................... 13.9 Usage Notes ...................................................................................................................... 13.9.1 Conflict between TCNT Write and Clear ............................................................ 13.9.2 Conflict between TCNT Write and Increment ..................................................... 13.9.3 Conflict between TCOR Write and Compare-Match........................................... 13.9.4 Conflict between Compare-Matches A and B...................................................... 13.9.5 Switching of Internal Clocks and TCNT Operation............................................. 13.9.6 Mode Setting with Cascaded Connection ............................................................ 330 330 331 331 332 332 333 333 334 335 335 335 336 338 339 339 340 341 342 342 344 Section 14 Timer Connection........................................................................................... 345 14.1 Features ............................................................................................................................. 14.2 Input/Output Pins .............................................................................................................. 14.3 Register Descriptions ........................................................................................................ 14.3.1 Timer Connection Register I (TCONRI) ............................................................. 14.3.2 Timer Connection Register O (TCONRO) .......................................................... 14.3.3 Timer Connection Register S (TCONRS)............................................................ 14.3.4 Edge Sense Register (SEDGR) ............................................................................ 14.4 Operation........................................................................................................................... 14.4.1 PWM Decoding (PDC Signal Generation) .......................................................... 14.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 14.4.3 8-Bit Timer Divided Waveform Period Measurement......................................... 14.4.4 IHI Signal and 2fH Modification ......................................................................... 14.4.5 IVI Signal Fall Modification and IHI Synchronization........................................ 14.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 14.4.7 HSYNCO Output ................................................................................................. 14.4.8 VSYNCO Output ................................................................................................. 14.4.9 CBLANK Output ................................................................................................. 345 347 347 348 352 354 356 358 358 359 361 363 365 367 370 371 372 Rev. 3.00 Jan 25, 2006 page xxv of lii Section 15 Watchdog Timer (WDT).............................................................................. 373 15.1 Features ............................................................................................................................. 15.2 Input/Output Pins .............................................................................................................. 15.3 Register Descriptions ........................................................................................................ 15.3.1 Timer Counter (TCNT)........................................................................................ 15.3.2 Timer Control/Status Register (TCSR) ................................................................ 15.4 Operation........................................................................................................................... 15.4.1 Watchdog Timer Mode ........................................................................................ 15.4.2 Interval Timer Mode ............................................................................................ 15.4.3 RESO Signal Output Timing ............................................................................... 15.5 Interrupt Sources ............................................................................................................... 15.6 Usage Notes ...................................................................................................................... 15.6.1 Notes on Register Access..................................................................................... 15.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 15.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 15.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 15.6.5 System Reset by RESO Signal............................................................................. 15.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................ 373 375 375 375 376 379 379 381 382 382 383 383 384 384 384 385 385 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) .................... 387 16.1 Features ............................................................................................................................. 16.2 Input/Output Pins .............................................................................................................. 16.3 Register Descriptions ........................................................................................................ 16.3.1 Receive Shift Register (RSR) .............................................................................. 16.3.2 Receive Data Register (RDR) .............................................................................. 16.3.3 Transmit Data Register (TDR)............................................................................. 16.3.4 Transmit Shift Register (TSR) ............................................................................. 16.3.5 Serial Mode Register (SMR)................................................................................ 16.3.6 Serial Control Register (SCR).............................................................................. 16.3.7 Serial Status Register (SSR) ................................................................................ 16.3.8 Smart Card Mode Register (SCMR) .................................................................... 16.3.9 Bit Rate Register (BRR) ...................................................................................... 16.3.10 Serial Interface Control Register (SCICR)........................................................... 16.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) .................... 16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2) ............... 16.4 Operation in Asynchronous Mode .................................................................................... 16.4.1 Data Transfer Format ........................................................................................... 16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 16.4.3 Clock.................................................................................................................... 16.4.4 Serial Enhanced Mode Clock............................................................................... Rev. 3.00 Jan 25, 2006 page xxvi of lii 387 391 391 392 392 392 392 393 396 398 404 405 412 412 416 417 418 419 420 421 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.4.5 SCI Initialization (Asynchronous Mode) ............................................................. 424 16.4.6 Serial Data Transmission (Asynchronous Mode) ................................................ 425 16.4.7 Serial Data Reception (Asynchronous Mode)...................................................... 427 Multiprocessor Communication Function......................................................................... 431 16.5.1 Multiprocessor Serial Data Transmission ............................................................ 432 16.5.2 Multiprocessor Serial Data Reception ................................................................. 433 Operation in Clocked Synchronous Mode ........................................................................ 437 16.6.1 Clock.................................................................................................................... 437 16.6.2 SCI Initialization (Synchronous).......................................................................... 437 16.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 438 16.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 441 16.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 443 16.6.6 SCI Selection in Serial Enhanced Mode .............................................................. 443 Smart Card Interface Description...................................................................................... 445 16.7.1 Sample Connection .............................................................................................. 445 16.7.2 Data Format (Except in Block Transfer Mode) ................................................... 446 16.7.3 Block Transfer Mode ........................................................................................... 447 16.7.4 Receive Data Sampling Timing and Reception Margin....................................... 447 16.7.5 Initialization ......................................................................................................... 449 16.7.6 Serial Data Transmission (Except in Block Transfer Mode) ............................... 450 16.7.7 Serial Data Reception (Except in Block Transfer Mode)..................................... 453 16.7.8 Clock Output Control........................................................................................... 454 IrDA Operation ................................................................................................................. 456 Interrupt Sources ............................................................................................................... 459 16.9.1 Interrupts in Normal Serial Communication Interface Mode............................... 459 16.9.2 Interrupts in Smart Card Interface Mode ............................................................. 460 Usage Notes ...................................................................................................................... 461 16.10.1 Module Stop Mode Setting .................................................................................. 461 16.10.2 Break Detection and Processing........................................................................... 461 16.10.3 Mark State and Break Detection .......................................................................... 462 16.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..................................................................... 462 16.10.5 Relation between Writing to TDR and TDRE Flag ............................................. 462 16.10.6 Restrictions on Using DTC or RFU ..................................................................... 462 16.10.7 SCI Operations during Mode Transitions ............................................................ 463 16.10.8 Notes on Switching from SCK Pins to Port Pins ................................................. 466 CRC Operation Circuit...................................................................................................... 467 16.11.1 Features................................................................................................................ 467 16.11.2 Register Descriptions ........................................................................................... 467 16.11.3 CRC Operation Circuit Operation........................................................................ 469 Rev. 3.00 Jan 25, 2006 page xxvii of lii 16.11.4 Note on CRC Operation Circuit........................................................................... 472 Section 17 I2C Bus Interface (IIC).................................................................................. 473 17.1 Features ............................................................................................................................. 17.2 Input/Output Pins .............................................................................................................. 17.3 Register Descriptions ........................................................................................................ 17.3.1 I2C Bus Data Register (ICDR) ............................................................................. 17.3.2 Slave Address Register (SAR) ............................................................................. 17.3.3 Second Slave Address Register (SARX) ............................................................. 17.3.4 I2C Bus Mode Register (ICMR)........................................................................... 17.3.5 I2C Bus Control Register (ICCR)......................................................................... 17.3.6 I2C Bus Status Register (ICSR)............................................................................ 17.3.7 IIC Operation Reservation Adapter Control Register (ICCRX) .......................... 17.3.8 IIC Operation Reservation Adapter Status Register A (ICSRA) ......................... 17.3.9 IIC Operation Reservation Adapter Status Register B (ICSRB).......................... 17.3.10 IIC Operation Reservation Adapter Status Register C (ICSRC).......................... 17.3.11 IIC Operation Reservation Adapter Data Register (ICDRX)............................... 17.3.12 IIC Data Shift Register (ICDRS) ......................................................................... 17.3.13 IIC Operation Reservation Adapter Count Register (ICCNT) ............................. 17.3.14 IIC Operation Reservation Adapter Command Register (ICCMD) ..................... 17.4 IIC Operation Reservation Adapter................................................................................... 17.4.1 Restrictions on Accessing IIC Registers .............................................................. 17.4.2 Operation Reservation Commands ...................................................................... 17.5 Operation........................................................................................................................... 17.5.1 I2C Bus Data Format ............................................................................................ 17.5.2 Master Transmit Operation .................................................................................. 17.5.3 Master Receive Operation.................................................................................... 17.5.4 Slave Receive Operation...................................................................................... 17.5.5 Slave Transmit Operation .................................................................................... 17.5.6 IRIC Setting Timing and SCL Control ................................................................ 17.5.7 Operation Using DTC .......................................................................................... 17.5.8 Noise Canceler ..................................................................................................... 17.5.9 Initialization of Internal State .............................................................................. 17.5.10 Sample Flowcharts............................................................................................... 17.6 Interrupt Sources ............................................................................................................... 17.7 Usage Notes ...................................................................................................................... 473 476 476 477 480 481 482 485 492 496 497 499 502 507 508 508 510 510 510 512 516 516 517 519 522 525 527 531 533 534 535 539 541 Section 18 Universal Serial Bus Interface (USB) ...................................................... 553 18.1 Features ............................................................................................................................. 553 18.2 Input/Output Pins .............................................................................................................. 555 18.3 Register Descriptions ........................................................................................................ 555 Rev. 3.00 Jan 25, 2006 page xxviii of lii 18.3.1 USB Data FIFO.................................................................................................... 18.3.2 Endpoint Size Register 1 (EPSZR1) .................................................................... 18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3 (EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3)........................... 18.3.4 Endpoint Valid Size Registers 0S, 0O, 0I, 1, 2, and 3 (FVSR0S, FVSR0O, FVSR0I, FVSR1, FVSR 2, and FVSR3) ........................... 18.3.5 Endpoint Direction Register 0 (EPDIR0) ............................................................ 18.3.6 Packet Transfer Enable Register 0 (PTTER0) ..................................................... 18.3.7 USB Interrupt Enable Registers 0 and 1 (USBIER0, USBIER1) ........................ 18.3.8 USB Interrupt Flag Registers 0 and 1 (USBIFR0, USBIFR1)............................. 18.3.9 Transfer Normal Completion Interrupt Flag Register 0 (TSFR0)........................ 18.3.10 Transfer Abnormal Completion Interrupt Flag Register 0 (TFFR0).................... 18.3.11 USB Control /Status Register 0 (USBCSR0)....................................................... 18.3.12 Endpoint Stall Register 0 (EPSTLR0) ................................................................. 18.3.13 Endpoint Reset Register 0 (EPRSTR0)................................................................ 18.3.14 Device Resume Register (DEVRSMR) ............................................................... 18.3.15 Interrupt Source Select Register 0 (INTSELR0).................................................. 18.3.16 USB Control Registers 0 and 1 (USBCR0, USBCR1) ........................................ 18.3.17 USB PLL Control Register (UPLLCR) ............................................................... 18.3.18 Configuration Value Register (CONFV) ............................................................. 18.3.19 Endpoint 4 Packet Size Register (EP4PKTSZR) ................................................. 18.3.20 RFU/FIFO Read Request Flag Register (UDTRFR) ........................................... 18.3.21 USB Mode Control Register (USBMDCR) ......................................................... 18.3.22 USB Port Control Register (UPRTCR), and USB Test Registers 0 and 1 (UTESTR0 and UTESTR1) ................................................................................. 18.4 Operation........................................................................................................................... 18.4.1 USB Function Core Functions ............................................................................. 18.4.2 Operation on Receiving a SETUP Token (Endpoint 0) ....................................... 18.4.3 Operation on Receiving an OUT Token (Endpoints 0, 2, and 5) ......................... 18.4.4 Operation on Receiving an IN Token (Endpoints 0, 1, 2, 3 and 4) ...................... 18.4.5 Suspend/Resume Operation ................................................................................. 18.4.6 USB Module Reset and Operation Stop Modes................................................... 18.4.7 USB Module Startup Sequence............................................................................ 18.5 Interrupt Sources ............................................................................................................... 18.6 Usage Notes ...................................................................................................................... 557 558 559 560 563 564 565 567 571 576 581 584 587 589 590 592 595 597 598 599 600 601 602 602 604 610 614 618 618 621 625 626 Section 19 Multimedia Card Interface (MCIF)........................................................... 627 19.1 Features ............................................................................................................................. 19.2 Input/Output Pins .............................................................................................................. 19.3 Register Descriptions ........................................................................................................ 19.3.1 Mode Register (MODER).................................................................................... 627 629 630 631 Rev. 3.00 Jan 25, 2006 page xxix of lii 19.4 19.5 19.6 19.7 19.8 19.3.2 Command Type Register (CMDTYR)................................................................. 19.3.3 Response Type Register (RSPTYR) .................................................................... 19.3.4 Transfer Byte Number Count Register (TBCR) .................................................. 19.3.5 Transfer Block Number Counter (TBNCR)......................................................... 19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5) ............................................... 19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) ............... 19.3.8 Command Start Register (CMDSTRT)................................................................ 19.3.9 Operation Control Register (OPCR) .................................................................... 19.3.10 Command Timeout Control Register (CTOCR) .................................................. 19.3.11 Data Timeout Register (DTOUTR) ..................................................................... 19.3.12 Card Status Register (CSTR) ............................................................................... 19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1) .......................................... 19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1)......................................... 19.3.15 Pin Mode Control Register (IOMCR).................................................................. 19.3.16 Transfer Clock Control Register (CLKON)......................................................... MCIF Activation ............................................................................................................... 19.4.1 Initial Status ......................................................................................................... 19.4.2 Activation Procedure ........................................................................................... Operations in MMC Mode ................................................................................................ 19.5.1 Operation of Broadcast Commands ..................................................................... 19.5.2 Operation of Relative Address Commands.......................................................... 19.5.3 Operation of Commands Not Requiring Command Response............................. 19.5.4 Operation of Commands without Data Transfer .................................................. 19.5.5 Commands with Read Data.................................................................................. 19.5.6 Commands with Write Data................................................................................. Operations in SPI Mode.................................................................................................... 19.6.1 Operation of Commands without Data Transfer .................................................. 19.6.2 Commands with Read Data.................................................................................. 19.6.3 Commands with Write Data................................................................................. Interrupt Sources ............................................................................................................... Usage Notes ...................................................................................................................... 632 633 636 636 637 638 640 641 643 644 645 647 649 653 654 655 655 655 656 656 657 657 659 663 669 675 675 679 683 687 687 Section 20 Encryption Operation Circuit (DES and GF)......................................... 689 Section 21 D/A Converter................................................................................................. 691 21.1 Features ............................................................................................................................. 21.2 Input/Output Pins .............................................................................................................. 21.3 Register Descriptions ........................................................................................................ 21.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 21.3.2 D/A Control Register (DACR) ............................................................................ 21.4 Operation........................................................................................................................... Rev. 3.00 Jan 25, 2006 page xxx of lii 691 692 692 692 692 694 21.5 Usage Notes ...................................................................................................................... 695 Section 22 A/D Converter................................................................................................. 697 22.1 Features ............................................................................................................................. 22.2 Input/Output Pins .............................................................................................................. 22.3 Register Descriptions ........................................................................................................ 22.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 22.3.2 A/D Control/Status Register (ADCSR) ............................................................... 22.3.3 A/D Control Register (ADCR) ............................................................................ 22.3.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 22.4 DTC Comparator Scan...................................................................................................... 22.5 Operation........................................................................................................................... 22.5.1 Single Mode......................................................................................................... 22.5.2 Scan Mode ........................................................................................................... 22.5.3 Input Sampling and A/D Conversion Time.......................................................... 22.5.4 External Trigger Input Timing ............................................................................. 22.6 Interrupt Source................................................................................................................. 22.7 A/D Conversion Accuracy Definitions ............................................................................. 22.8 Usage Notes ...................................................................................................................... 22.8.1 Permissible Signal Source Impedance ................................................................. 22.8.2 Influences on Absolute Accuracy ........................................................................ 22.8.3 Setting Range of Analog Power Supply and Other Pins ...................................... 22.8.4 Notes on Board Design ........................................................................................ 22.8.5 Notes on Noise Countermeasures ........................................................................ 697 699 700 700 701 702 703 704 705 705 706 706 708 708 709 711 711 711 712 712 712 Section 23 RAM .................................................................................................................. 715 Section 24 ROM .................................................................................................................. 717 Features ............................................................................................................................. Mode Transition Diagrams ............................................................................................... Block Configuration.......................................................................................................... Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 24.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 24.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 24.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 24.6 Operating Modes............................................................................................................... 24.7 On-Board Programming Modes ........................................................................................ 24.7.1 Boot Mode ........................................................................................................... 24.7.2 User Program Mode............................................................................................. 24.8 Flash Memory Programming/Erasing ............................................................................... 24.1 24.2 24.3 24.4 24.5 717 718 722 723 723 723 725 725 727 727 728 732 732 Rev. 3.00 Jan 25, 2006 page xxxi of lii 24.9 24.10 24.11 24.12 24.8.1 Program/Program-Verify ..................................................................................... 24.8.2 Erase/Erase-Verify............................................................................................... Program/Erase Protection.................................................................................................. 24.9.1 Hardware Protection ............................................................................................ 24.9.2 Software Protection.............................................................................................. 24.9.3 Error Protection.................................................................................................... Interrupts during Flash Memory Programming/Erasing ................................................... Programmer Mode ............................................................................................................ Usage Notes ...................................................................................................................... 733 735 737 737 737 737 738 738 739 Section 25 User Debug Interface (H-UDI)................................................................... 741 25.1 Features ............................................................................................................................. 25.2 Input/Output Pins .............................................................................................................. 25.3 Register Descriptions ........................................................................................................ 25.3.1 Instruction Register (SDIR) ................................................................................. 25.3.2 Bypass Register (SDBPR) ................................................................................... 25.3.3 Boundary Scan Register (SDBSR)....................................................................... 25.3.4 ID Code Register (SDIDR) .................................................................................. 25.4 Operation........................................................................................................................... 25.4.1 TAP Controller State Transitions......................................................................... 25.4.2 H-UDI Reset ........................................................................................................ 25.5 Boundary Scan .................................................................................................................. 25.5.1 Supported Instructions ......................................................................................... 25.5.2 Notes .................................................................................................................... 25.6 Usage Notes ...................................................................................................................... 741 743 744 744 746 746 754 755 755 755 756 756 757 758 761 762 762 763 765 766 766 766 767 767 767 768 768 768 769 Section 26 Clock Pulse Generator .................................................................................. 26.1 Oscillator........................................................................................................................... 26.1.1 Connecting a Crystal Oscillator ........................................................................... 26.1.2 External Clock Input Method............................................................................... 26.2 Duty Correction Circuit..................................................................................................... 26.3 Medium-Speed Clock Divider .......................................................................................... 26.4 Bus Master Clock Select Circuit ....................................................................................... 26.5 Subclock Input Circuit ...................................................................................................... 26.6 Waveform Forming Circuit............................................................................................... 26.7 Clock Select Circuit .......................................................................................................... 26.8 PLL Circuit ....................................................................................................................... 26.9 Usage Notes ...................................................................................................................... 26.9.1 Note on Resonator................................................................................................ 26.9.2 Notes on Board Design ........................................................................................ 26.9.3 Processing for X1 and X2 Pins ............................................................................ Rev. 3.00 Jan 25, 2006 page xxxii of lii Section 27 Power-Down Modes...................................................................................... 771 27.1 Register Descriptions ........................................................................................................ 27.1.1 Standby Control Register (SBYCR) .................................................................... 27.1.2 Low-Power Control Register (LPWRCR) ........................................................... 27.1.3 System Control Register 2 (SYSCR2) ................................................................. 27.1.4 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) Sub-Chip Module Stop Control Registers BH and BL (SUBMSTPBH, SUBMSTPBL) .... 27.2 Mode Transitions and LSI States ...................................................................................... 27.3 Medium-Speed Mode........................................................................................................ 27.4 Sleep Mode ....................................................................................................................... 27.5 Software Standby Mode.................................................................................................... 27.6 Hardware Standby Mode .................................................................................................. 27.7 Watch Mode...................................................................................................................... 27.8 Subsleep Mode.................................................................................................................. 27.9 Subactive Mode ................................................................................................................ 27.10 Module Stop Mode ........................................................................................................... 27.11 Direct Transitions.............................................................................................................. 27.12 Usage Notes ...................................................................................................................... 27.12.1 I/O Port Status...................................................................................................... 27.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 27.12.3 DTC Module Stop Mode ..................................................................................... 772 772 774 775 777 778 781 782 782 784 785 786 787 787 788 789 789 789 789 Section 28 List of Registers.............................................................................................. 791 28.1 Register Addresses (Address Order) ................................................................................. 791 28.2 Register Bits...................................................................................................................... 804 28.3 Register States in Each Operating Mode........................................................................... 815 Section 29 Electrical Characteristics.............................................................................. 825 29.1 Absolute Maximum Ratings ............................................................................................. 29.2 DC Characteristics ............................................................................................................ 29.3 AC Characteristics ............................................................................................................ 29.3.1 Clock Timing ....................................................................................................... 29.3.2 Control Signal Timing ......................................................................................... 29.3.3 Bus Timing .......................................................................................................... 29.3.4 Timing of On-Chip Peripheral Modules .............................................................. 29.4 A/D Conversion Characteristics........................................................................................ 29.5 D/A Conversion Characteristics........................................................................................ 29.6 Flash Memory Characteristics........................................................................................... 825 826 834 835 837 839 845 856 858 859 Appendix .................................................................................................................................. 861 A. I/O Port States in Each Pin State....................................................................................... 861 Rev. 3.00 Jan 25, 2006 page xxxiii of lii B. C. Product Lineup.................................................................................................................. 863 Package Dimensions ......................................................................................................... 864 Index .......................................................................................................................................... 865 Rev. 3.00 Jan 25, 2006 page xxxiv of lii Figures Section 1 Overview Figure 1.1 Internal Block Diagram ........................................................................................ Figure 1.2 Pin Arrangement (TBP-112A: Top View)............................................................ Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) .............................................................. Figure 2.2 Stack Structure in Normal Mode .......................................................................... Figure 2.3 Exception Vector Table (Advanced Mode) .......................................................... Figure 2.4 Stack Structure in Advanced Mode ...................................................................... Figure 2.5 Memory Map ........................................................................................................ Figure 2.6 CPU Internal Registers ......................................................................................... Figure 2.7 Usage of General Registers................................................................................... Figure 2.8 Stack ..................................................................................................................... Figure 2.9 General Register Data Formats (1) ....................................................................... Figure 2.9 General Register Data Formats (2) ....................................................................... Figure 2.10 Memory Data Formats .......................................................................................... Figure 2.11 Instruction Formats (Examples)............................................................................ Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ................. Figure 2.13 State Transitions ................................................................................................... 2 3 21 21 22 23 24 25 26 27 30 31 32 44 47 51 Section 3 MCU Operating Modes Figure 3.1 Address Map (Mode 2) ......................................................................................... 62 Figure 3.2 Address Map (Mode 3) ......................................................................................... 63 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3) ..................................................................................... 68 Figure 4.2 Stack Status after Exception Handling.................................................................. 70 Figure 4.3 Operation when SP Value Is Odd ......................................................................... 71 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................. Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ....................................................... Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8 (Example of KIN9 to KIN0) ................................................................................. Figure 5.4 Block Diagram of Interrupt Control Operation..................................................... Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.................................................................................................................. Figure 5.6 State Transition in Interrupt Control Mode 1........................................................ 74 85 86 90 93 94 Rev. 3.00 Jan 25, 2006 page xxxv of lii Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.................................................................................................................. Interrupt Exception Handling ............................................................................... Interrupt Control for DTC..................................................................................... Conflict between Interrupt Generation and Disabling .......................................... 96 97 99 101 Section 6 Bus Controller Figure 6.1 Block Diagram of Bus Controller ......................................................................... Figure 6.2 IOS Signal Output Timing.................................................................................... Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)......................... Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ....................... Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space......................................................... Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space......................................................... Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ...................... Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ....................... Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access).............................. Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ...................... Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ....................... Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access).............................. Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) .................................. Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................. Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................. Figure 6.16 Access Sizes and Data Alignment Control ........................................................... Figure 6.17 Access Timing in Memory Card Mode (Basic Cycle).......................................... Figure 6.18 Access Timing in Memory Card Mode (OWEAC = OWENC = 1 with Wait State Insertion) ........................................... Figure 6.19 Access Timing Example in Memory Card Mode (Wait State Insertion by Program Wait and CPWAIT Pin) .................................. Figure 6.20 Examples of Idle Cycle Operation........................................................................ Section 7 Data Transfer Controller (DTC) Figure 7.1 Block Diagram of DTC......................................................................................... Figure 7.2 Block Diagram of DTC Activation Source Control.............................................. Figure 7.3 DTC Register Information Location in Address Space ........................................ Figure 7.4 DTC Operation Flowchart .................................................................................... Figure 7.5 Memory Mapping in Normal Mode...................................................................... Figure 7.6 Memory Mapping in Repeat Mode....................................................................... Figure 7.7 Memory Mapping in Block Transfer Mode.......................................................... Figure 7.8 Chain Transfer Operation ..................................................................................... Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................. 104 122 123 124 125 126 127 128 129 130 131 132 134 135 136 137 139 139 140 141 146 152 153 156 157 158 159 160 161 Rev. 3.00 Jan 25, 2006 page xxxvi of lii Figure 7.10 Figure 7.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ............................................................................................ 162 DTC Operation Timing (Example of Chain Transfer).......................................... 162 Section 8 RAM-FIFO Unit (RFU) Figure 8.1 Block Diagram of RFU......................................................................................... Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode .......................... Figure 8.3 Example of RFU Response Time ........................................................................ Figure 8.4 RFU Interface of USB .......................................................................................... Figure 8.5 Operation Flow of USB IN Transfer .................................................................... Figure 8.6 Operation Flow of USB OUT Transfer................................................................. Figure 8.7 RFU Interface of SCI............................................................................................ Figure 8.8 Operation Flow of SCI Transmission ................................................................... Figure 8.9 Operation Flow of SCI Reception......................................................................... Figure 8.10 RFU Interface of MCIF ........................................................................................ Figure 8.11 Operation Flow of MCIF Transmission................................................................ Figure 8.12 Operation Flow of MCIF Reception ..................................................................... Figure 8.13 RFU Initialization Flow ........................................................................................ 168 188 190 194 195 196 197 198 199 200 201 202 203 Section 10 8-Bit PWM Timer (PWM) Figure 10.1 Block Diagram of PWM Timer ............................................................................ 262 Figure 10.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ............................................................ 271 Section 11 14-Bit PWM Timer (PWMX) Figure 11.1 PWM (D/A) Block Diagram................................................................................. Figure 11.2 PWM (D/A) Operation ......................................................................................... Figure 11.3 Output Waveform (OS = 0, DADR corresponds to TL)........................................ Figure 11.4 Output Waveform (OS = 1, DADR corresponds to TH) ....................................... Figure 11.5 D/A Data Register Configuration when CFS = 1 ................................................. Figure 11.6 Output Waveform when DADR = H'0207 (OS = 1)............................................. Section 12 16-Bit Free-Running Timer (FRT) Figure 12.1 Block Diagram of 16-Bit Free-Running Timer..................................................... Figure 12.2 Example of Pulse Output ...................................................................................... Figure 12.3 Increment Timing with Internal Clock Source...................................................... Figure 12.4 Increment Timing with External Clock Source .................................................... Figure 12.5 Timing of Output Compare A Output................................................................... Figure 12.6 Clearing of FRC by Compare-Match A Signal..................................................... Figure 12.7 Input Capture Input Signal Timing (Usual Case) ................................................. Figure 12.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read).................... 273 281 283 284 284 285 288 299 300 300 301 301 302 302 Rev. 3.00 Jan 25, 2006 page xxxvii of lii Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Buffered Input Capture Timing ............................................................................ Buffered Input Capture Timing (BUFEA = 1)...................................................... Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................. Timing of Output Compare Flag (OCFA or OCFB) Setting ................................ Timing of Overflow Flag (OVF) Setting .............................................................. OCRA Automatic Addition Timing...................................................................... Timing of Input Capture Mask Signal Setting ...................................................... Timing of Input Capture Mask Signal Clearing.................................................... FRC Write-Clear Conflict..................................................................................... FRC Write-Increment Conflict ............................................................................. Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) .............................................. Figure 12.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Used) ..................................................... Section 13 8-Bit Timer (TMR) Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ......................................... Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ....................................... Figure 13.3 Pulse Output Example .......................................................................................... Figure 13.4 Count Timing for Internal Clock Input ................................................................. Figure 13.5 Count Timing for External Clock Input................................................................ Figure 13.6 Timing of CMF Setting at Compare-Match.......................................................... Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal .......................... Figure 13.8 Timing of Counter Clear by Compare-Match....................................................... Figure 13.9 Timing of Counter Clear by External Reset Input ................................................ Figure 13.10 Timing of OVF Flag Setting ................................................................................. Figure 13.11 Timing of Input Capture Operation ...................................................................... Figure 13.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read) ......................... Figure 13.13 Input Capture Signal Selection ............................................................................. Figure 13.14 Conflict between TCNT Write and Clear ............................................................. Figure 13.15 Conflict between TCNT Write and Increment...................................................... Figure 13.16 Conflict between TCOR Write and Compare-Match............................................ Section 14 Timer Connection Figure 14.1 Block Diagram of Timer Connection.................................................................... Figure 14.2 Timing Chart for PWM Decoding ........................................................................ Figure 14.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)............. Figure 14.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) ............................. Figure 14.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods ................................................................................................ Rev. 3.00 Jan 25, 2006 page xxxviii of lii 303 304 304 305 306 306 307 307 309 310 311 312 316 317 330 331 331 332 332 333 333 334 336 337 337 340 340 341 346 359 360 360 363 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 2fH Modification Timing Chart............................................................................ Fall Modification and IHI Synchronization Timing Chart.................................... IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................... CBLANK Output Waveform Generation ............................................................. 364 366 369 372 Section 15 Watchdog Timer (WDT) Figure 15.1 Block Diagram of WDT ....................................................................................... Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation .............................................. Figure 15.3 Interval Timer Mode Operation ............................................................................ Figure 15.4 OVF Flag Set Timing ........................................................................................... Figure 15.5 Output Timing of RESO Signal............................................................................ Figure 15.6 Writing to TCNT and TCSR (WDT_0) ................................................................ Figure 15.7 Conflict between TCNT Write and Increment...................................................... Figure 15.8 Sample Circuit for Resetting the System by the RESO Signal ............................. Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Figure 16.1 Block Diagram of SCI_1 ...................................................................................... Figure 16.2 Block Diagram of SCI_0 and SCI_2 .................................................................... Figure 16.3 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... Figure 16.4 Receive Data Sampling Timing in Asynchronous Mode...................................... Figure 16.5 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) .......................................................................................... Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1)................... Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2)................... Figure 16.8 Sample SCI Initialization Flowchart..................................................................... Figure 16.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................. Figure 16.10 Sample Serial Transmission Flowchart................................................................. Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ........................................................................................................ Figure 16.12 Sample Serial Reception Flowchart (1) ................................................................ Figure 16.12 Sample Serial Reception Flowchart (2) ................................................................ Figure 16.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart........................................ Figure 16.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ........................................................................ Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... Figure 16.17 Data Format in Synchronous Communication (LSB-First) .................................. 374 380 381 381 382 383 384 385 389 390 417 419 420 422 423 424 425 426 427 429 430 432 433 434 435 436 437 Rev. 3.00 Jan 25, 2006 page xxxix of lii Figure 16.18 Figure 16.19 Figure 16.20 Figure 16.21 Figure 16.22 Figure 16.23 Figure 16.24 Figure 16.25 Figure 16.26 Figure 16.27 Figure 16.28 Figure 16.29 Figure 16.30 Figure 16.31 Figure 16.32 Figure 16.33 Figure 16.34 Figure 16.35 Figure 16.36 Figure 16.37 Figure 16.38 Figure 16.39 Figure 16.40 Figure 16.41 Figure 16.42 Figure 16.43 Figure 16.44 Figure 16.45 Figure 16.46 Figure 16.47 Figure 16.48 Figure 16.49 Figure 16.50 Sample SCI Initialization Flowchart..................................................................... Sample SCI Transmission Operation in Clocked Synchronous Mode.................. Sample Serial Transmission Flowchart................................................................. Example of SCI Receive Operation in Clocked Synchronous Mode.................... Sample Serial Reception Flowchart...................................................................... Sample Flowchart of Simultaneous Serial Transmission and Reception.............. Pin Connection for Smart Card Interface.............................................................. Data Formats in Normal Smart Card Interface Mode........................................... Direct Convention (SDIR = SINV = O/E = 0)...................................................... Inverse Convention (SDIR = SINV = O/E = 1) .................................................... Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate) ............................................ Data Re-transfer Operation in SCI Transmission Mode ....................................... TEND Flag Set Timings during Transmission ..................................................... Sample Transmission Flowchart........................................................................... Data Re-transfer Operation in SCI Reception Mode ............................................ Sample Reception Flowchart ................................................................................ Clock Output Fixing Timing................................................................................. Clock Stop and Restart Procedure ........................................................................ IrDA Block Diagram ............................................................................................ IrDA Transmission and Reception........................................................................ Sample Transmission using DTC in Clocked Synchronous Mode ....................... Sample Flowchart for Mode Transition during Transmission .............................. Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ Pin States during Transmission in Clocked Synchronous Mode (Internal Clock)..................................................................................................... Sample Flowchart for Mode Transition during Reception.................................... Switching from SCK Pins to Port Pins ................................................................. Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ......... Block Diagram of CRC Operation Circuit............................................................ LSB-First Data Transmission ............................................................................... MSB-First Data Transmission .............................................................................. LSB-First Data Reception..................................................................................... MSB-First Data Reception.................................................................................... LSB-First and MSB-First Transmit Data.............................................................. 438 439 440 441 442 444 445 446 446 447 448 451 451 452 453 454 455 456 456 457 463 464 464 465 465 466 466 467 469 469 470 471 472 Section 17 I2C Bus Interface (IIC) Figure 17.1 Block Diagram of I2C Bus Interface ..................................................................... Figure 17.2 I2C Bus Interface Connections (Example: This LSI as Master)............................ Figure 17.3 State Transitions of TDRE, SDRF, and RDRF Bits ............................................. Figure 17.4 I2C Bus Data Formats (I2C Bus Formats) ............................................................. Rev. 3.00 Jan 25, 2006 page xl of lii 475 476 507 516 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 Figure 17.9 Figure 17.10 Figure 17.11 Figure 17.12 Figure 17.13 Figure 17.14 Figure 17.15 Figure 17.16 Figure 17.17 Figure 17.18 Figure 17.19 Figure 17.20 Figure 17.21 Figure 17.22 Figure 17.23 Figure 17.24 Figure 17.25 Figure 17.26 Figure 17.27 Figure 17.28 Figure 17.29 I2C Bus Formats (Serial Formats)......................................................................... I2C Bus Timing ..................................................................................................... Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) ............ Master Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, WAIT = 1) ........................................................................... Master Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, WAIT = 1) ........................................................................... Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0).......... Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0)......... Slave Transmit Mode Operation Timing Example (MLS = 0) ............................. IRIC Flag Timing and SCL Control (1)................................................................ IRIC Flag Timing and SCL Control (2)................................................................ IRIC Flag Timing and SCL Control (3)................................................................ Example of Interrupt Flag Timing of Operation Reservation Adapter ................. Block Diagram of Noise Canceler ........................................................................ Sample Flowchart for Master Transmit Mode...................................................... Sample Flowchart for Master Receive Mode ....................................................... Sample Flowchart for Slave Receive Mode.......................................................... Sample Flowchart for Slave Transmit Mode ........................................................ Notes on Reading Master Receive Data ............................................................... Flowchart and Timing of Start Condition Issuance for Retransmission ............... Stop Condition Issuance Timing........................................................................... IRIC Flag Clearing Timing When WAIT = 1....................................................... ICDR Read and ICCR Access Timing in Slave Transmit Mode .......................... TRS Bit Set Timing in Slave Mode ...................................................................... IRIC Flag Clear Timing on WAIT Operation....................................................... Diagram of Erroneous Operation when Arbitration Is Lost.................................. 516 517 519 521 522 523 524 526 527 528 529 530 534 536 537 538 539 544 545 546 546 547 548 550 551 Section 18 Universal Serial Bus Interface (USB) Figure 18.1 Block Diagram of USB......................................................................................... Figure 18.2 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is not Required and When SETICNT = 0) ..... Figure 18.3 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Required and When SETICNT = 0) ........... Figure 18.4 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Not Required and When SETICNT = 1) .... Figure 18.5 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Required and When SETICNT = 1) ........... Figure 18.6 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Empty) ....... Figure 18.7 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Full) ........... Figure 18.8 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Empty) ....... 554 606 607 608 609 610 611 612 Rev. 3.00 Jan 25, 2006 page xli of lii Figure 18.9 Figure 18.10 Figure 18.11 Figure 18.12 Figure 18.13 Figure 18.14 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Full) ........... Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Full) ................... Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Empty)............... Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Full) ................... Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Empty)............... Operation Procedure for Initializing USB Module ............................................... 613 614 615 616 617 624 Section 19 Multimedia Card Interface (MCIF) Figure 19.1 Block Diagram of MCIF....................................................................................... Figure 19.2 Example of Command Sequence for Commands that Do Not Require Command Response ............................................................................................. Figure 19.3 Operational Flow for Commands that Do Not Require Command Response....... Figure 19.4 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) ............................................................................................ Figure 19.5 Example of Command Sequence for Commands without Data Transfer (with Data Busy State).......................................................................................... Figure 19.6 Operational Flow for Commands without Data Transfer...................................... Figure 19.7 Example of Command Sequence for Commands with Read Data (1) .................. Figure 19.8 Example of Command Sequence for Commands with Read Data (2) .................. Figure 19.9 Example of Command Sequence for Commands with Read Data (3) .................. Figure 19.10 Example of Command Sequence for Commands with Read Data (4) .................. Figure 19.11 Operational Flow for Commands with Read Data................................................ Figure 19.12 Example of Command Sequence for Commands with Write Data (1) ................. Figure 19.13 Example of Command Sequence for Commands with Write Data (2) ................. Figure 19.14 Example of Command Sequence for Commands with Write Data (3) ................. Figure 19.15 Example of Command Sequence for Commands with Write Data (4) ................. Figure 19.16 Operational Flow for Commands with Write Data ............................................... Figure 19.17 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) ............................................................................................ Figure 19.18 Example of Command Sequence for Commands without Data Transfer (with Data Busy State).......................................................................................... Figure 19.19 Operational Flow for Commands without Data Transfer...................................... Figure 19.20 Example of Command Sequence for Commands with Read Data (1) .................. Figure 19.21 Example of Command Sequence for Commands with Read Data (2) .................. Figure 19.22 Operational Flow for Commands with Read Data................................................ Figure 19.23 Example of Command Sequence for Commands with Write Data (1) ................. Figure 19.24 Example of Command Sequence for Commands with Write Data (2) ................. Figure 19.25 Operational Flow for Commands with Write Data ............................................... 628 658 658 660 661 662 664 665 666 667 668 670 671 672 673 674 676 677 678 680 681 682 684 685 686 Section 21 D/A Converter Figure 21.1 Block Diagram of D/A Converter......................................................................... 691 Rev. 3.00 Jan 25, 2006 page xlii of lii Figure 21.2 D/A Converter Operation Example ...................................................................... 694 Section 22 A/D Converter Figure 22.1 Block Diagram of A/D Converter......................................................................... Figure 22.2 A/D Conversion Timing ....................................................................................... Figure 22.3 External Trigger Input Timing.............................................................................. Figure 22.4 A/D Conversion Accuracy Definitions ................................................................. Figure 22.5 A/D Conversion Accuracy Definitions ................................................................. Figure 22.6 Example of Analog Input Circuit.......................................................................... Figure 22.7 Example of Analog Input Protection Circuit ........................................................ Figure 22.8 Analog Input Pin Equivalent Circuit..................................................................... Section 24 ROM Figure 24.1 Block Diagram of Flash Memory ......................................................................... Figure 24.2 Flash Memory State Transitions ........................................................................... Figure 24.3 Boot Mode ............................................................................................................ Figure 24.4 User Program Mode (Example) ............................................................................ Figure 24.5 Flash Memory Block Configuration .................................................................... Figure 24.6 On-Chip RAM Area in Boot Mode ...................................................................... Figure 24.7 ID Code Area........................................................................................................ Figure 24.8 Programming/Erasing Flowchart Example in User Program Mode ..................... Figure 24.9 Program/Program-Verify Flowchart ..................................................................... Figure 24.10 Erase/Erase-Verify Flowchart............................................................................... Figure 24.11 Memory Map in Programmer Mode ..................................................................... Section 25 User Debug Interface (H-UDI) Figure 25.1 Block Diagram of H-UDI ..................................................................................... Figure 25.2 TAP Controller State Transitions.......................................................................... Figure 25.3 Reset Signal Circuit Without Reset Signal Interference ....................................... Figure 25.4 Serial Data Input/Output (1) ................................................................................. Figure 25.4 Serial Data Input/Output (2) ................................................................................. Section 26 Clock Pulse Generator Figure 26.1 Block Diagram of Clock Pulse Generator............................................................. Figure 26.2 Typical Connection to Crystal Resonator ............................................................. Figure 26.3 Equivalent Circuit of Crystal Resonator ............................................................... Figure 26.4 Example of External Clock Input ......................................................................... Figure 26.5 External Clock Input Timing ................................................................................ Figure 26.6 Timing of External Clock Output Stabilization Delay Time ................................ Figure 26.7 Subclock Input Timing ......................................................................................... Figure 26.8 Note on Board Design of Oscillation Circuit Section........................................... 698 707 708 710 710 711 713 713 718 719 720 721 722 731 731 732 734 736 739 742 755 758 759 760 761 762 762 763 764 765 767 768 Rev. 3.00 Jan 25, 2006 page xliii of lii Figure 26.9 Processing for X1 and X2 Pins ............................................................................. 769 Section 27 Power-Down Modes Figure 27.1 Mode Transition Diagram..................................................................................... Figure 27.2 Medium-Speed Mode Timing............................................................................... Figure 27.3 Software Standby Mode Application Example..................................................... Figure 27.4 Hardware Standby Mode Timing.......................................................................... Section 29 Electrical Characteristics Figure 29.1 Darlington Transistor Drive Circuit (Example) .................................................... Figure 29.2 LED Drive Circuit (Example)............................................................................... Figure 29.3 Output Load Circuit .............................................................................................. Figure 29.4 System Clock Timing ........................................................................................... Figure 29.5 Oscillation Stabilization Timing ........................................................................... Figure 29.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) .................... Figure 29.7 Reset Input Timing ............................................................................................... Figure 29.8 Interrupt Input Timing .......................................................................................... Figure 29.9 Basic Bus Timing/2-State Access......................................................................... Figure 29.10 Basic Bus Timing/3-State Access......................................................................... Figure 29.11 Basic Bus Timing/3-State Access with One Wait State........................................ Figure 29.12 CF Interface Basic Timing/3-State Access ........................................................... Figure 29.13 Burst ROM Access Timing/2-State Access .......................................................... Figure 29.14 Burst ROM Access Timing/1-State Access .......................................................... Figure 29.15 I/O Port Input/Output Timing ............................................................................... Figure 29.16 FRT Input/Output Timing..................................................................................... Figure 29.17 FRT Clock Input Timing ...................................................................................... Figure 29.18 8-Bit Timer Output Timing................................................................................... Figure 29.19 8-Bit Timer Clock Input Timing........................................................................... Figure 29.20 8-Bit Timer Reset Input Timing ........................................................................... Figure 29.21 PWM, PWMX Output Timing.............................................................................. Figure 29.22 SCK Clock Input Timing...................................................................................... Figure 29.23 SCI Input/Output Timing (Clock Synchronous Mode)......................................... Figure 29.24 A/D Converter External Trigger Input Timing ..................................................... Figure 29.25 WDT Output Timing (RESO)............................................................................... Figure 29.26 I2C Bus Interface Input/Output Timing ................................................................ Figure 29.27 USB Driver/Receiver Output Timing ................................................................... Figure 29.28 Multimedia Card Interface Timing ....................................................................... Figure 29.29 H-UDI ETCK Timing........................................................................................... Figure 29.30 Reset Hold Timing................................................................................................ Figure 29.31 H-UDI Input/Output Timing................................................................................. 779 782 784 785 833 833 834 835 836 836 838 838 840 841 842 843 844 845 847 847 847 848 848 848 848 849 849 849 849 851 852 853 854 855 855 Rev. 3.00 Jan 25, 2006 page xliv of lii Appendix Figure C.1 Package Dimensions (TBP-112A) ......................................................................... 864 Rev. 3.00 Jan 25, 2006 page xlv of lii Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ Table 1.2 Pin Functions.......................................................................................................... Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation ................................................................................................. Table 2.3 Data Transfer Instructions ...................................................................................... Table 2.4 Arithmetic Operations Instructions (1)................................................................... Table 2.4 Arithmetic Operations Instructions (2)................................................................... Table 2.5 Logic Operations Instructions ................................................................................ Table 2.6 Shift Instructions .................................................................................................... Table 2.7 Bit Manipulation Instructions (1) ........................................................................... Table 2.7 Bit Manipulation Instructions (2) ........................................................................... Table 2.8 Branch Instructions................................................................................................. Table 2.9 System Control Instructions ................................................................................... Table 2.10 Block Data Transfer Instructions............................................................................ Table 2.11 Addressing Modes.................................................................................................. Table 2.12 Absolute Address Access Ranges .......................................................................... Table 2.13 Effective Address Calculation (1) .......................................................................... Table 2.13 Effective Address Calculation (2) .......................................................................... 4 8 33 34 35 36 37 38 38 39 40 41 42 43 45 46 48 49 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................ 55 Table 3.2 Pin Functions in Each Operating Mode.................................................................. 61 Section 4 Exception Handling Table 4.1 Exception Types and Priority ................................................................................. 65 Table 4.2 Exception Handling Vector Table .......................................................................... 66 Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 70 Section 5 Interrupt Controller Table 5.1 Pin Configuration ................................................................................................... Table 5.2 Correspondence between Interrupt Source and ICR .............................................. Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ Table 5.4 Interrupt Control Modes......................................................................................... Table 5.5 Interrupts Acceptable in Each Interrupt Control Mode .......................................... Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode ........... Rev. 3.00 Jan 25, 2006 page xlvi of lii 75 76 87 90 91 92 Table 5.7 Table 5.8 Table 5.9 Interrupt Response Times....................................................................................... 98 Number of States in Interrupt Handling Routine Execution Status........................ 98 Interrupt Source Selection and Clearing Control.................................................... 100 Section 6 Bus Controller Table 6.1 Pin Configuration ................................................................................................... Table 6.2 Address Ranges and External Address Spaces....................................................... Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface ................................... Table 6.4 Bus Specifications for Basic Expansion Area/Basic Bus Interface ........................ Table 6.5 Bus Specifications for 256-kbyte Expansion Area/Basic Bus Interface................. Table 6.6 Bus Specifications for CP Expansion Area (Basic Mode)/Basic Bus Interface ..... Table 6.7 Bus Specifications for CF Expansion Area (Memory Card Mode)/ Basic Bus Interface................................................................................................. Table 6.8 Address Range for IOS Signal Output ................................................................... Table 6.9 Data Buses Used and Valid Strobes ....................................................................... Table 6.10 Data Buses Used and Valid Strobes ....................................................................... Table 6.11 Pin States in Idle Cycle .......................................................................................... Section 7 Data Transfer Controller (DTC) Table 7.1 Correspondence between Interrupt Sources and DTCER....................................... Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ Table 7.3 Register Functions in Normal Mode ...................................................................... Table 7.4 Register Functions in Repeat Mode ....................................................................... Table 7.5 Register Functions in Block Transfer Mode........................................................... Table 7.6 DTC Execution Status ............................................................................................ Table 7.7 Number of States Required for Each Execution Status .......................................... Section 8 RAM-FIFO Unit (RFU) Table 8.1 Valid Bits in BAR, RAR, WAR, and TMP ............................................................ Table 8.2 Correspondence between Activation Sources and ID Numbers ............................. Table 8.3 RFU Bus Cycle Types............................................................................................ Table 8.4 Requests from Peripheral Modules and RFU Bus Cycle........................................ Table 8.5 Bus Cycle Insertion ................................................................................................ Table 8.6 Settings when Using Boundary Overflow (Transmission/Reception of Single Data Block) .................................................... Table 8.7 DATAN/FREEN Read Value................................................................................. 105 115 117 118 119 120 121 122 124 138 142 150 154 157 158 159 163 163 174 183 185 186 189 192 204 Section 9 I/O Ports Table 9.1 Port Functions ........................................................................................................ 205 Table 9.2 Port 1 Input Pull-Up MOS States ........................................................................... 211 Table 9.3 Port 2 Input Pull-Up MOS States ........................................................................... 215 Rev. 3.00 Jan 25, 2006 page xlvii of lii Table 9.4 Table 9.5 Table 9.6 Port 3 Input Pull-Up MOS States ........................................................................... 222 Port 6 Input Pull-Up MOS States ........................................................................... 244 Port A Input Pull-Up MOS States .......................................................................... 257 Section 10 8-Bit PWM Timer (PWM) Table 10.1 Pin Configuration ................................................................................................... Table 10.2 Internal Clock Selection ......................................................................................... Table 10.3 Resolution, PWM Conversion Period, and Carrier Frequency when = 20 MHz................................................................................................... Table 10.4 Duty Cycle of Basic Pulse...................................................................................... Table 10.5 Position of Pulses Added to Basic Pulses............................................................... 263 265 266 270 271 Section 11 14-Bit PWM Timer (PWMX) Table 11.1 Pin Configuration ................................................................................................... 274 Table 11.2 Read and Write Access Methods for 16-Bit Registers ........................................... 280 Table 11.3 Settings and Operation (Examples when = 25 MHz) .......................................... 282 Table 11.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) ................. 286 Section 12 16-Bit Free-Running Timer (FRT) Table 12.1 Pin Configuration ................................................................................................... 289 Table 12.2 FRT Interrupt Sources ............................................................................................ 308 Table 12.3 Switching of Internal Clock and FRC Operation ................................................... 313 Section 13 8-Bit Timer (TMR) Table 13.1 Pin Configuration ................................................................................................... Table 13.2 Clock Input to TCNT and Count Condition ........................................................... Table 13.3 Input Capture Signal Selection............................................................................... Table 13.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X......... Table 13.5 Timer Output Priorities .......................................................................................... Table 13.6 Switching of Internal Clocks and TCNT Operation ............................................... Section 14 Timer Connection Table 14.1 Pin Configuration ................................................................................................... Table 14.2 Synchronization Signal Connection Enable ........................................................... Table 14.3 Registers Accessible by TMR_X/TMR_Y............................................................. Table 14.4 Examples of TCR Settings ..................................................................................... Table 14.5 Examples of TCORB (Pulse Width Threshold) Settings........................................ Table 14.6 Examples of TCR and TCSR Settings.................................................................... Table 14.7 Examples of TCR, TCSR, TOCR, and OCRDM Settings...................................... Table 14.8 Examples of TCR, TCSR, and TCORB Settings ................................................... 318 322 338 339 342 343 347 351 355 358 358 362 364 366 Rev. 3.00 Jan 25, 2006 page xlviii of lii Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF, and TOCR Settings................................................................................................. 368 Table 14.10 HSYNCO Output Modes........................................................................................ 370 Table 14.11 VSYNCO Output Modes........................................................................................ 371 Section 15 Watchdog Timer (WDT) Table 15.1 Pin Configuration ................................................................................................... 375 Table 15.2 WDT Interrupt Source............................................................................................ 382 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.1 Pin Configuration ................................................................................................... Table 16.2 Relationships between N Setting in BRR and Bit Rate B ...................................... Table 16.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ............................ Table 16.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................. Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Table 16.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372).......................................................... Table 16.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) ... Table 16.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... Table 16.11 SSR Status Flags and Receive Data Handling........................................................ Table 16.12 IrCKS2 to IrCKS0 Bit Settings .............................................................................. Table 16.13 SCI Interrupt Sources ............................................................................................. Table 16.14 SCI Interrupt Sources ............................................................................................. Section 17 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Table 17.5 Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 17.10 Table 17.11 Table 17.12 Table 17.13 I2C Bus Interface (IIC) Pin Configuration ................................................................................................... Communication Format.......................................................................................... I2C Transfer Rate.................................................................................................... Flags and Transfer States ....................................................................................... Restrictions on Accessing IIC Registers ................................................................ Operation Reservation Commands......................................................................... Operation When the Operation Reservation Command Is Completed ................... Examples of Operation Using DTC ....................................................................... Examples of Operation Reservation Adapter Operation Using DTC..................... IIC Interrupt Sources .............................................................................................. I2C Bus Timing (SCL and SDA Outputs) .............................................................. Permissible SCL Rise Time (tsr) Values................................................................. I2C Bus Timing (with Maximum Influence of tSr/tSf) ............................................. 391 405 406 409 409 410 410 411 411 418 428 458 460 460 476 481 484 490 511 513 514 532 533 540 541 542 543 Rev. 3.00 Jan 25, 2006 page xlix of lii Section 18 Universal Serial Bus Interface (USB) Table 18.1 Pin Configuration ................................................................................................... 555 Table 18.2 FIFO Configuration................................................................................................ 557 Table 18.3 Port 6 Functions ..................................................................................................... 595 Table 18.4 USB Function Core and Slave CPU Functions ...................................................... 603 Table 18.5 Packets Included in Each Transaction .................................................................... 605 Table 18.6 Registers Initialized by Bit UIFRST or FSRST ..................................................... 619 Table 18.7 Endpoint Information ............................................................................................. 622 Table 18.8 USB Interrupt Sources (When SETICNT of USBMDCR Is 0).............................. 625 Table 18.9 USB Interrupt Sources (When SETICNT of USBMDCR Is 1).............................. 625 Section 19 Multimedia Card Interface (MCIF) Table 19.1 Pin Configuration ................................................................................................... Table 19.2 Correspondence between Commands and Settings of CMDTYR and RSPTYR ... Table 19.3 CMDR Configuration............................................................................................. Table 19.4 Correspondence between Number of Command Response Bytes and RSPR Register ................................................................................................. Table 19.5 Card States in which Command Sequence Is Halted.............................................. Table 19.6 MCIF Interrupt Sources.......................................................................................... 629 634 637 639 642 687 Section 21 D/A Converter Table 21.1 Pin Configuration ................................................................................................... 692 Table 21.2 D/A Channel Enable............................................................................................... 693 Section 22 A/D Converter Table 22.1 Pin Configuration ................................................................................................... Table 22.2 Analog Input Channels and Corresponding ADDR Registers................................ Table 22.3 CIN7 to CIN0 Scan by DTC Comparator Scan Function....................................... Table 22.4 A/D Conversion Time (Single Mode) .................................................................... Table 22.5 A/D Converter Interrupt Source ............................................................................. Section 24 ROM Table 24.1 Differences between Boot Mode and User Program Mode.................................... Table 24.2 Pin Configuration ................................................................................................... Table 24.3 Operating Modes and ROM ................................................................................... Table 24.4 On-Board Programming Mode Settings ................................................................. Table 24.5 Boot Mode Operation............................................................................................. Table 24.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible............................................................................................................... 699 700 704 707 708 719 723 727 727 730 731 Rev. 3.00 Jan 25, 2006 page l of lii Section 25 User Debug Interface (H-UDI) Table 25.1 Pin Configuration ................................................................................................... 743 Table 25.2 H-UDI Register Serial Transfer.............................................................................. 744 Table 25.3 Correspondence between Pins and Boundary Scan Register.................................. 747 Section 26 Clock Pulse Generator Table 26.1 Damping Resistance Values ................................................................................... Table 26.2 Crystal Resonator Parameters................................................................................. Table 26.3 External Clock Input Conditions ............................................................................ Table 26.4 External Clock Output Stabilization Delay Time................................................... Table 26.5 Subclock Input Conditions ..................................................................................... 762 763 764 765 766 Section 27 Power-Down Modes Table 27.1 Operating Frequency and Wait Time ..................................................................... 774 Table 27.2 LSI Internal States in Each Operating Mode.......................................................... 780 Section 29 Table 29.1 Table 29.2 Table 29.2 Table 29.2 Table 29.3 Table 29.4 Table 29.5 Table 29.6 Table 29.7 Table 29.8 Table 29.9 Table 29.10 Table 29.11 Table 29.12 Table 29.13 Table 29.14 Table 29.15 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics (1) ............................................................................................ DC Characteristics (2) ............................................................................................ DC Characteristics (3) ............................................................................................ Permissible Output Currents................................................................................... I2C Bus Drive Characteristics................................................................................. USB Pin Characteristics ......................................................................................... Multimedia Card Interface Pin Characteristics....................................................... Clock Timing.......................................................................................................... Control Signal Timing............................................................................................ Bus Timing (1) (Normal Mode and Advanced Mode) ........................................... Timing of On-Chip Peripheral Modules (1) ........................................................... I2C Bus Timing....................................................................................................... USB Timing ........................................................................................................... Multimedia Card Interface ..................................................................................... H-UDI Timing........................................................................................................ A/D Conversion Characteristics (AN7 to AN2 Input: 134/266-State Conversion).................................................... Table 29.16 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) ................................................. Table 29.17 D/A Conversion Characteristics ............................................................................. Table 29.18 Flash Memory Characteristics................................................................................ 825 826 828 829 830 831 832 833 835 837 839 846 850 851 852 854 856 857 858 859 Rev. 3.00 Jan 25, 2006 page li of lii Rev. 3.00 Jan 25, 2006 page lii of lii Section 1 Overview Section 1 Overview 1.1 Features * High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 CPU and H8/300H CPU on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions Data transfer controller (DTC) RAM-FIFO unit (RFU) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) CRC operator (CRC) I2C bus interface (IIC) Universal serial bus interface (USB) Multimedia card interface (MCIF) Encryption operation circuit (DES, GF) 8-bit D/A converter 10-bit A/D converter User debug interface (H-UDI) Clock pulse generator * On-chip memory ROM F-ZTAT Version Model HD64F2158 ROM 256 kbytes RAM 10 kbytes * General I/O ports I/O pins: 65 Input-only pins: 7 * Supports various power-down modes Rev. 3.00 Jan 25, 2006 page 1 of 872 REJ09B0286-0300 Section 1 Overview * Compact package Package TFBGA-112 Code TBP-112A Body Size 10.0 x 10.0 mm Pin Pitch 0.8 mm 1.2 Internal Block Diagram VCC VCL VSS XTAL EXTAL X1 X2 MD2 MD1 MD0 RES RESO STBY FWE NMI ETRST ETMS ETDO ETDI ETCK USDP USDM Port A Port 1 Port 2 Peripheral address bus Peripheral data bus Sub address bus Sub data bus Clock pulse generator Internal data bus Internal address bus PA0/A16/KIN8/SSE0I PA1/A17/KIN9/SSE2I H8S/2000 CPU DTC Interrupt controller Bus controller P10/A0/PW0/CPA0 P11/A1/PW1/CPA1 P12/A2/PW2/CPA2 P13/A3/PW3/CPA3 P14/A4/PW4/CPA4 P15/A5/PW5/CPA5 P16/A6/PW6/CPA6 P17/A7/PW7/CPA7 P20/A8/PW8/CPA8 P21/A9/PW9/CPA9 P22/A10/PW10/CPA10 P23/A11/PW11/CPREG P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P27/A15/PW15 P30/D8/CPD8/WUE8/MCCLK P31/D9/CPD9/WUE9/MCCMD/MCTxD P32/D10/CPD10/WUE10/MCDAT/MCRxD P33/D11/CPD11/WUE11/MCDATDIR/MCCSA P34/D12/CPD12/WUE12/MCCMDDIR/MCCSB P35/D13/CPD13/WUE13 P36/D14/CPD14/WUE14 P37/D15/CPD15/WUE15 P50/IRQ8/TxD0 P51/IRQ9/RxD0 P52/IRQ10/TxD1/IrTxD P53/IRQ11/RxD1/IrRxD P54/IRQ12/TxD2 P55/IRQ13/RxD2 P56/IRQ14/PWX0 P57/IRQ15/PWX1 P40/IRQ0/TMI0/ExMCCLK P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI P42/IRQ2/TMO0/ExMCDAT/ExMCRxD P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB P45/IRQ5/TMIY P46/IRQ6/TMOX P47/IRQ7/TMOY RFU LWR/P90 CPCS2/P91 CPCS1/P92 CPOE/RD/P93 CPWE/HWR/P94 IOS/AS/P95 EXCL//P96 CS256/CPWAIT/WAIT/P97 SPEED/HFBACKI/DBA_S/KIN0/CIN0/FTCI/CPD0/D0/P60 SUSPEND/VSYNCO/DBA_R/KIN1/CIN1/FTOA/CPD1/D1/P61 TXENL/VSYNCI/DBB_S/KIN2/CIN2/FTIA/CPD2/D2/P62 TXDMNS/VFBACKI/DBB_R/KIN3/CIN3/FTIB/CPD3/D3/P63 TXDPLS/CLAMPO/DBC_S/KIN4/CIN4/FTIC/CPD4/D4/P64 XVERDATA/CSYNCI/DBC_R/KIN5/CIN5/FTID/CPD5/D5/P65 DMNS/CBLANK/DBD_S/KIN6/CIN6/FTOB/CPD6/D6/P66 DPLS/DBD_R/KIN7/CIN7/CPD7/D7/P67 RAM 8-bit PWM 14-bit PWM x 2 channels Port 9 ROM WDT x 2 channels 16-bit FRT 8-bit timer x 4 channels Timer connection Port 6 SCI x 3 channels (IrDA x 1 channel) 10-bit A/D MCIF CRC operator Port 5 Port 4 8-bit D/A AN2/ExIRQ2/P72 AN3/ExIRQ3/P73 AN4/ExIRQ4/P74 AN5/ExIRQ5/P75 DA0/AN6/ExIRQ6/P76 DA1/AN7/ExIRQ7/P77 DES Port 7 IIC x 2 channels GF USB AVCC/DrVCC AVref AVSS/DrVSS Port 8 SCL0/ExIRQ8/P80 SDA0/ExIRQ9/P81 SCL1/ExIRQ10/P82 SDA1/ExIRQ11/P83 ExTMI0/SCK0/ExIRQ12/P84 ExTMI1/SCK1/ExIRQ13/P85 ExTMIX/SCK2/ExIRQ14/P86 USEXCL/ExTMIY/ADTRG/ExIRQ15/P87 Figure 1.1 Internal Block Diagram Rev. 3.00 Jan 25, 2006 page 2 of 872 REJ09B0286-0300 Port 3 Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement 1 2 3 4 5 6 7 8 9 1011 A B C D E F G H J K L Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 TBP-112A (Top View) Pin Name (Reserved) FWE P83/ExIRQ11/SDA1 P80/ExIRQ8/SCL0 P84/ExIRQ12/SCK0/ExTMI0 P36/D14/CPD14/WUE14 P33/D11/CPD11/WUE11/MCDATDIR/MCCSA P30/D8/CPD8/WUE8/MCCLK P87/ExIRQ15/ADTRG/ExTMIY/USEXCL Pin No. E1 E2 E3 E4 Pin Name X1 X2 VCL STBY Pin No. J1 J2 J3 J4 J5 J6 J7 Pin Name P57/IRQ15/PWX1 P92/CPCS1 P90/LWR ETCK P67/D7/CPD7/CIN7/KIN7/DPLS AVCC/DrVCC P75/ExIRQ5/AN5 PA1/A17/KIN9/SSE2I P55/IRQ13/RxD2 E8 E9 VSS ETMS J8 J9 A10 P12/A2/PW2/CPA2 A11 (Reserved) B1 B2 B3 B4 B5 B6 B7 B8 B9 E10 P20/A8/PW8/CPA8 E11 P21/A9/PW9/CPA9 F1 F2 F3 F4 J10 P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO J11 P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB K1 P91/CPCS2 K2 P60/D0/CPD0/FTCI/CIN0/KIN0/HFBACKI/SPEED K3 P63/D3/CPD3/FTIB/CIN3/KIN3/VFBACKI/TXDMNS K4 P64/D4/CPD4/FTIC/CIN4/KIN4/CLAMPO/TXDPLS K5 AVCC/DrVCC K6 USDM K7 P74/ExIRQ4/AN4 XTAL RES P53/IRQ11/RxD1/IrRxD P82/ExIRQ10/SCL1 VSS P37/D15/CPD15/WUE15 P34/D12/CPD12/WUE12/MCCMDDIR/MCCSB (Reserved) P10/A0/PW0/CPA0 P51/IRQ9/RxD0 P50/IRQ8/TxD0 ETRST VSS F8 F9 P22/A10/PW10/CPA10 P25/A13/PW13 K8 AVSS/DrVSS K9 PA0/A16/KIN8/SSE0I K10 P40/IRQ0/TMI0/ExMCCLK K11 P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI L1 (Reserved) L2 P61/D1/CPD1/FTOA/CIN1/KIN1/VSYNCO/SUSPEND L3 ETDI L4 P65/D5/CPD5/FTID/CIN5/KIN5/CSYNCI/XVERDATA L5 AVref L6 USDP L7 P73/ExIRQ3/AN3 B10 P13/A3/PW3/CPA3 B11 P15/A5/PW5/CPA5 C1 MD2 C2 EXTAL C3 RESO C4 P52/IRQ10/TxD1/IrTxD C5 VSS C6 P35/D13/CPD13/WUE13 C7 P32/D10/CPD10/WUE10/MCDAT/MCRxD C8 P86/ExIRQ14/SCK2/ExTMIX C9 P14/A4/PW4/CPA4 C10 P16/A6/PW6/CPA6 C11 VSS D1 NMI D2 MD0 D3 MD1 D4 (Reserved) D5 P81/ExIRQ9/SDA0 D6 P85/ExIRQ13/SCK1/ExTMI1 D7 P31/D9/CPD9/WUE9/MCCMD/MCTxD D8 P11/A1/PW1/CPA1 D9 P17/A7/PW7/CPA7 D10 VSS D11 ETDO F10 P23/A11/PW11/CPREG F11 P24/A12/PW12 G1 G2 G3 G4 VSS P97/WAIT/CPWAIT/CS256 P96//EXCL P94/HWR/CPWE G8 G9 VCC VCC L8 P76/ExIRQ6/AN6/DA0 L9 AVSS/DrVSS L10 P54/IRQ12/TxD2 L11 (Reserved) G10 P26/A14/PW14 G11 P27/A15/PW15 H1 H2 H3 H4 H5 H6 H7 H8 H9 P95/AS/IOS P56/IRQ14/PWX0 P93/RD/CPOE P62/D2/CPD2/FTIA/CIN2/KIN2/VSYNCI/TXENL P66/D6/CPD6/FTOB/CIN6/KIN6/CBLANK/DMNS P72/ExIRQ2/AN2 P77/ExIRQ7/AN7/DA1 P42/IRQ2/TMO0/ExMCDAT/ExMCRxD P45/IRQ5/TMIY H10 P46/IRQ6/TMOX H11 P47/IRQ7/TMOY Figure 1.2 Pin Arrangement (TBP-112A: Top View) Rev. 3.00 Jan 25, 2006 page 3 of 872 REJ09B0286-0300 Section 1 Overview 1.3.2 Table 1.1 Pin No. Pin Arrangement in Each Operating Mode Pin Arrangement in Each Operating Mode Pin Name Extended Mode Single-Chip Mode Modes 2 and 3 (EXPE = 0) RES XTAL EXTAL MD2 MD1 MD0 NMI STBY VCL X1 X2 ETRST P51/IRQ9/RxD0 P50/IRQ8/TxD0 VSS P97 P96//EXCL P95 P94 P56/IRQ14/PWX0 P57/IRQ15/PWX1 P93 P92 P91 P90 2 D0/CPD0* TBP-112A B2 B1 C2 C1 D3 D2 D1 E4 E3 E1 E2 F3 F1 F2 F4, G1 G2 G3 H1 G4 H2 J1 H3 J2 K1 J3 K2 Modes 2 and 3 (EXPE = 1) RES XTAL EXTAL MD2 MD1 MD0 NMI STBY VCL X1 X2 ETRST P51/IRQ9/RxD0 P50/IRQ8/TxD0 VSS P97/WAIT/CPWAIT/CS256 P96//EXCL AS/IOS HWR/CPWE P56/IRQ14/PWX0 P57/IRQ15/PWX1 RD/CPOE P92/CPCS1 P91/CPCS2 P90/LWR P60/FTCI/CIN0/ 1 KIN0/HFBACKI* Flash Memory Programmer Mode RES XTAL EXTAL VCC VSS VSS FA9 VCC VCL NC NC VSS FA17 NC VSS VCC NC FA16 FA15 NC NC WE VSS VCC VCC NC P60/FTCI/CIN0/KIN0/ HFBACKI/SPEED Rev. 3.00 Jan 25, 2006 page 4 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Extended Mode TBP-112A L2 H4 K3 L3 J4 K4 L4 H5 J5 L5 K5, J6 L6 K6 H6 L7 K7 J7 L8 H7 K8, L9 J8 K9 L10 J9 Modes 2 and 3 (EXPE = 1) P61/FTOA/CIN1/ 1 KIN1/VSYNCO* P62/FTIA/CIN2/ 1 KIN2/VSYNCI* P63/FTIB/CIN3/ 1 KIN3/VFBACKI* ETDI ETCK P64/FTIC/CINk4/ 1 KIN4/CLAMPO* P65/FTID/CIN5/ 1 KIN5/CSYNCI* P66/FTOB/CIN6/ 1 KIN6/CBLANK* P67/CIN7/KIN7* AVref AVCC/DrVCC USDP USDM P72/ExIRQ2/AN2 P73/ExIRQ3/AN3 P74/ExIRQ4/AN4 P75/ExIRQ5/AN5 P76/ExIRQ6/AN6/DA0 P77/ExIRQ7/AN7/DA1 AVSS/DrVSS PA1/A17/KIN9/ 3 SSE2I* PA0/A16/KIN8/ 3 SSE0I* P54/IRQ12/TxD2 P55/IRQ13/RxD2 PA1/KIN9/ 4 SSE2I* PA0/KIN8/ 4 SSE0I* 1 Pin Name Single-Chip Mode Modes 2 and 3 (EXPE = 0) D1/CPD1* D2/CPD2* D3/CPD3* 2 Flash Memory Programmer Mode NC NC NC NC NC NC NC NC VSS VCC VCC NC NC NC NC NC NC NC NC VSS NC NC NC NC P61/FTOA/CIN1/KIN1/ VSYNCO/SUSPEND P62/FTIA/CIN2/KIN2/ VSYNCI/TXENL P63/FTIB/CIN3/KIN3/ VFBACKI/TXDMNS ETDI ETCK 2 2 D4/CPD4* D5/CPD5* D6/CPD6* D7/CPD7* 2 P64/FTIC/CIN4/KIN4/ CLAMPO/TXDPLS P65/FTID/CIN5/KIN5/ CSYNCI/XVERDATA P66/FTOB/CIN6/KIN6/ CBLANK/DMNS P67/CIN7/KIN7/DPLS AVref AVCC/DrVCC USDP USDM P72/ExIRQ2/AN2 P73/ExIRQ3/AN3 P74/ExIRQ4/AN4 P75/ExIRQ5/AN5 P76/ExIRQ6/AN6/DA0 P77/ExIRQ7/AN7/DA1 AVSS/DrVSS PA1/KIN9/SSE2I PA0/KIN8/SSE0I P54/IRQ12/TxD2 P55/IRQ13/RxD2 2 2 2 Rev. 3.00 Jan 25, 2006 page 5 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Extended Mode TBP-112A K10 K11 H8 J10 Modes 2 and 3 (EXPE = 1) P40/IRQ0/TMI0/ExMCCLK P41/IRQ1/TMI1/ExMCCMD/ ExMCTxD/HSYNCI P42/IRQ2/TMO0/ExMCDAT/ ExMCRxD P43/IRQ3/TMO1/ ExMCDATDIR/ExMCCSA/ HSYNCO P44/IRQ4/TMIX/ ExMCCMDDIR/ExMCCSB P45/IRQ5/TMIY P46/IRQ6/TMOX P47/IRQ7/TMOY VCC P27/A15 P26/A14 P25/A13 P24/A12 P23/A11/CPREG P22/A10/CPA10 P21/A9/CPA9 P20/A8/CPA8 ETMS ETDO VSS VSS P17/A7/CPA7 P16/A6/CPA6 P15/A5/CPA5 P14/A4/CPA4 P13/A3/CPA3 Pin Name Single-Chip Mode Modes 2 and 3 (EXPE = 0) P40/IRQ0/TMI0/ExMCCLK P41/IRQ1/TMI1/ExMCCMD/ ExMCTxD/HSYNCI P42/IRQ2/TMO0/ExMCDAT/ ExMCRxD P43/IRQ3/TMO1/ ExMCDATDIR/ExMCCSA/ HSYNCO P44/IRQ4/TMIX/ ExMCCMDDIR/ExMCCSB P45/IRQ5/TMIY P46/IRQ6/TMOX P47/IRQ7/TMOY VCC P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 ETMS ETDO VSS VSS P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 Flash Memory Programmer Mode NC NC NC NC J11 H9 H10 H11 G8, G9 G11 G10 F9 F11 F10 F8 E11 E10 E9 D11 E8, D10 C11 D9 C10 B11 C9 B10 NC NC NC NC VCC CE FA14 FA13 FA12 FA11 FA10 OE FA8 NC NC VSS VSS FA7 FA6 FA5 FA4 FA3 Rev. 3.00 Jan 25, 2006 page 6 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Extended Mode TBP-112A A10 D8 B9 A9 C8 A8 D7 C7 A7 B7 C6 A6 B6 D6 A5 B5, C5 A4 D5 B4 A3 C4 B3 A2 C3 Notes: 1. 2. 3. 4. Modes 2 and 3 (EXPE = 1) P12/A2/CPA2 P11/A1/CPA1 P10/A0/CPA0 P87/ExIRQ15/ADTRG/ExTMIY/ USEXCL P86/ExIRQ14/SCK2/ExTMIX D8/CPD8 D9/CPD9 D10/CPD10 D11/CPD11 D12/CPD12 D13/CPD13 D14/CPD14 D15/CPD15 P85/ExIRQ13/SCK1/ExTMI1 P84/ExIRQ12/SCK0/ExTMI0 VSS P80/ExIRQ8/SCL0 P81/ExIRQ9/SDA0 P82/ExIRQ10/SCL1 P83/ExIRQ11/SDA1 P52/IRQ10/TxD1/IrTxD P53/IRQ11/RxD1/IrRxD FWE RESO 8-bit data bus 16-bit data bus Extended mode (mode 2) Extended mode (mode 3) Pin Name Single-Chip Mode Modes 2 and 3 (EXPE = 0) P12/PW2 P11/PW1 P10/PW0 Flash Memory Programmer Mode FA2 FA1 FA0 P87/ExIRQ15/ADTRG/ExTMIY/ NC USEXCL P86/ExIRQ14/SCK2/ExTMIX P30/WUE8/MCCLK P31/WUE9/MCCMD/MCTxD P32/WUE10/MCDAT/MCRxD P33/WUE11/MCDATDIR/ MCCSA P34/WUE12/MCCMDDIR/ MCCSB P35/WUE13 P36/WUE14 P37/WUE15 P85/ExIRQ13/SCK1/ExTMI1 P84/ExIRQ12/SCK0/ExTMI0 VSS P80/ExIRQ8/SCL0 P81/ExIRQ9/SDA0 P82/ExIRQ10/SCL1 P83/ExIRQ11/SDA1 P52/IRQ10/TxD1/IrTxD P53/IRQ11/RxD1/IrRxD FWE RESO NC FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 NC NC VSS NC NC NC NC FA18 NC FWE NC Rev. 3.00 Jan 25, 2006 page 7 of 872 REJ09B0286-0300 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. Type Power supply Symbol VCC VCL VSS TBP-112A G8, G9 E3 F4, G1 E8, D10 C11, B5 C5 B1 C2 I/O Input Input Input Name and Function Power supply pins. Connect all these pins to the system power supply. Power supply pin. Connect this pin to VCC. Ground pins. Connect all these pins to the system power supply (0 V). Clock XTAL EXTAL Input Input For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For an example of crystal resonator connection, see section 26, Clock Pulse Generator. Supplies the system clock to external devices. 32.768-kHz external clock for subclock should be supplied. For connection to a crystal resonator. An external clock can be supplied from the X2 pin. For an example of crystal resonator connection, see section 26, Clock Pulse Generator. These pins set the operating mode. Inputs at these pins should not be changed during operation. Reset pin. When this pin is low, the chip is reset. Outputs a reset signal to an external device. When this pin is low, a transition is made to hardware standby mode. Pin for use by flash memory. EXCL X1 X2 G3 G3 E1 E2 Output Input Input Input Operating mode control System control MD2 MD1 MD0 RES RESO STBY FWE C1 D3 D2 B2 C3 E4 A2 Input Input Output Input Input Rev. 3.00 Jan 25, 2006 page 8 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type Address bus Symbol A17 to A0 TBP-112A J8, K9 G11, G10 F9, F11 F10, F8 E11, E10 D9, C10 B11, C9 B10, A10 D8, B9 B6, A6 C6, B7 A7, C7 D7, A8 J5, H5 L4, K4 K3, H4 L2, K2 F10 F8, E11 E10, D9 C10, B11 C9, B10 A10, D8 B9 B6, A6 C6, B7 A7, C7 D7, A8 J5, H5 L4, K4 K3, H4 L2, K2 K1 J2 G2 H3 G4 Output I/O Output Name and Function Address output pins Data bus D15 to D8 Input/ Output Upper bidirectional data bus D7 to D0 Lower bidirectional data bus CompactFlash control CPREG CPA10 to CPA0 CompactFlash address output pins CPD15 to CPD0 Input/ Output CompactFlash bidirectional data bus CPCS2 CPCS1 CPWAIT CPOE CPWE Output Input Output Output CompactFlash chip select output pins CompactFlash wait input pin CompactFlash output enable output pin CompactFlash write enable output pin Rev. 3.00 Jan 25, 2006 page 9 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type Bus control Symbol WAIT TBP-112A G2 I/O Input Name and Function Requests insertion of a wait state in the bus cycle when accessing an external 3state address space. This pin is low when the external address space is being read from. This pin is low when the external address space is being written to, and the upper half of the data bus is enabled. This pin is low when the external space is being written to, and the lower half of the data bus is enabled. This pin is low when address output on the address bus is valid. Indicates that the 256-kbyte area from H'F80000 to H'FBFFFF is accessed. Nonmaskable interrupt request input pin These pins request a maskable interrupt. Selectable to which pin of IRQn or ExIRQn to insert IRQ15 to IRQ0 interrupts. RD HWR H3 G4 Output Output LWR J3 Output AS/IOS CS256 Interrupts NMI IRQ15 to IRQ0 H1 G2 D1 J1, H2 J9, L10 B3, C4 F1, F2 H11, H10 H9, J11 J10, H8 K11, K10 A9, C8 D6, A5 A3, B4 D5, A4 H7, L8 J7, K7 L7, H6 F3 E9 D11 L3 J4 Output Output Input Input ExIRQ15 to ExIRQ2 On-chip emulator ETRST ETMS ETDO ETDI ETCK Input Input Output Input Input On-chip emulator interface pins Rev. 3.00 Jan 25, 2006 page 10 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type PWM timer (PWM) Symbol PW15 to PW0 TBP-112A G11, G10 F9, F11 F10, F8 E11, E10 D9, C10 B11, C9 B10, A10 D8, B9 J1 H2 K2 L2 H5 H4, K3 K4, L4 H8 J10 H10 H11 K10 K11 J11 H9 A5 D6 C8 A9 H4 K11 L4 K3 K2 L2 J10 K4 H5 I/O Output Name and Function PWM timer pulse output pins 14-bit PWM timer (PWMX) 16-bit free running timer (FRT) PWX1 PWX0 FTCI FTOA FTOB FTIA to FTID Output PWMX (D/A) pulse output pins Input Output Output Input Output External event input pin Output compare output pins Input capture input pins Waveform output pins with output compare function 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) TMO0 TMO1 TMOX TMOY TMI0 TMI1 TMIX TMIY ExTMI0 ExTMI1 ExTMIX ExTMIY VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI VSYNCO HSYNCO CLAMPO CBLANK Input External event input pins and counter reset input pins. Selectable to which pin of TMIn or ExTMIn to insert external event and counter reset. Timer connection Input Timer connection synchronization signal input pins Output Timer connection synchronization signal output pins Rev. 3.00 Jan 25, 2006 page 11 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type Serial communication Interface (SCI_0, SCI_1, SCI_2) Symbol TxD0 to TxD2 RxD0 to RxD2 SCK0 to SCK2 SSE0I SSE2I SCI with IrDA (SCI) I C bus interface (IIC) 2 TBP-112A F2, C4 L10 F1, B3 J9 A5, D6 C8 K9 J8 C4 B3 A4 B4 D5 A3 J8, K9 J5, H5 L4, K4 K3, H4 L2, K2 I/O Output Input Input/ Output Input Input Output Input Input/ Output Input/ Output Input Name and Function Transmit data output pins Receive data input pins Clock input/output pins. Output format is NMOS push-pull output. Input pin to halt SCI_0 Input pin to halt SCI_2 Encoded data output pin for IrDA Encoded data input pin for IrDA IIC clock input/output pins. These pins can drive a bus directly with the NMOS open drain output. IIC data input/output pins. These pins can drive a bus directly with the NMOS open drain output. Keyboard matrix input pins. All pins have a wake-up function. Normally, KIN9 to KIN0 function as key scan inputs, and P17 to P10 and P27 to P20 function as key scan outputs. Thus, at a maximum of 16 outputs x 8 inputs, 128-key matrix can be configured. Wake-up event input pins. Same wake up as key wake up can be performed with various sources. Analog input pins IrTxD IrRxD SCL0 SCL1 SDA0 SDA1 Keyboard control KIN9 to KIN0 WUE15 to WUE8 B6, A6 C6, B7 A7, C7 D7, A8 H7, L8 J7, K7 L7, H6 J5, H5 L4, K4 K3, H4 L2, K2 A9 H7 L8 Input A/D converter AN7 to AN2 Input CIN7 to CIN0 Input Extended A/D conversion input pins ADTRG D/A converter DA1 DA0 Input Output External trigger input pin to start A/D conversion Analog output pins Rev. 3.00 Jan 25, 2006 page 12 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type A/D converter D/A converter Symbol AVCC TBP-112A K5, J6 I/O Input Name and Function Analog power supply pins for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, these pins should be connected to the system power supply. These pins are used with the USB internal driver/receiver power supply, and should therefore be connected to a power supply of 3.3 V 0.3 V whenever the USB is used. Reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply. Ground pins for the A/D converter and D/A converter. These pins should be connected to the system power supply (0 V). USB serial data I/O pins USB external clock input pin These pins should be connected to the internal driver/receiver power supply (3.3 V 0.3 V). These pins should be connected to the internal driver/receiver power supply (0 V). External driver/receiver connection signals. These pins are for connection to a driver/receiver compatible with PDIUSBP11A manufactured by Philips Electronics. AVref L5 Input AVSS K8, L9 Input Universal serial bus (USB) USDP USDM USEXCL DrVCC L6 K6 A9 K5, J6 Input/ Output Input Input DrVSS K8, L9 Input SPEED SUSPEND TXENL TXDMNS TXDPLS XVERDATA DMNS DPLS K2 L2 H4 K3 K4 L4 H5 J5 Output Output Output Output Output Input Input Input Rev. 3.00 Jan 25, 2006 page 13 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type Multimedia card interface (MCIF) Symbol ExMCCLK MCCLK ExMCTxD MCTxD ExMCRxD MCRxD ExMCCSA ExMCCSB MCCSA MCCSB ExMCCMD MCCMD ExMCDAT MCDAT ExMCDATDIR ExMCCMDDIR MCDATDIR MCCMDDIR I/O ports P17 to P10 TBP-112A K10 A8 K11 D7 H8 C7 J10 J11 A7 B7 K11 D7 H8 C7 J10 J11 A7 B7 D9, C10 B11, C9 B10, A10 D8, B9 G11, G10 F9, F11 F10, F8 E11, E10 B6, A6 C6, B7 A7, C7 D7, A8 H11, H10 H9, J11 J10, H8 K11, K10 J1, H2 J9, L10 B3, C4 F1, F2 I/O Output Output Input Output Name and Function Common clock output pins for MMC mode*/SPI mode Command/data output pins in SPI mode Response/data input pins in SPI mode Chip select output pins to select multimedia card in SPI mode Input/ Output Input/ Output Output Command output/response input pins in MMC mode* Data I/O pins in MMC mode* Output pins indicating I/O direction of MCCMD and MCDAT pins Input/ Output Eight input/output pins P27 to P20 Input/ Output Eight input/output pins P37 to P30 Input/ Output Eight input/output pins P47 to P40 Input/ Output Eight input/output pins P57 to P50 Input/ Output Eight input/output pins Rev. 3.00 Jan 25, 2006 page 14 of 872 REJ09B0286-0300 Section 1 Overview Pin No. Type I/O ports Symbol P67 to P60 TBP-112A J5, H5 L4, K4 K3, H4 L2, K2 H7, L8 J7, K7 L7, H6 A9, C8 D6, A5 A3, B4 D5, A4 G2, G3 H1, G4 H3, J2 K1, J3 J8, K9 I/O Input/ Output Name and Function Eight input/output pins P77 to P72 Input Six input pins P87 to P80 Input/ Output Eight input/output pins P97 to P90 Input/ Output Eight input/output pins. Note that pin P96 cannot be used as a general output port. PA1, PA0 Note: * Input/ Output Two input/output pins MMC mode is MultiMediaCard mode. Rev. 3.00 Jan 25, 2006 page 15 of 872 REJ09B0286-0300 Section 1 Overview Rev. 3.00 Jan 25, 2006 page 16 of 872 REJ09B0286-0300 Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. 2.1 Features * Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B) CPUS210A_000020020300 Rev. 3.00 Jan 25, 2006 page 17 of 872 REJ09B0286-0300 Section 2 CPU 16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Rev. 3.00 Jan 25, 2006 page 18 of 872 REJ09B0286-0300 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. * Extended address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. Rev. 3.00 Jan 25, 2006 page 19 of 872 REJ09B0286-0300 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. * Address space Linear access to a maximum address space of 64 kbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) * Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. Rev. 3.00 Jan 25, 2006 page 20 of 872 REJ09B0286-0300 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 3.00 Jan 25, 2006 page 21 of 872 REJ09B0286-0300 Section 2 CPU 2.2.2 Advanced Mode * Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 3.00 Jan 25, 2006 page 22 of 872 REJ09B0286-0300 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. * Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 3.00 Jan 25, 2006 page 23 of 872 REJ09B0286-0300 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. H'0000 64 kbytes H'FFFF H'00000000 16 Mbytes Program area H'00FFFFFF Data area Not available in this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.5 Memory Map Rev. 3.00 Jan 25, 2006 page 24 of 872 REJ09B0286-0300 Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers 23 PC 0 EXR* T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: : Stack pointer SP : Program counter PC EXR : Extended control register T : Trace bit I2 to I0 : Interrupt mask bits CCR : Condition-code register : Interrupt mask bit I UI : User bit or interrupt mask bit H U N Z V C : Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag Note: * Does not affect operation in this LSI. Figure 2.6 CPU Internal Registers Rev. 3.00 Jan 25, 2006 page 25 of 872 REJ09B0286-0300 Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 3.00 Jan 25, 2006 page 26 of 872 REJ09B0286-0300 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI. Bit 7 Bit Name T Initial Value R/W 0 R/W Description Trace Bit Does not affect operation in this LSI. 6 to 3 -- All 1 R Reserved These bits are always read as 1. 2 1 0 I2 I1 I0 1 1 1 R/W Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI. Rev. 3.00 Jan 25, 2006 page 27 of 872 REJ09B0286-0300 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Rev. 3.00 Jan 25, 2006 page 28 of 872 REJ09B0286-0300 Section 2 CPU Bit 1 Bit Name V Initial Value Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 3.00 Jan 25, 2006 page 29 of 872 REJ09B0286-0300 Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type 1-bit data Register Number RnH Data Image 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 3.00 Jan 25, 2006 page 30 of 872 REJ09B0286-0300 Section 2 CPU Data Type Word data Register Number Rn Data Image 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.00 Jan 25, 2006 page 31 of 872 REJ09B0286-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Image 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M + 1 MSB LSB Longword data Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 MSB LSB Figure 2.10 Memory Data Formats Rev. 3.00 Jan 25, 2006 page 32 of 872 REJ09B0286-0300 Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* 2 LDM, STM* Size B/W/L W/L L 3 Types 5 MOVFPE* , MOVTPE* 3 B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L B -- -- -- 4 8 14 5 9 1 19 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 4 BCC* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP Block data transfer EEPMOV Total: 65 Legend: B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register. 3. Cannot be used in this LSI. 4. BCC is the general name for conditional branch instructions. Rev. 3.00 Jan 25, 2006 page 33 of 872 REJ09B0286-0300 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Jan 25, 2006 page 34 of 872 REJ09B0286-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* 1 Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. B/W/L MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM* STM 2 L L @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. *2 Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register. Rev. 3.00 Jan 25, 2006 page 35 of 872 REJ09B0286-0300 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Jan 25, 2006 page 36 of 872 REJ09B0286-0300 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS Note: * B @ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Jan 25, 2006 page 37 of 872 REJ09B0286-0300 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of data in a general register. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Jan 25, 2006 page 38 of 872 REJ09B0286-0300 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ( of ) C Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ( of ) C Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ( of ) C Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ( of ) C Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 3.00 Jan 25, 2006 page 39 of 872 REJ09B0286-0300 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( of ) C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ( of ) C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 3.00 Jan 25, 2006 page 40 of 872 REJ09B0286-0300 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Condition Always Never CZ=0 CZ=1 C=0 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 3.00 Jan 25, 2006 page 41 of 872 REJ09B0286-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC ORC XORC B B B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP Note: * -- PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev. 3.00 Jan 25, 2006 page 42 of 872 REJ09B0286-0300 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next: if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields, and some have no register field. * Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions. Rev. 3.00 Jan 25, 2006 page 43 of 872 REJ09B0286-0300 Section 2 CPU (1) Operation field only op NOP, RTS (2) Operation field and register fields op rn rm ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev. 3.00 Jan 25, 2006 page 44 of 872 REJ09B0286-0300 Section 2 CPU Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register Indirect with Post-Increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Rev. 3.00 Jan 25, 2006 page 45 of 872 REJ09B0286-0300 Section 2 CPU Register Indirect with Pre-Decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Rev. 3.00 Jan 25, 2006 page 46 of 872 REJ09B0286-0300 Section 2 CPU 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, see section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode Rev. 3.00 Jan 25, 2006 page 47 of 872 REJ09B0286-0300 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect (@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 3.00 Jan 25, 2006 page 48 of 872 REJ09B0286-0300 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Rev. 3.00 Jan 25, 2006 page 49 of 872 REJ09B0286-0300 Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, see section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In a product which has a bus master other than the CPU, such as a data transfer controller (DTC) and a RAM-FIFO unit (RFU), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 27, Power-Down Modes. Rev. 3.00 Jan 25, 2006 page 50 of 872 REJ09B0286-0300 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 27, Power-Down Modes. Figure 2.13 State Transitions Rev. 3.00 Jan 25, 2006 page 51 of 872 REJ09B0286-0300 Section 2 CPU 2.9 2.9.1 Usage Notes Note on TAS Instruction Usage The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. The TAS instruction can be used as a user-defined intrinsic function. 2.9.2 Note on Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Example: The BCLR instruction is executed for DDR in port 4. P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at P46. P45 to P40 are output pins and output low-level signals. The following shows an example in which P40 is set to be an input pin with the BCLR instruction. Prior to executing BCLR P47 Input/output Pin state DDR DR Input Low level 0 1 P46 Input High level 0 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Output Low level 1 0 Rev. 3.00 Jan 25, 2006 page 52 of 872 REJ09B0286-0300 Section 2 CPU BCLR instruction executed BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4 After executing BCLR P47 Input/output Pin state DDR DR Output Low level 1 1 P46 Output High level 1 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Input High level 0 0 [Description on Operation] 1. When the BCLR instruction is executed, first the CPU reads P4DDR. Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a value of H'3F, but the value read by the CPU is H'FF. 2. The CPU clears bit 0 of the read data to 0, changing data to H'FE. 3. The CPU writes H'FE to DDR, completing execution of BCLR. As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin. However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins. Rev. 3.00 Jan 25, 2006 page 53 of 872 REJ09B0286-0300 Section 2 CPU 2.9.3 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction that transfers the byte size of data indicated by R4*1, which starts from the address indicated by ER5, to the address indicated by ER6. ER5 ER6 ER5 + R4*1 ER6 + R4*1 2. Set R4*1 and ER6 so that the end address of the destination address (value of ER6 + R4*1) does not exceed H'00FFFFFF*2 (the value of ER6 must not change from H'00FFFFFF to H'01000000*2 during execution). ER5 ER6 ER5 + R4*1 *2 Invalid H'FFFFFF ER6 + R4*1 Notes: 1. In normal mode, it becomes R4L. 2. In normal mode, it should not exceed H'0000FFFF. Rev. 3.00 Jan 25, 2006 page 54 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection MCU CPU Operating Operating Mode Description MD2 MD1 MD0 Mode 2 3 1 1 1 1 0 1 Advanced mode Normal mode Extended mode with on-chip ROM Single-chip mode Extended mode with on-chip ROM Single-chip mode On-Chip ROM Enabled Enabled Modes 2 and 3 are single-chip mode after a reset. The CPU can switch to extended mode by setting bit EXPE in MDCR to 1. Modes 0, 1, and 5 cannot be used in this LSI. Modes 4, 6, and 7 are specific modes. Thus, mode pins should be set to enable mode 2 or 3 in normal program execution state. Mode pins should not be changed during operation. Mode 4 is a boot mode to write/erase the flash memory. For details, see section 24, ROM. Modes 6 and 7 are on-chip emulation modes. These modes are controlled by the on-chip emulator (E10A) via the JTAG interface, and on-chip emulation can be performed. 3.2 Register Descriptions The following registers are related to the operating mode. For details on the bus control register (BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2 (BCR2), see section 6.3.2, Bus Control Register 2 (BCR2). * Mode control register (MDCR) * System control register (SYSCR) * Serial timer control register (STCR) Rev. 3.00 Jan 25, 2006 page 55 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit 7 Bit Name EXPE Initial Value 0 R/W R/W Description Extended Mode Enable Specifies extended mode. 0: Single-chip mode 1: Extended mode 6 to 3 2 1 0 -- All 0 R Reserved MDS2 MDS1 MDS0 --* --* --* R R R Mode Select 2 to 0 These bits indicate the input levels at mode pins (MD2, MD1, and MD0) (the current operating mode). Bits MDS2, MDS1, and MDS0 correspond to MD2, MD1, and MD0, respectively. MDS2 to MDS0 are read-only bits and they cannot be written to. The mode pin (MD2, MD1, and MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * The initial values are determined by the settings of the MD2, MD1, and MD0 pins. Rev. 3.00 Jan 25, 2006 page 56 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit 7 Bit Name CS256E Initial Value 0 R/W R/W Description Chip Select 256 Enable Enables or disables P97/WAIT/CPWAIT/CS256 pin function in extended mode. 0: P97/WAIT/CPWAIT pin WAIT/CPWAIT pin function is selected by the settings of WSCR and WSCR2. 1: CS256 pin Outputs low when a specified address of addresses H'F80000 to H'FBFFFF is accessed. 6 IOSE 0 R/W IOS Enable Enables or disables AS/IOS pin function in extended mode. 0: AS pin Outputs low when an external area is accessed. 1: IOS pin Outputs low when a specified address of addresses H'(FF)F000 to H'(FF)F7FF is accessed. 5 4 INTM1 INTM0 0 0 R R/W These bits select the control mode of the interrupt controller. For details on the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset This bit indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows. 1: A reset is caused by an external reset. Rev. 3.00 Jan 25, 2006 page 57 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes Bit 2 Bit Name NMIEG Initial Value 0 R/W R/W Description NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input 1 KINWUE 0 R/W Keyboard Control Register Access Enable Enables or disables CPU access for input control registers (KMIMRA, KMIMR6, WUEMR3) of KINn and WUEn pins, input pull-up MOS control register (KMPCR6) of the KINn pin, registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, TCORB_X) of 8-bit timers (TMR_X, TMR_Y), and timer connection registers (TCONRI, TCONRO, TCONRS, SEDGR). 0: Enables CPU access for registers of TMR_X and TMR_Y and timer connection registers in an area from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF. 1: Enables CPU access for input control registers of the KINn and WUEn pins and the input pull-up MOS control register of the KINn pin in an area from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF. 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 3.00 Jan 25, 2006 page 58 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit 7 6 5 Bit Name -- IICX1 IICX0 Initial Value 0 0 0 R/W R/(W) R/W R/W Description Reserved The initial value should not be changed. IIC Transfer Rate Select 1 and 0 These bits control the IIC operation. These bits select a transfer rate in master mode together with bits 2 CKS2 to CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, see table 17.3. The IICX0 bit controls IIC_0 and the IICX1 bit controls IIC_1. IIC Master Enable Enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), and SCI registers (SMR, BRR, SCMR). 0: SCI_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed in an area from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. SCI_0 registers are accessed in an area from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 1: IIC_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in an area from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in an area from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 4 IICE 0 R/W Rev. 3.00 Jan 25, 2006 page 59 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes Bit 3 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers of power-down states (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (BCR2, WSCR2, PCSR, SYSCR2). 0: Control registers of power-down states and onchip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 1: Control registers of flash memory are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 2 1 0 -- ICKS1 ICKS0 0 0 0 R/(W) R/W Reserved The initial value should not be changed. Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, see section 13.3.4, Timer Control Register (TCR). 3.3 3.3.1 Operating Mode Descriptions Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. However, because this LSI has a maximum of 18 address output pins, an external address space can be accessed only when the I/O strobe function of the AS/IOS pin, the CP/CF extension function, and the CS256 function are used. In extended mode, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port 6 functions as a data bus when the ABW bit in WSCR is cleared to 0. Rev. 3.00 Jan 25, 2006 page 60 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes 3.3.2 Mode 3 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. In extended mode, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port 6 functions as a data bus when the ABW bit in WSCR is cleared to 0. 3.3.3 Pin Functions Pin functions of ports 1 to 3, 6, 9, and A depend on the operating mode. Table 3.2 shows pin functions in each operating mode. Table 3.2 Port Port 1 Port 2 Port 3 Port 6 Port 9 P97 P96 P95 to P93 P90 Port A Legend: *: After reset Pin Functions in Each Operating Mode Mode 2 I/O port*/Address bus output I/O port*/Address bus output I/O port*/Data bus I/O I/O port*/Data bus I/O I/O port*/Control signal output Input port*/Clock I/O I/O port*/Control signal output I/O port*/Control signal output I/O port*/Address bus output Mode 3 I/O port*/Address bus output I/O port*/Address bus output I/O port*/Data bus output I/O port*/Data bus output I/O port*/Control signal output Input port*/Clock I/O I/O port*/Control signal output I/O port*/Control signal output I/O port* Rev. 3.00 Jan 25, 2006 page 61 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. ROM: 256 kbytes, RAM: 10 kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM H'000000 ROM: 256 kbytes, RAM: 10 kbytes Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000 On-chip ROM On-chip ROM H'03FFFF H'03FFFF Reserved area H'07FFFF H'080000 H'F7FFFF H'F80000 H'FBFFFF H'FC0000 H'FEFFFF H'FF0000 H'FF07FF H'FF0800 H'FF1FFF H'FF2000 Reserved area*1 *2 H'FF7FFF H'FF8000 H'FFBFFF H'FFC000 H'FFDFFF H'FFE000 H'FFE07F H'FFE080 H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE3F H'FFFE40 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Notes: H'FF7FFF External address*2 space CP/CF expansion area External address*2 space On-chip RAM*1 *2 (3,968 bytes) External address*2 space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM*1 *2 (128 bytes) Internal I/O registers 1 H'07FFFF External address*2 space 256-kbyte expansion area External address*2 space Reserved area On-chip RAM *1 *2 (6,144 bytes) H'FF0000 H'FF07FF H'FF0800 H'FF1FFF H'FF2000 Reserved area Reserved area On-chip RAM (6,144 bytes) Reserved area H'FFE080 H'FFEFFF On-chip RAM (3,968 bytes) H'FFF800 H'FFFE3F H'FFFE40 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 1. These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. 2. Since this LSI has 18 address output pins (max), the address space to be accessed is overlapped in the area from H'00000 to H'3FFFF. Figure 3.1 Address Map (Mode 2) Rev. 3.00 Jan 25, 2006 page 62 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes ROM: 56 kbytes, RAM: 4 kbytes Mode 3 (EXPE = 1) Normal mode Extended mode with on-chip ROM H'0000 H'0000 ROM: 56 kbytes, RAM: 4 kbytes Mode 3 (EXPE = 0) Normal mode Single-chip mode On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'EFFF H'F800 H'FE3F H'FE40 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'DFFF H'E080 On-chip RAM H'EFFF H'F800 H'FE3F H'FE40 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. Figure 3.2 Address Map (Mode 3) Rev. 3.00 Jan 25, 2006 page 63 of 872 REJ09B0286-0300 Section 3 MCU Operating Modes Rev. 3.00 Jan 25, 2006 page 64 of 872 REJ09B0286-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direction transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in program execution state. Direct transition Trap instruction Low Rev. 3.00 Jan 25, 2006 page 65 of 872 REJ09B0286-0300 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Vector Number 0 1 5 6 7 8 9 10 11 Direct transition (clock switchover) 12 Vector Address Normal Mode H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 Exception Source Reset Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) Reserved for system use 13 15 16 17 18 19 20 21 22 23 24 29 H'001A to H'001B | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'003A to H'003B H'000034 to H'000037 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'000074 to H'000077 External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt Internal interrupt* IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Rev. 3.00 Jan 25, 2006 page 66 of 872 REJ09B0286-0300 Section 4 Exception Handling Vector Number KIN7 to KIN0 KIN9, KIN8 WUE15 to WUE8 30 31 32 33 34 55 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 56 57 58 59 60 61 62 63 64 114 Vector Address Normal Mode H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 H'006E to H'006F H'0070 to H'0071 H'0072 to H'0073 H'0074 to H'0075 H'0076 to H'0077 H'0078 to H'0079 H'007A to H'007B H'007C to H'007D H'007E to H'007F H'0080 to H'0081 H'00E4 to H'00E5 Advanced Mode H'000078 to H'00007B H'00007C to H'00007F H'000080 to H'000083 H'000084 to H'000087 H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001C8 to H'0001CB Exception Source External interrupt External interrupt External interrupt Internal interrupt* Reserved for system use External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 15, Watchdog Timer (WDT). Rev. 3.00 Jan 25, 2006 page 67 of 872 REJ09B0286-0300 Section 4 Exception Handling 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit is set to 1 in CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. Vector fetch Internal Prefetch of first program processing instruction RES Internal address bus (1) (3) Internal read signal Internal write signal High Internal data bus (2) (4) (1) (2) (3) (4) Reset exception handling vector address ((1) = H'0000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First program instruction Figure 4.1 Reset Sequence (Mode 3) Rev. 3.00 Jan 25, 2006 page 68 of 872 REJ09B0286-0300 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled After a reset is cancelled, the module stop control registers (MSTPCR, SUBMSTPA, and SUBMSTPB) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN9 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. 4.5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. Rev. 3.00 Jan 25, 2006 page 69 of 872 REJ09B0286-0300 Section 4 Exception Handling The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains value prior to execution Set to 1 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 3.00 Jan 25, 2006 page 70 of 872 REJ09B0286-0300 Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd. Address CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 3.00 Jan 25, 2006 page 71 of 872 REJ09B0286-0300 Section 4 Exception Handling Rev. 3.00 Jan 25, 2006 page 72 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI, KIN, and WUE. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Thirty-five external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for IRQ15 to IRQ0. An interrupt is requested at the falling edge for KIN9 to KIN0 and WUE15 to WUE8. * DTC control The DTC can be activated by an interrupt request. Rev. 3.00 Jan 25, 2006 page 73 of 872 REJ09B0286-0300 Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR IER Priority level determination I, UI Interrupt request Vector number CPU KMIMR WUEMR KIN input WUE input Internal interrupt sources SWDTEND to MMCIC ICR Interrupt controller KIN, WUE input CCR Legend: ICR ISCR IER ISR KMIMR WUEMR SYSCR : Interrupt control register : IRQ sense control register : IRQ enable register : IRQ status register : Keyboard matrix interrupt mask register : Wake-up event interrupt mask register : System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 3.00 Jan 25, 2006 page 74 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Symbol NMI IRQ15 to IRQ0 ExIRQ15 to ExIRQ2 Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin. Pin of IRQn or ExIRQn to input IRQ15 to IRQ2 interrupts can be selected. Input Input Maskable external interrupts An interrupt is requested at falling edge. Maskable external interrupts An interrupt is requested at falling edge. KIN9 to KIN0 WUE15 to WUE8 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense port select registers (ISSR16, ISSR), see section 9.11.1, IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR). * Interrupt control registers A to D (ICRA to ICRD) * Address break control register (ABRKCR) * Break address registers A to C (BARA to BARC) * IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, ISCRL) * IRQ enable registers (IER16, IER) * IRQ status registers (ISR16, ISR) * Keyboard matrix interrupt mask registers (KMIMRA, KMIMR6) * Wake-up event interrupt mask registers (WUEMR3) Rev. 3.00 Jan 25, 2006 page 75 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2. Bit 7 to 0 Bit Name ICRn7 to IRCn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) Note: n: A to D Table 5.2 Correspondence between Interrupt Source and ICR Register Bit 7 6 5 4 3 2 1 0 Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1 ICRB A/D converter FRT -- TMR_X TMR_0 TMR_1 TMR_Y -- ICRC SCI_0 SCI_1 SCI_2 IIC_0 IIC_1 -- -- USB ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 -- -- -- -- -- MCIF Notes: n: A to D --: Reserved. The write value should always be 0. Rev. 3.00 Jan 25, 2006 page 76 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested. Bit 7 Bit Name CMIF Initial Value Undefined R/W R/W Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1. 6 to 1 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled Rev. 3.00 Jan 25, 2006 page 77 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. BARA Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus. BARB Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus. BARC Bit 7 to 1 0 Bit Name A7 to A1 -- Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. All 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 78 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Switching between pins IRQ15 to IRQ2 and pins ExIRQ15 to ExIRQ2 is performed by means of IRQ sense port select register 16 (ISSR16) and the IRQ sense port select register (ISSR). ISCR16H Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 15 to 12) ISCR16L Bit 7 6 5 4 3 2 1 0 Bit Name IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 11 to 8) Rev. 3.00 Jan 25, 2006 page 79 of 872 REJ09B0286-0300 Section 5 Interrupt Controller ISCRH Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 7 to 4) ISCRL Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn or ExIRQn* input 01: Interrupt request generated at falling edge of IRQn or ExIRQn* input 10: Interrupt request generated at rising edge of IRQn or ExIRQn* input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn* input (n = 3 to 0) Note: * ExIRQn stands for ExIRQ3 or ExIRQ2. Rev. 3.00 Jan 25, 2006 page 80 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) IERs control the enabling and disabling of interrupt requests IRQ15 to IRQ0. IER16 Bit 15 14 13 12 11 10 9 8 Bit Name IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable (n = 15 to 8) The IRQn interrupt request is enabled when this bit is 1. IER Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. Rev. 3.00 Jan 25, 2006 page 81 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. ISR16 Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * When reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn or ExIRQn input is high When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 15 to 8) * ISR Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * When reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn or ExIRQn* input is high (n = 7 to 0) * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 7 to 0) Note: * ExIRQn stands for ExIRQ7 to ExIRQ2. Rev. 3.00 Jan 25, 2006 page 82 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) The KMIMR and WUEMR registers enable or disable wake-up key-sensing interrupt inputs (KIN9 to KIN0), and wake-up event interrupt inputs (WUE15 to WUE8). KMIMRA Bit 7 to 2 1 0 Bit Name -- KMIM9 KMIM8 Initial Value All 1 1 1 R/W R/W R/W R/W Description Reserved These bits should not be cleared to 0. Keyboard Matrix Interrupt Mask These bits enable or disable a key-sensing input interrupt request (KIN9 and KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request KMIMR6 Bit 7 6 5 4 3 2 1 0 Bit Name KMIM7 KMIM6 KMIM5 KMIM4 KMIM3 KMIM2 KMIM1 KMIM0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask These bits enable or disable a wake-up key-in input interrupt request (KIN7 to KIN0). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request WUEMR3 Bit 7 6 5 4 3 2 1 0 Bit Name WUEM15 WUEM14 WUEM13 WUEM12 WUEM11 WUEM10 WUEM9 WUEM8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request Rev. 3.00 Jan 25, 2006 page 83 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are four external interrupts: NMI, IRQ15 to IRQ0, KIN9 to KIN0 and WUE15 to WUE8. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. Interrupts IRQ15 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2. * Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER. * The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding port DDR to 0 to use the pin as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2. Rev. 3.00 Jan 25, 2006 page 84 of 872 REJ09B0286-0300 Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input or ExIRQn* input Clear signal Notes: n = 15 to 0 * ExIRQn stands for ExIRQ15 to ExIRQ2. S R Q IRQn interrupt request Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 KIN9 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts KIN9 to KIN0 and WUE15 to WUE8 are requested by an input signal at pins KIN9 to KIN0 and WUE15 to WUE8. Interrupts KIN9 to KIN0 and WUE15 to WUE8 have the following features: * Interrupts KIN9 and KIN8, KIN7 to KIN0, and WUE15 to WUE8 each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address. * Enabling or disabling of interrupt requests can be selected with the I bit in CCR. * An interrupt is generated by a falling edge at pins KIN9 to KIN0 and WUE15 to WUE8. * Enabling or disabling of interrupt requests KIN9 to KIN0 and WUE15 to WUE8 can be selected using KMIMRA, KMIMR6, and WUEMR3. * The status of interrupt requests KIN9 to KIN0 and WUE15 to WUE8 are not indicated. The detection of KIN9 to KIN0 and WUE15 to WUE8 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding port DDR to 0 to use the pin as an I/O pin for another function. A block diagram of interrupts KIN9 to KIN0 and WUE15 to WUE8 is shown in figure 5.3. Rev. 3.00 Jan 25, 2006 page 85 of 872 REJ09B0286-0300 Section 5 Interrupt Controller KMIMn Falling-edge detection circuit KINn input Clear signal Note: n = 9 to 0 S R Q KINn interrupt request Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8 (Example of KIN9 to KIN0) 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. * The control level for each interrupt can be set by ICR. * The DTC can be activated by an interrupt request from an on-chip peripheral module. * An interrupt request that activates the DTC is not affected by the interrupt control mode or the status of the CPU interrupt mask bits. 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to interrupt control level 0 (no priority). Rev. 3.00 Jan 25, 2006 page 86 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Table 5.3 Origin of Interrupt Source Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Name Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Normal Mode H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'000078 H'00007C H'000080 H'000084 H'000088 H'00008C H'000090 H'000094 H'000098 H'00009C H'0000A0 H'0000A4 H'0000A8 H'0000AC H'0000B0 H'0000B4 H'0000B8 H'0000BC ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 -- ICRB7 -- -- Priority High External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTC WDT_0 WDT_1 -- A/D converter -- SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break ADI (A/D conversion end) Reserved for system use External pin KIN7 to KIN0 KIN9 and KIN8 Reserved for system use WUE15 to WUE8 RFU DTI0 DTI1 DTI2 DTI3 Reserved for system use Reserved for system use Reserved for system use Reserved for system use DTIE Reserved for system use CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) ICIX (Input capture) -- TMR_X ICRB4 Low Rev. 3.00 Jan 25, 2006 page 87 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Origin of Interrupt Source FRT Vector Address Name ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use Vector Number 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Normal Mode H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE Advanced Mode H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C ICR ICRB6 Priority High External pin IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) Reserved for system use Reserved for system use ICRD7 ICRD6 ICRB3 TMR_1 ICRB2 TMR_Y ICRB1 -- ICRC2 SCI_0 ERI0 (Reception error 0) RXI0 (Reception completion 0) TXI0 (Transmission data empty 0) TEI0 (Transmission end 0) ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) ICRC7 SCI_1 ICRC6 Low Rev. 3.00 Jan 25, 2006 page 88 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Origin of Interrupt Source SCI_2 Vector Address Name ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICC0 IICM0 IICR0 IICT0 IICC1 IICM1 IICR1 IICT1 Reserved for system use Vector Number 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Normal Mode H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00C2 H'00C4 H'00C6 H'00C8 H'00CA H'00CC H'00CE H'00D0 H'00D2 H'00D4 H'00D6 H'00D8 H'00DA H'00DC H'00DE H'00E0 H'00E2 H'00E4 Advanced Mode H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'000184 H'000188 H'00018C H'000190 H'000194 H'000198 H'00019C H'0001A0 H'0001A4 H'0001A8 H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC H'0001C0 H'0001C4 H'0001C8 ICR ICRC5 Priority High IIC_0 ICRC4 IIC_1 ICRC3 -- ICRB0 -- Reserved for system use ICRC1 USB USBI0 USBI1 USBI2 USBI3 MMCIA MMCIB MMCIC ICRC0 MCIF ICRD0 Low Rev. 3.00 Jan 25, 2006 page 89 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes Priority Setting Registers ICR Interrupt Mask Bits I Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0 Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 1 1 ICR I, UI Figure 5.4 shows a block diagram of the priority decision circuit. I ICR UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.4 Block Diagram of Interrupt Control Operation Rev. 3.00 Jan 25, 2006 page 90 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts that can be accepted in each interrupt control mode. Table 5.5 Interrupts Acceptable in Each Interrupt Control Mode I Bit 0 1 1 0 1 UI Bit 0 1 NMI, Address Break O O O O O KIN, WUE, DTI O X O X X Peripheral Module Interrupt O (All interrupts) X O (All interrupts) O (Interrupts with ICR = 1) X Interrupt Control Mode 0 Legend: : Don't care Note: * Interrupt control level 1 has priority. Default Priority Determination: The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.6 shows operations and control signal functions in each interrupt control mode. Rev. 3.00 Jan 25, 2006 page 91 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 INTM0 0 0 1 O O Interrupt Acceptance Control 3-Level Control I IM IM UI -- IM ICR PR PR Default Priority Determination O O T (Trace) -- -- Interrupt Control Mode 0 1 Legend: O: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets priority --: Not used 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI are masked by ICR and the I bit of the CCR in the CPU. Note however that the KIN, WUE, and DTI interrupt requests can be accepted when the I bit is cleared to 0 and are held pending when the I bit is set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. Rev. 3.00 Jan 25, 2006 page 92 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program excution state Interrupt generated? Yes Yes No NMI No An interrupt with interrupt control level 1? No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 MMCIC Yes Yes MMCIC Yes No No I=0 Yes No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00 Jan 25, 2006 page 93 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. Note however that the KIN, WUE, and DTI interrupt requests can be accepted when the I bit is cleared to 0 and are held pending when the I bit is set to 1. 1. An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. 2. An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRD are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown below. Figure 5.6 shows a state transition diagram. 1. All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > IRQ0 > IRQ1 > address break ...) 2. Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI = 0. 3. Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1. I All interrupt requests are accepted I 0 0 1, UI Only NMI, address break, and interrupt control level 1 interrupt requests are accepted I Exception handling execution or I 1, UI 1 0 UI 0 Exception handling execution or UI 1 Only NMI and address break interrupt requests are accepted Figure 5.6 State Transition in Interrupt Control Mode 1 Rev. 3.00 Jan 25, 2006 page 94 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Figure 5.7 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When both the I and UI bits are set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit is not affected. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address break interrupt. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00 Jan 25, 2006 page 95 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Program excution state No Interrupt generated? Yes Yes NMI No An interrupt with interrupt control level 1? No Hold pending Yes No No IRQ1 Yes MMCIC Yes No IRQ0 Yes IRQ1 Yes MMCIC Yes No IRQ0 Yes I=0 Yes No I=0 No Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 5.6.3 Interrupt Exception Handling Sequence Figure 5.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.00 Jan 25, 2006 page 96 of 872 REJ09B0286-0300 Interrupt is accepted Interrupt level decision and wait for end of instruction Instruction prefetch Stack access Vector fetch Internal processing Internal processing Prefetch of instruction in interrupt-handling routine Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) (13) Internal read signal Internal write signal Figure 5.8 Interrupt Exception Handling (2) (4) (6) (8) (10) (12) (6) (8) (9) (11) (10) (12) (13) (14) Internal data bus (14) (1) Rev. 3.00 Jan 25, 2006 page 97 of 872 REJ09B0286-0300 Section 5 Interrupt Controller (2) (4) (3) (5) (7) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.) SP - 2 SP - 4 Saved PC and CCR Vector address Starting address of interrupt-handling routine (contents of vector address) Starting address of interrupt-handling routine ((13) = (10) (12)) First instruction in interrupt-handling routine Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times--the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7 Interrupt Response Times Normal Mode *1 3 Advanced Mode 3 1 to (19 + 2*SI) 2*SK 2*SI 2*SI 2 12 to 32 No. Execution Status 1 2 3 4 5 6 Interrupt priority determination Number of wait states until executing instruction 1 to (19 + 2*SI) 2 ends* PC, CCR stack save Vector fetch 3 Instruction fetch* 2*SK SI 2*SI Internal processing* 4 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.8 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m Internal Memory SI SJ SK 1 2-State Access 4 3-State Access 6 + 2m Symbol Instruction fetch Branch address read Stack manipulation Legend: m: Number of wait states in external device access. Rev. 3.00 Jan 25, 2006 page 98 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.9 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip peripheral module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI Interrupt controller Figure 5.9 Interrupt Control for DTC The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.4, Location of Register Information and DTC Vector Table, for the respective priorities. Rev. 3.00 Jan 25, 2006 page 99 of 872 REJ09B0286-0300 Section 5 Interrupt Controller Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC. Table 5.9 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 x Interrupt Source Selection/Clearing Control DTC CPU x Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. x: The relevant bit cannot be used. *: Don't care Rev. 3.00 Jan 25, 2006 page 100 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.7 5.7.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10 shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.10 Conflict between Interrupt Generation and Disabling Rev. 3.00 Jan 25, 2006 page 101 of 872 REJ09B0286-0300 Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 Rev. 3.00 Jan 25, 2006 page 102 of 872 REJ09B0286-0300 Section 6 Bus Controller Section 6 Bus Controller This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters--CPU, data transfer controller (DTC), and RAM FIFO unit (RFU). 6.1 Features * Expansion area division The external address space can be accessed as basic expansion areas A 256-kbyte expansion area can be set and controlled independently of basic expansion areas in mode 2 (advanced mode) A CP expansion area can be set and controlled independently of basic expansion areas in mode 2 (advanced mode) * Address pin reduction A 256-kbyte expansion area from H'F80000 to H'FBFFFF can be selected using 18 address pins and the CS256 signal A CP expansion area (8 kbytes, basic mode) from H'FFC000 to H'FFDFFF can be selected using 13 address pins and the CPCS1 signal A 2-kbyte area from H'(FF)F000 to H'(FF)F7FF can be selected using six to eleven address pins and the IOS signal * Basic bus interface 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Memory card interface A CompactFlash* interface can be supported for the CF expansion area (4 kbytes, memory card mode) in the CP expansion area * Burst ROM interface A burst ROM interface can be set for basic expansion areas 1-state access or 2-state access can be selected for burst access * Idle cycle insertion An idle cycle can be inserted for external write cycles immediately after external read cycles * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and RFU BSCS200A_000020020300 Rev. 3.00 Jan 25, 2006 page 103 of 872 REJ09B0286-0300 Section 6 Bus Controller Note: * CompactFlash (CompactFlashTM) is a trademark of SanDisk Corporation in the United States, licensed through CFA (CompactFlashTM Association). External bus control signals Bus controller Internal control signals Bus mode signal BCR WSCR BCR2 WAIT/CPWAIT Wait controller CPU bus request signal DTC bus request signal RFU bus request signal CPU bus acknowledge signal DTC bus acknowledge signal RFU bus acknowledge signal Bus arbiter Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Jan 25, 2006 page 104 of 872 REJ09B0286-0300 Internal data bus WSCR2 Section 6 Bus Controller 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Symbol AS Pin Configuration I/O Output Function Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). Note that this signal is not output (the 256-kbyte expansion area is accessed while the CS256E bit in SYSCR is 1) or when the CP/CF expansion area is accessed (the CPCSE bit in BCR2 is 1). I/O select signal (when the IOSE bit in SYSCR is set to 1). Chip select signal indicating that the CP/CF expansion area is being accessed (in mode 2 or when the CPCSE bit in BCR2 is set to 1). Chip select signal indicating that the 256-kbyte expansion area is being accessed (in mode 2 or when the CS256E bit in SYSCR is set to 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written to, and the upper half (D15 to D8) of the data bus is enabled. (Note however that the effective data bus must be specified by the CPCS1 and CPCS2 signals when the CP/CF expansion area is being accessed.) IOS CPCS1, CPCS2 Output Output CS256 Output RD/CPOE HWR/CPWE Output Output LWR Output Strobe signal indicating that the external address space is being written to, and the lower half (D7 to D0) of the data bus is enabled. Wait request signal when accessing the external 3-state access space or CP/CF expansion area. WAIT/CPWAIT Input Rev. 3.00 Jan 25, 2006 page 105 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.3 Register Descriptions The bus controller has the following registers. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). * Bus control register (BCR) * Bus control register 2 (BCR2) * Wait state control register (WSCR) * Wait state control register 2 (WSCR2) 6.3.1 Bus Control Register (BCR) BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin. Bit 7 6 Bit Name ICIS Initial Value 1 1 R/W R/(W) R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between successive external read and external write cycles. 0: Idle cycle not inserted 1: 1-state idle cycle inserted 5 BRSTRM 0 R/W Burst ROM Enable Selects the bus interface for the external address space. 0: Basic bus interface 1: Burst ROM interface When the CS256E bit in SYSCR and the CPCSE bit in BCR2 are set to 1, burst ROM interface cannot be selected for the 256-kbyte expansion area and CP/CF expansion area. Rev. 3.00 Jan 25, 2006 page 106 of 872 REJ09B0286-0300 Section 6 Bus Controller Bit 4 Bit Name BRSTS1 Initial Value 1 R/W R/W Description Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM interface. 0: 1 state 1: 2 states 3 BRSTS0 0 R/W Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max. 4 words 1: Max. 8 words 2 CFE 0 R/W CF Expansion Area Enable Selects the CP/CF expansion area to be accessed when the CPCSE bit in BCR2 is set to 1. For details, see table 6.2. 0: CP expansion area (basic mode) 1: CF expansion area (memory card mode) 1 0 IOS1 IOS0 1 1 R/W R/W IOS Select 1, 0 Select the address range where the IOS signal is output. For details, refer to table 6.8. Rev. 3.00 Jan 25, 2006 page 107 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.3.2 Bus Control Register 2 (BCR2) BCR2 is used to specify the access mode for the CP expansion area (basic mode) and CF expansion area (memory card mode). Bit 7 Bit Name OWEAC Initial Value 0 R/W R/W Description OE/WE Assert Control Specifies the number of cycles from address output to the CPOE and CPWE signal assertion when the CF expansion area is specified as the CP expansion area. 0: 0.5 cycles 1: 1.5 cycles If the ASTCP bit is cleared to 0, this bit must not be set to 1. 6 OWENC 0 R/W OE/WE Negate Control Specifies the number of delay cycles from CPOE and CPWE signal negation to address hold when the CF expansion area is specified as the CP expansion area. 0: 0.5 cycles 1: 1.5 cycles If the ASTCP bit is cleared to 0, this bit must not be set to 1. 5 ABWCP 1 R/W CP Expansion Area Bus Width Control Selects the bus width for access to the CP expansion area when the CPCSE bit in BCR2 is set to 1 while the CFE bit in BCR is cleared to 0. When the CPCSE bit in BCR2 is set to 1 while the CFE bit in BCR is set to 1, the bus width for access to the CF expansion area is fixed at 16 bits. 0: 16-bit bus 1: 8-bit bus Rev. 3.00 Jan 25, 2006 page 108 of 872 REJ09B0286-0300 Section 6 Bus Controller Bit 4 Bit Name ASTCP Initial Value 1 R/W R/W Description CP/CF Expansion Area Access State Control Selects the number of states for access to the CP/CF expansion area when the CPCSE bit in BCR2 is set to 1. This bit also enables or disables wait-state insertion. 0: 2-state access space. Wait state insertion disabled in CP/CF expansion area access 1: 3-state access space. Wait state insertion enabled in CP/CF expansion area access 3 ADFULLE 0 R/W Address Output Full Enable Controls the IOS signal output and address output in access to the 256-kbyte expansion area and CP/CF expansion area. For details, refer to section 9, I/O Ports. 2 EXCKS 0 R/W External Expansion Clock Select Selects the operating clock used in external expansion area access. 0: Medium-speed clock is selected as the operating clock 1: System clock () is selected as the operating clock. The operating clock is switched in the bus cycle prior to external expansion area access. 1 BUSDIVE 1 R/W Bus Division Arbitration Enable Controls the bus arbitration timing for the divided bus cycles in the RFU operation. For details, refer to section 8, RAM FIFO Unit (RFU). 0 CPCSE 0 R/W CP/CF Expansion Area Enable Selects the expansion area to be accessed. 0: External address space (basic expansion area) 1: CP/CF expansion area (basic mode when CFE bit in BCR is 0, memory card mode when CFE bit in BCR is 1) Rev. 3.00 Jan 25, 2006 page 109 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.3.3 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces (basic expansion area and 256-kbyte expansion area). The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings. Bit 7 Bit Name ABW256 Initial Value 1 R/W R/W Description 256-kbyte Expansion Area Bus Width Control Selects the bus width for access to the 256-kbyte expansion area when the CS256E bit in SYSCR is set to 1. 0: 16-bit bus 1: 8-bit bus 6 AST256 1 R/W 256-kbyte Expansion Area Access State Control Selects the number of states for access to the 256kbyte expansion area when the CS256E bit in SYSCR is set to 1. This bit also enables or disables wait-state insertion. 0: 2-state access space. Wait state insertion disabled in 256-kbyte expansion area access 1: 3-state access space. Wait state insertion enabled in 256-kbyte expansion area access 5 ABW 1 R/W Bus Width Control Selects the bus width for access to the basic expansion area. 0: 16-bit bus 1: 8-bit bus When the CS256E bit in SYSCR and the CPCSE bit in BCR2 are set to 1, this bit setting is ignored in 256kbyte expansion area access and CP/CF expansion area access. Rev. 3.00 Jan 25, 2006 page 110 of 872 REJ09B0286-0300 Section 6 Bus Controller Bit 4 Bit Name AST Initial Value 1 R/W R/W Description Access State Control Selects the number of states for access to the basic expansion area. This bit also enables or disables waitstate insertion. 0: 2-state access space. Wait state insertion disabled in basic expansion area access 1: 3-state access space. Wait state insertion enabled in basic expansion area access When the CS256E bit in SYSCR and the CPCSE bit in BCR2 are set to 1, this bit setting is ignored in 256kbyte expansion area access and CP/CF expansion area access. 3 2 WMS21 WMS20 0 0 R/W R/W Wait Mode Select 1, 0 Select the wait mode for access to the basic expansion area when the AST bit is set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode When the CS256E bit in SYSCR and the CPCSE bit in BCR2 are set to 1, this bit setting is ignored in 256kbyte expansion area access and CP/CF expansion area access. 1 0 WC1 WC0 1 1 R/W R/W Wait Count 1, 0 Select the number of program wait states to be inserted when the basic expansion area is accessed while the AST bit is set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted When the CS256E bit in SYSCR and the CPCSE bit in BCR2 are set to 1, this bit setting is ignored in 256kbyte expansion area access and CP/CF expansion area access. Rev. 3.00 Jan 25, 2006 page 111 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.3.4 Wait State Control Register 2 (WSCR2) WSCR2 is used to specify the wait mode and number of wait states in access to the 256-kbyte expansion area and CP/CF expansion area. Bit 7 Bit Name WMS10 Initial Value 0 R/W R/W Description 256-kbyte Expansion Area Wait Mode Select 0 Selects the wait mode for access to the 256-kbyte expansion area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1. 0: Program wait mode 1: Wait disabled mode 6 5 WC11 WC10 1 1 R/W R/W 256-kbyte Expansion Area Wait Count 1, 0 Select the number of program wait states to be inserted for access to the 256-kbyte expansion area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted 4 3 WMS21 WMS20 0 0 R/W R/W CP/CF Expansion Area Wait Mode Select 1, 0 Select the wait mode for access to the CP/CF expansion area when the CPCSE and ASTCP bits in BCR2 are set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode (only in CP expansion area access) Rev. 3.00 Jan 25, 2006 page 112 of 872 REJ09B0286-0300 Section 6 Bus Controller Bit 2 1 0 Bit Name WC22 WC21 WC20 Initial Value 1 1 1 R/W R/W R/W R/W Description CP/CF Expansion Area Wait Count 2-0 Select the number of program wait states to be inserted for access to the CP/CF expansion area when the CPCSE and ASTCP bits in BCR2 are set to 1. If the CP expansion area is selected, the WC22 bit must be cleared to 0. 000: Program wait state is not inserted 001: 1 program wait state is inserted 010: 2 program wait states are inserted 011: 3 program wait states are inserted 100: 4 program wait states are inserted (only for CF expansion area) 101: 6 program wait states are inserted (only for CF expansion area) 110: 8 program wait states are inserted (only for CF expansion area) 111: 10 program wait states are inserted (only for CF expansion area) 6.4 6.4.1 Bus Control Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access states, and the wait mode and the number of program wait states. The bus width and the number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings. Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR, and the ABWCP bit in BCR2. If memory card mode is selected when the CFE bit in BCR is set to 1, a 16-bit bus is automatically selected for CP expansion area access. Number of Access States: Two or three access states can be selected via the AST and AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated, waitstate insertion is disabled. In the burst ROM interface, the number of access states for the basic expansion area is determined regardless of the AST bit setting. Rev. 3.00 Jan 25, 2006 page 113 of 872 REJ09B0286-0300 Section 6 Bus Controller Wait Mode and Number of Program Wait States: When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected. When the 256-kbyte expansion area is specified as a 3-state access space by the AST256 bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS10, WC11, and WC10 bits in WSCR2. From 0 to 3 program wait states can be selected. When the CP/CF expansion area is specified as a 3-state access space by the ASTCP bit in BCR2, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS21, WMS20, WC21, and WC20 bits in WSCR2. From 0 to 3 program wait states can be selected. When the CP expansion area is set to the CF expansion area (memory card mode) by the CFE bit in BCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS21, WMS20, WC22, WC21, and WC20 bits in WSCR2. From 0 to 4, 6, 8, or 10 program wait states can be selected. The wait function for external expansion is effective for connecting low-speed devices to the external address space. However, this wait function may cause some problems when bus masters other than the CPU, such as the DTC and RFU are to be delayed. The RFU is mostly used for data transmission and reception of interface peripheral modules. In this case, the wait function for external expansion may cause difficulty in making data transfer satisfy the communication rate of transmit/receive data of the interface peripheral modules. To prevent such a problem, it is recommended that when using the RFT, the external address space should be designated as a 2state or 3-state access space with no wait state. Tables 6.2 to 6.7 show each bit setting and external address space division in the address ranges of the external address space, and the bus specifications for the basic bus interface of each area. Rev. 3.00 Jan 25, 2006 page 114 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.2 Address Ranges and External Address Spaces Areas 256-kbyte Expansion Area, CP Expansion Area (Basic Mode), CF Expansion Area (Memory Card Mode) When WAIT/CPWAIT pin function is not selected while CS256E = 1, CS256 is output and address pins A17 to A0 are used. When CPCSE = 1 while CFE = 0, CPCS1 is output in the CP expansion area and address pins A12 to A0 are used. When CPCSE = 1 while CFE = 1, CPCS1 and CPCS2 are output in the CF expansion area and pins CPREG and CAP10 to CAP0 are used. Address Range H'080000-H'F7FFFF (15 Mbytes) H'F80000-H'FBFFFF (256 kbytes) 256-kbyte expansion area Basic Expansion Area No condition When CS256E = 0, used as basic expansion area. H'FC0000-H'FEFFFF (192 kbytes) H'FF0800-H'FF7FFF H'FF8000-H'FFBFFF (16 kbytes) H'FFC000-H'FFCFFF (4 kbytes) CP expansion area (1), CF expansion area No condition When RAME = 0, used as basic expansion area. No condition When CPCSE = 0, used as basic expansion area. H'FFD000-H'FFDFFF (4 kbytes) CP expansion area (2) When CPCSE = 0, used as basic expansion area. When CPCSE = 1 while CFE = 0, CPCS1 is output in the CP expansion area and address pins A12 to A0 are used. When CPCSE = 1 while CFE = 1, this address area cannot be used. H'(FF)E000-H'(FF)E07F (128 bytes) H'(FF)E080-H'(FF)EFFF (3968 bytes) No condition When RAME = 0, used as basic expansion area. Rev. 3.00 Jan 25, 2006 page 115 of 872 REJ09B0286-0300 Section 6 Bus Controller Areas 256-kbyte Expansion Area, CP Expansion Area (Basic Mode), CF Expansion Area (Memory Card Mode) Address Range H'(FF)F000-H'(FF)F7FF (2 kbytes) Basic Expansion Area No condition When IOSE = 1, IOS is output and address pins A10 to A0 are used. When RAME = 0, used as basic expansion area. H'(FF)FF00-H'(FF)FF7F (128 bytes) Legend: : This address range unconditionally becomes the basic expansion area when it is accessed. : Condition for making this address range included in the basic expansion area when it is accessed. : Irrelevant address range. Rev. 3.00 Jan 25, 2006 page 116 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface Areas CP Expansion Area (Basic Mode) and CF Expansion Area (Memory Card Mode) Used as basic expansion area ABWCP, ASTCP, WMS21, WMS20, WC21, WC20 Memory card mode WMS21, WMS20, WC22, WC21, WC20 ABW256, AST256, WMS10, WC11, WC10 Burst ROM interface* ABW, AST, WMS0, WC1, WC0, BRSTS1, BRSTS0 Used as burst ROM interface Same as when CS256E = 0 BRSTRM 0 CS256E 0 CPCSE 0 1 CFE -- 0 Basic Expansion Area Basic expansion area ABW, AST, WMS1, WMS0, WC1, WC0 256-kbyte Expansion Area Used as basic expansion area 1 1 0 1 -- 0 1 1 0 0 1 -- 0 Used as burst ROM interface ABWCP, ASTCP, WMS21, WMS20, WC21, WC20 Memory card mode WMS21, WMS20, WC22, WC21, WC20 1 1 0 1 -- 0 1 ABW256, AST256, WMS10, WC11, WC10 Same as when CS256E = 0 Legend: : Don't care Note: * In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the number of full access states (wait can be inserted) is specified by the AST bit in WSCR, and the number of access cycles in burst access is specified regardless of the AST bit setting. Rev. 3.00 Jan 25, 2006 page 117 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.4 Bus Specifications for Basic Expansion Area/Basic Bus Interface Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3 ABW 0 AST 0 1 WMS1 -- 0 WMS0 -- 1 WC1 -- -- 0 1 -- -- 0 1 WC0 -- -- 0 1 0 1 -- -- 0 1 0 1 Bus Width 16 16 Other than WMS1 = 0 and WMS0 = 1 1 0 1 -- 0 -- 1 Other than WMS1 = 0 and WMS0 = 1 Legend: : Don't care Rev. 3.00 Jan 25, 2006 page 118 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.5 Bus Specifications for 256-kbyte Expansion Area/Basic Bus Interface Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3 ABW256 AST256 WMS10 WC11 WC10 Bus Width 16 16 0 0 1 -- 1 0 -- -- 0 1 -- -- 0 1 0 1 -- -- 0 1 0 1 1 0 1 -- 1 0 -- -- 0 1 Legend: : Don't care Rev. 3.00 Jan 25, 2006 page 119 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.6 Bus Specifications for CP Expansion Area (Basic Mode)/Basic Bus Interface Bus Specifications Bus Width Number of Number of Access Program States Wait States 2 3 3 0 0 0 1 2 3 8 8 2 3 3 0 0 0 1 2 3 ABWCP ASTCP 0 0 1 WMS21 -- 0 WMS20 WC21 -- 1 -- -- 0 1 -- -- 0 1 WC20 -- -- 0 1 0 1 -- -- 0 1 0 1 16 16 Other than WMS21 = 0 and WMS20 = 1 1 0 1 -- 0 -- 1 Other than WMS21 = 0 and WMS20 = 1 Legend: : Don't care Rev. 3.00 Jan 25, 2006 page 120 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.7 Bus Specifications for CF Expansion Area (Memory Card Mode)/Basic Bus Interface Bus Specifications Number of Access States 2 3 3 Number of Program Wait States 0 0 0 1 2 3 4 6 8 10 ASTCP 0 1 WMS21 -- 0 WMS20 -- 1 WC22 -- -- 0 WC21 -- -- 0 1 WC20 -- -- 0 1 0 1 0 1 0 1 Bus Width 16 16 Other than WMS21 = 0 and WMS20 = 1 or WMS21 = 1 and WMS20 = 1 1 0 1 Legend: : Don't care 6.4.2 Advanced Mode This LSI cannot output upper addresses (A23 to A18) in mode 2 (advanced mode) because this LSI has 18 address output pins (A17 to A0). Therefore, the external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS pin as an I/O strobe pin. The 256-kbyte expansion area (H'F80000 to H'FBFFFF) and CP expansion area (H'FFC000 to H'FFDFFF) can be accessed by the CS256 pin and CPCS1 pin functions, respectively. The external address space is initialized as the basic bus interface and a 3-state access space. In mode 2, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1, and disabled when the RAME bit is cleared to 0. Addresses H'FF0800 to H'FF7FFF, H'FFE080 to H'FFEFFF, and H'FFFF00 to H'FFFF7F in the on-chip RAM area and its reserved area are always specified as the external address space. Rev. 3.00 Jan 25, 2006 page 121 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In mode 3 (normal mode), the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM area is enabled when the RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. 6.4.4 I/O Select Signals The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 Address bus External addresses selected by IOS IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE bit to 1. For details, refer to section 9, I/O Ports. The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR, as shown in table 6.8. Table 6.8 IOS1 0 1 Address Range for IOS Signal Output IOS0 0 1 0 1 IOS Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)F7FF (Initial value) Rev. 3.00 Jan 25, 2006 page 122 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.5 Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications for the basic expansion area, 256-kbyte expansion area, and CP/CF expansion area when using the basic bus interface, see tables 6.4 to 6.6. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Rev. 3.00 Jan 25, 2006 page 123 of 872 REJ09B0286-0300 Section 6 Bus Controller Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.9 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.9 Area 8-bit access space 16-bit access space Data Buses Used and Valid Strobes Access Size Byte Byte Read/ Write Read Write Read Write Word Read Write Address -- -- Even Odd Even Odd -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Undefined Valid Valid Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) Valid Ports or others Ports or others Invalid Valid Undefined Valid Valid Valid Notes: Undefined Invalid Ports or others : Undefined data is output. : Input state with the input value ignored. : Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus. Rev. 3.00 Jan 25, 2006 page 124 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.5.3 Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space Rev. 3.00 Jan 25, 2006 page 125 of 872 REJ09B0286-0300 Section 6 Bus Controller 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space Rev. 3.00 Jan 25, 2006 page 126 of 872 REJ09B0286-0300 Section 6 Bus Controller 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High level Valid D7 to D0 Undefined Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) Rev. 3.00 Jan 25, 2006 page 127 of 872 REJ09B0286-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS * (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev. 3.00 Jan 25, 2006 page 128 of 872 REJ09B0286-0300 Section 6 Bus Controller Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.00 Jan 25, 2006 page 129 of 872 REJ09B0286-0300 Section 6 Bus Controller 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR High level LWR Write D15 to D8 Valid D7 to D0 Undefined Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) Rev. 3.00 Jan 25, 2006 page 130 of 872 REJ09B0286-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Rev. 3.00 Jan 25, 2006 page 131 of 872 REJ09B0286-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.00 Jan 25, 2006 page 132 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.5.4 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT/CPWAIT pin, and the combination of program wait and the WAIT/CPWAIT pin. Program Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in WSCR2 for the 256-kbyte expansion area, and the WC21 and WC20 bits in WSCR2 for the CP expansion area). Pin Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP expansion area). If the WAIT/CPWAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT/CPWAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states to be inserted for each external device. Pin Auto-Wait Mode: A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space according to the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP expansion area) if the WAIT/CPWAIT pin is low at the falling edge of in the last T2 state. Even if the WAIT/CPWAIT pin is held low, TW states can be inserted only up to the specified number of states. This function enables the low-speed memory interface only by inputting the chip select signal to the WAIT/CPWAIT pin. Figure 6.13 shows an example of wait state insertion timing in pin wait mode. The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT/CPWAIT pin input disabled. Rev. 3.00 Jan 25, 2006 page 133 of 872 REJ09B0286-0300 Section 6 Bus Controller By program wait T1 T2 TW By WAIT/CPWAIT pin TW TW T3 WAIT/CPWAIT Address bus AS/IOS (IOSE = 0) CPCS1 (CPCSE = 1 and CFE = 0) AS/IOS* (IOSE = 0) RD Read Data bus Read data WR Write Data bus Write data Notes: shown in clock indicates the WAIT/CPWAIT pin sampling timing. * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1. Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) 6.6 Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. Rev. 3.00 Jan 25, 2006 page 134 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.6.1 Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight words is performed when the BRSTS0 bit in BCR is set to 1. The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15. Full access T1 T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) Rev. 3.00 Jan 25, 2006 page 135 of 872 REJ09B0286-0300 Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. Rev. 3.00 Jan 25, 2006 page 136 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.7 Memory Card Interface A CP expansion area can be set to the CF expansion area (memory card mode) by setting both the CPCSE bit in BCR2 to 1 and the CFE bit in BCR to 1. In memory card mode, the bus width is fixed to 16 bits. In this mode, signal pins other than CPCS1 and CPCS2 are common to the basic bus interface, but their signal waveforms differ. The number of access states and waveforms of the strobe signals (CPOE and CPWE) can be controlled by the WMS21, WMS20, WC22, WC21, and WC20 bits in WSCR2 and the OWEAC and OWENC bits in BCR2. 6.7.1 Data Size and Data Alignment The data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used when the CF expansion area is accessed in memory card mode according to the accessed data size. Figure 6.16 illustrates the data alignment control. In CF expansion area access, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used. The amount of data that can be accessed at one time is one byte or one word: a longword access is performed as two word accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle : Even data : Odd data * Even address * Odd address Figure 6.16 Access Sizes and Data Alignment Control Rev. 3.00 Jan 25, 2006 page 137 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.7.2 Valid Strobes Table 6.10 shows the data buses used and valid strobes. Table 6.10 Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Address Even Odd Write Even Odd Word Read Write -- -- CPCS1 Pin L L L L L L CPCS2 Pin H H H H L L CPOE CPWE CPWE Valid Strobe CPOE Upper Data Bus (D15 to D8) Invalid Invalid Undefined Undefined Valid (odd data) Valid (odd data) Lower Data Bus (D7 to D0) Valid (even data) Valid (odd data) Valid (even data) Valid (even data) Valid (even data) Valid (even data) Notes: Undefined: Undefined data is output. Invalid: Input state with the input value ignored. 6.7.3 Basic Operation Timing The memory card interface is basically specified as having 3 access states. Figure 6.17 shows the access timing in memory card mode. The strobe signal waveform for the rising edge and falling edge at address output can be moved one state by setting the OWEAC and OWENC bits in BCR, respectively. In this case, wait states must be inserted. For 2-state access, clear both the OWEAC and OWENC bits to 0. In addition, note that in 3-state access, set the OWEAC and OWENC bits to B'01 or B'10. Figure 6.18 shows the access timing in memory card mode when the OWEAC and OWENC bits are set to 1 simultaneously. Rev. 3.00 Jan 25, 2006 page 138 of 872 REJ09B0286-0300 Section 6 Bus Controller Bus cycle T1 T2 T3 Address bus CPCS1, CPCS2 CPOE Read D15 to D0 CPWE Write D15 to D0 Valid Valid Figure 6.17 Access Timing in Memory Card Mode (Basic Cycle) By program wait T1 TW TW T2 T3 Address bus CPCS1, CPCS2 CPOE Read D15 to D0 CPWE Write D15 to D0 Valid Valid Figure 6.18 Access Timing in Memory Card Mode (OWEAC = OWENC = 1 with Wait State Insertion) Rev. 3.00 Jan 25, 2006 page 139 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.7.4 Wait Control With memory card interface, there are two ways of inserting wait states: Program wait insertion and pin wait insertion using the CPWAIT pin. Program Wait Mode: A specified number of wait states TW can be inserted between the T2 state and T3 state when accessing the CF expansion area according to the settings in the WC22, WC21, and WC20 bits in WSCR2. Pin Wait Mode: A specified number of wait states TW can be inserted between the T2 state and T3 state when accessing the CF expansion area according to the settings in the WC22, WC21, and WC20 bits. If the CPWAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the CPWAIT pin is held low, TW states are inserted until it goes high. Note, however, that TW state insertion by the CPWAIT pin is not performed unless program wait mode is specified. Figure 6.19 shows an example of wait state insertion timing. By program wait T1 TW TW By CPWAIT pin TW T2 T3 CPWAIT Address bus CPCS1, CPCS2 CPOE Read D15 to D0 CPWE Write D15 to D0 Valid Valid Figure 6.19 Access Timing Example in Memory Card Mode (Wait State Insertion by Program Wait and CPWAIT Pin) Rev. 3.00 Jan 25, 2006 page 140 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.8 Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.20 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.20 (a), with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In figure 6.20 (b), an idle cycle is inserted, thus preventing data collision. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Address bus RD WR Data bus Address bus RD WR Data bus Data collision Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion Figure 6.20 Examples of Idle Cycle Operation Rev. 3.00 Jan 25, 2006 page 141 of 872 REJ09B0286-0300 Section 6 Bus Controller Table 6.11 shows the pin states in an idle cycle. Table 6.11 Pin States in Idle Cycle Pins A17 to A0 D15 to D0 AS, IOS, CS256, CPCS1, CPCS2 RD, CPOE HWR, LWR, CPWE Pin State Contents of immediately following bus cycle High impedance High High High 6.9 Bus Arbitration The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters--the CPU, DTC, and RFU--that perform read/write operations when they have possession of the bus. 6.9.1 Bus Master Priority Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal to the bus master making the request at the designated timing. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) RFU > DTC > CPU (Low) Rev. 3.00 Jan 25, 2006 page 142 of 872 REJ09B0286-0300 Section 6 Bus Controller 6.9.2 Bus Transfer Timing When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. Each bus master can relinquish the bus at the timings given below. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or RFU, the bus arbiter transfers the bus to the DTC. * DTC bus transfer timing The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. For details, refer to section 2.7, Bus States During Instruction Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual. If the CPU is in sleep mode, the bus is transferred immediately. * RFU bus transfer timing The bus is transferred at a break between bus cycles. Even in discrete operations, as in the case of a longword-size access, the bus can be transferred between the component operations. For details, refer to section 8, RAM-FIFO Unit (RFU). If the CPU is in sleep mode, the bus is transferred immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. Since the bus master priority of the DTC is lower than the RFU, the bus arbiter transfers the bus mastership from the DTC to the RFU if the RFU requests the bus. * RFU bus transfer timing The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. In addition, in 32-bit access by the DTC, the bus is not transferred at a break between longword access cycles. For details, refer to section 8, RAM-FIFO Unit (RFU). RFU: The RFU has the highest bus master priority. The RFU sends the bus arbiter a request for the bus when an activation request is generated. The RFU does not release the bus until it completes its operation. For details, refer to section 8, RAM-FIFO Unit (RFU). Rev. 3.00 Jan 25, 2006 page 143 of 872 REJ09B0286-0300 Section 6 Bus Controller Rev. 3.00 Jan 25, 2006 page 144 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 7.1 Features * Transfer is possible over any number of channels * Three transfer modes: Normal, repeat, and block transfer modes are available * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16-Mbyte address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set * Usable for scan operations of CIN7 to CIN0 * DTC operates in high-speed mode even when the LSI is in medium-speed mode DTCH801A_000020020300 Rev. 3.00 Jan 25, 2006 page 145 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request DTC activation request Legend: MRA, MRB : DTC mode register A, B : DTC transfer count register A, B CRA, CRB : DTC source address register SAR : DTC destination register DAR DTCERA to DTCERE : DTC enable registers A to E : DTC vector register DTVECR Figure 7.1 Block Diagram of DTC 7.2 Register Descriptions The DTC has the following registers. * DTC mode register A (MRA) * DTC mode register B (MRB) * DTC source address register (SAR) * DTC destination address register (DAR) * DTC transfer count register A (CRA) * DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. Rev. 3.00 Jan 25, 2006 page 146 of 872 REJ09B0286-0300 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERE DTVECR Section 7 Data Transfer Controller (DTC) * DTC enable registers (DTCER) * DTC vector register (DTVECR) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1, 0 These bits specify an SAR operation after a data transfer. 0X: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined -- -- Destination Address Mode 1, 0 These bits specify a DAR operation after a data transfer. 0X: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area Rev. 3.00 Jan 25, 2006 page 147 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) Bit 0 Bit Name Sz Initial Value Undefined R/W -- Description DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: X: Don't care 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit 7 Bit Name CHNE Initial Value Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time data transfer ends. When this bit is cleared to 0, a CPU interrupt request is generated only when the specified number of data transfer ends. Note however that when the DTC is activated by a USB or MCIF interrupt source and this bit is cleared to 0, this LSI does not operate correctly. In such a case, be sure to set this bit to 1. 5 to -- 0 Undefined -- Reserved These bits have no effect on DTC operation. The write value should always be 0. Rev. 3.00 Jan 25, 2006 page 148 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 7.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev. 3.00 Jan 25, 2006 page 149 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 to 7.3. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When data transfer has ended with the DISEL bit in MRB set to 1 When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed Table 7.1 Correspondence between Interrupt Sources and DTCER Register Bit 7 6 5 4 3 2 1 0 Bit Name DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 DTCERA (16)IRQ0 (17)IRQ1 (18)IRQ2 (19)IRQ3 (28)ADI (48)ICIA (49)ICIB (52)OCIA DTCERB (53)OCIB (93)IICM0 (94)IICR0 (95)IICT0 -- (64)CMIA0 (65)CMIB0 (68)CMIA1 DTCERC (69)CMIB1 (72)CMIAY (73)CMIBY -- (44)CMIAX (81)RXI0 (82)TXI0 (85)RXI1 DTCERD (86)TXI1 (89)RXI2 (90)TXI2 (97)IICM1 (98)IICR1 (99)IICT1 (112)MMCIA (45)CMIBX DTCERE (108)USBI0 (109)USBI1 (110)USBI2 (111)USBI3 -- -- -- -- Notes: n: A to E ( ): Vector number --: Reserved. The write value should always be 0. Rev. 3.00 Jan 25, 2006 page 150 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] 1. When the DISEL bit is 0 and the specified number of transfers have not ended 2. When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. This bit will not be cleared when the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended. 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to. Rev. 3.00 Jan 25, 2006 page 151 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.3 Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag in SCI_0. When an interrupt has been designated as a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block diagram of DTC activation source control. For details on the interrupt controller, see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip peripheral module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 7.2 Block Diagram of DTC Activation Source Control Rev. 3.00 Jan 25, 2006 page 152 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal and advanced modes; a 2-byte unit is used in both cases. Specify the lower two bits of the register information start address. Lower address 0 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 4 bytes Figure 7.3 DTC Register Information Location in Address Space Rev. 3.00 Jan 25, 2006 page 153 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 Vector Number DTVECR 16 17 18 19 28 44 45 48 49 52 53 64 65 68 69 72 73 76 78 79 81 82 85 86 89 90 93 94 95 DTC Vector Address DTCE* Priority High Activation Source Origin Software External pins H'0400 + (vector -- number x 2) H'0420 DTCEA7 H'0422 H'0424 H'0426 H'0438 H'0458 H'045A H'0460 H'0462 H'0468 H'046A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049C H'049E H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04BA H'04BC H'04BE DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEC3 DTCED0 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCED2 DTCED2 DTCEB4 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCEB6 DTCEB5 DTCEB4 A/D converter TMR_X FRT IRQ3 ADI CMIAX CMIBX ICIA ICIB OCIA OCIB TMR_0 TMR_1 TMR_Y CMIA0 CMIB0 CMIA1 CMIB1 CMIAY CMIBY Reserved for system use Reserved for system use Reserved for system use RXI0 TXI0 RXI1 TXI1 RXI2 TXI2 IICM0 IICR0 IICT0 SCI_0 SCI_1 SCI_2 IIC_0 Low Rev. 3.00 Jan 25, 2006 page 154 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) Activation Source Origin IIC_1 Vector Number 97 98 99 104 105 106 107 108 109 110 DTC Vector Address H'04C2 H'04C4 H'04C6 H'04D0 H'04D2 H'04D4 H'04D6 H'04D8 H'04DA H'04DC Activation Source IICM1 IICR1 IICT1 Reserved for system use Reserved for system use Reserved for system use DTCE* DTCED4 DTCED3 DTCED2 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEE7 DTCEE6 DTCEE5 Priority High USB Reserved for system use USBI0 USBI1 USBI2 MCIF Note: * USBI3 111 H'04DE DTCEE4 MMCIA 112 H'04E0 DTCED1 Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. Rev. 3.00 Jan 25, 2006 page 155 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1 No Yes Transfer counter = 0 or DISEL = 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 7.4 DTC Operation Flowchart Rev. 3.00 Jan 25, 2006 page 156 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 7.3 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Functions in Normal Mode Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer counter Not used SAR Transfer DAR Figure 7.5 Memory Mapping in Normal Mode Rev. 3.00 Jan 25, 2006 page 157 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.4 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0. Table 7.4 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer counter Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 7.6 Memory Mapping in Repeat Mode Rev. 3.00 Jan 25, 2006 page 158 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.5 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. Table 7.5 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size counter Transfer counter 1st block SAR or DAR * * * Block area Transfer DAR or SAR N th block Figure 7.7 Memory Mapping in Block Transfer Mode Rev. 3.00 Jan 25, 2006 page 159 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Destination Source Destination Figure 7.8 Chain Transfer Operation Rev. 3.00 Jan 25, 2006 page 160 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5.6 Operation Timing DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 3.00 Jan 25, 2006 page 161 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) DTC activation request DTC request Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 7.11 DTC Operation Timing (Example of Chain Transfer) Rev. 3.00 Jan 25, 2006 page 162 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.5.7 Number of DTC Execution States Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number of states required for each execution status. Table 7.6 DTC Execution Status Register Information Vector Read Read/Write Data Read I J K 1 1 1 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) Table 7.7 Number of States Required for Each Execution Status On-Chip RAM On-Chip RAM (On-Chip RAM other than left) (H'(FF)EC00 to H'(FF)EFFF) Object to be Accessed Bus width Access states Execution Vector read SI status Register information read/write SJ Byte data read Word data read Byte data write Word data write SK SK SL SL OnChip ROM 16 1 1 -- 1 1 1 1 1 On-Chip I/O Registers External Devices 8 2 -- -- 2 4 2 4 1 16 2 -- -- 2 2 2 2 1 8 2 4 -- 2 4 2 4 1 8 3 6 + 2m -- 3+m 6 + 2m 3+m 6 + 2m 1 16 2 2 -- 2 2 2 2 1 16 3 3+m -- 3+m 3+m 3+m 3+m 1 32 1 -- 1 1 1 1 1 1 16 1 -- -- 1 1 1 1 1 Internal operation SM The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states. Rev. 3.00 Jan 25, 2006 page 163 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.6 7.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 7.6.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to the SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested. 7.7 7.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the Rev. 3.00 Jan 25, 2006 page 164 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) SCI's RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing. 7.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform wrap-up processing. Rev. 3.00 Jan 25, 2006 page 165 of 872 REJ09B0286-0300 Section 7 Data Transfer Controller (DTC) 7.8 7.8.1 Usage Notes Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode can be specified. For details, refer to section 27, Power-Down Modes. 7.8.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR should not be cleared to 0. 7.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm that is set to 1 before making a transition to subactive mode or watch mode. 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter Interrupt sources of the SCI, IIC, or A/D converter which activate the DTC are cleared when DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit in MRB. 7.8.6 DTC Activation by Interrupt Sources of USB or MCIF When activating the DTC by a USB or MCIF interrupt source, correct operation is not guaranteed if the DISEL bit in MRB is cleared to 0. Be sure to set the DISEL bit to 1 before DTC activation. Rev. 3.00 Jan 25, 2006 page 166 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Section 8 RAM-FIFO Unit (RFU) This LSI incorporates a RAM-FIFO unit (RFU). The RFU is activated by a request from the peripheral modules and can transfer data between the peripheral modules and on-chip RAM. As the RFU can specify the RAM address to be transferred by using a pointer that is updated for every data transfer execution, the RAM specified area can be regarded as an FIFO. If an FIFO full/empty or overrun error occurs according to pointer update, the RFU can acknowledge this error to the peripheral modules. The peripheral modules request pointer reset and manipulation of the temporary pointer in addition to data transfer. A block diagram of the RFU is shown in figure 8.1. 8.1 Features * Bus master with priority higher than that of the CPU and DTC * Provides the RFU-ID to specific peripheral modules (SCI, USB, and MCIF) to specify the peripheral modules to be manipulated by the RFU with ID numbers * RFU bus cycle accesses the peripheral modules and on-chip RAM simultaneously * During an RFU bus cycle, the address bus outputs a RAM address for data transfer * RAM address for data transfer is specified by the on-chip pointer set of the RFU * Four pointer sets * The contents of the pointer set are updated for every data transfer, and a specific RAM area can be manipulated as the FIFO (RAM-FIFO) * RAM-FIFO size: 32/64/128/256/512/1024/2048 bytes selectable * An interrupt can be generated by a RAM-FIFO full/empty or overrun error * RFU operates in high-speed mode even when the LSI is in medium-speed mode RAMFU00A_000020020300 Rev. 3.00 Jan 25, 2006 page 167 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Internal address bus Internal data bus RFU activation request Internal data bus interface Pointer set 0 BAR_0 RAR_0 TMP_0 Internal address bus interface/address control circuit WAR_0 DTCRA_0 Internal module data bus DTCRB_0 DTSTRC_0 DTIDR_0 Pointer set 1* Pointer set 2* Pointer set 3* DATAN/FREEN NRA/NWA DTCRC DTCRD DTSTRA DTSTRB DTIER DTRSR DTIDSRA DTIDSRB RFU control circuit Legend: BAR RAR TMP WAR DATAN FREEN NRA NWA DTCRA DTCRB : Base address register : Read address pointer : Temporary pointer : Write address pointer : Valid data byte number : Free area byte number : Read start address : Write start address : Data transfer control register A : Data transfer control register B DTSTRC : Data transfer status register C DTIDR : Data transfer ID register DTIDSRA : Data transfer ID read/write select register A DTIDSRB : Data transfer ID read/write select register B DTSTRA : Data transfer status register A DTSTRB : Data transfer status register B DTCRC : Data transfer control register C DTCRD : Data transfer control register D DTIER : Data transfer interrupt enable register DTRSR : Data transfer register select register DTI0 to DTI3 DTIE Interrupt signal Notes: * Pointer sets 1 to 3 have a function similar to pointer set 0. Figure 8.1 Block Diagram of RFU Rev. 3.00 Jan 25, 2006 page 168 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2 Register Descriptions The RFU has the following registers. * FIFO status/register/pointer (FSTR) Base address register (BAR) Read address pointer (RAR) Write address pointer (WAR) Temporary pointer (TMP) Valid data byte number (DATAN) Free area byte number (FREEN) Read start address (NRA) Write start address (NWA) * Data transfer control register A (DTCRA) * Data transfer control register B (DTCRB) * Data transfer status register C (DTSTRC) * Data transfer ID register (DTIDR) * Data transfer ID read/write select register A (DTIDSRA) * Data transfer ID read/write select register B (DTIDSRB) * Data transfer status register A (DTSTRA) * Data transfer status register B (DTSTRB) * Data transfer control register C (DTCRC) * Data transfer control register D (DTCRD) * Data transfer interrupt enable register (DTIER) * Data transfer select register (DTRSR) 8.2.1 FIFO Status/Register/Pointer (FSTR) FSTR is a 32-bit readable/writable register used to access the FIFO status/register/pointer of the pointer sets (0 to 3). Any one of four registers/pointers (BAR, RAR, WAR, and TMP) and four states (DATAN, FREEN, NRA, and NWA) can be accessed using FSTR. The status is updated by writing (selecting pointer or status) to DTRSR. The new status should be referenced after writing to DTRSR, even when referencing the same pointer or same status. BAR in pointer set 0 is selected via the initial value of DTRSR, however, an undefined value is read from FSTR until data is written to DTRSR. Rev. 3.00 Jan 25, 2006 page 169 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.2 Base Address Register (BAR) BAR is a 16-bit register provided in each pointer set, and allocated to bits 19 to 4 in FSTR. The base address should be set at the boundary specified by the BUD2 to BUD0 bits in DTCRA. Otherwise, address specification by the pointer and status display by calculation inter-pointers may not be performed correctly. Bit 31 to 20 19 to 4 3 to 0 Bit Name -- Initial Value All 1 R/W R Description Base Addresses 31 to 20 These bits are always read as 1 and cannot be modified. BA19 to BA4 -- Undefined R/W Base Addresses 19 to 4 These bits specify a RAM base address that can be used as the FIFO. All 0 R Base Addresses 3 to 0 These bits are always read as 0 and cannot be modified. 8.2.3 Read Address Pointer (RAR) RAR is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR. Bit 31 to 11 10 to 0 Bit Name -- Initial Value All 0 R/W R Description Read Addresses 31 to 11 These bits are always read as 0 and cannot be modified. RA10 to RA0 All 0 R/W Read Addresses 10 to 0 These bits are pointers to specify the RAM address to be read from in a RAM read cycle of the RFU. The RAM address is calculated by BAR + RAR. These can be read as NRA. These bits are incremented for the number of bytes to be read for each RAM read cycle. However, these bits are not incremented and cleared to 0 when exceeding the selected FIFO size. Rev. 3.00 Jan 25, 2006 page 170 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.4 Write Address Pointer (WAR) WAR is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR. Bit 31 to 11 10 to 0 Bit Name -- Initial Value All 0 R/W R Description Write Addresses 31 to 11 These bits are always read as 0 and cannot be modified. WA10 to WA0 All 0 R/W Write Addresses 10 to 0 These bits are pointers to specify the RAM address to be written to in a RAM write cycle of the RFU. The RAM address is calculated by BAR + WAR. These can be read as NWA. These bits are incremented for the number of bytes to be written for each RAM write cycle. However, these bits are not incremented and cleared to 0 when exceeding the selected FIFO size. 8.2.5 Temporary Pointer (TMP) TMP is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR. TMP can select the pointer set operation by setting the PMD1 and PMD0 bits in DTCRA. Bit 31 to 11 10 to 0 Bit Name -- Initial Value All 0 R/W R Description Temporary Addresses 31 to 11 These bits are always read as 0 and cannot be modified. TMP10 to TMP0 All 0 R/W Temporary Addresses 10 to 0 [When TMP is used as a read temporary pointer] These bits can copy the contents of RAR to TMP or copy the contents of TMP to RAR by pointer update manipulation. [When TMP is used as a write temporary pointer] These bits can copy the contents of WAR to TMP or copy the contents of TMP to WAR by pointer update manipulation. Rev. 3.00 Jan 25, 2006 page 171 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.6 Valid Data Byte Number (DATAN) DATAN is 11-bit status data allocated to bits 10 to 0 in FSTR. Bit 31 to 11 10 to 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. -- All 0 R Valid Data Byte Number These bits indicate the number of bytes of valid data that can be read by FIFO in each pointer set. 8.2.7 Free Area Byte Number (FREEN) FREEN is 11-bit status data allocated to bits 10 to 0 in FSTR. Bit 31 to 11 10 to 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. -- All 0 R Free Area Byte Number These bits indicate the number of bytes of the free area that can be written to FIFO in each pointer set. 8.2.8 Read Start Address (NRA) NRA is 32-bit status data allocated to bits 31 to 0 in FSTR. Bit 31 to 0 Bit Name -- Initial Value Undefined R/W R Description Read Start Addresses 31 to 0 The RAM address is calculated by BAR + RAR Rev. 3.00 Jan 25, 2006 page 172 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.9 Write Start Address (NWA) NWA is 32-bit status data allocated to bits 31 to 0 in FSTR. Bit 31 to 0 Bit Name -- Initial Value Undefined R/W R Description Write Start Addresses 31 to 0 The RAM address is calculated by BAR + WAR 8.2.10 Data Transfer Control Register A (DTCRA) DTCRA is a register provided in each pointer set that controls the operation of each pointer set. Bit 7 Bit Name IDE-A Initial Value 0 R/W R/W Description ID-A Enable Enables/disables ID-A selected by DTIDR. 0: Disables ID-A 1: Enables ID-A 6 IDE-B 0 R/W ID-B Enable Enables/disables ID-B selected by DTIDR. 0: Disables ID-B 1: Enables ID-B 5 4 PMD1 PMD0 0 0 R/W R/W Pointer mode 1, 0 These bits select operation mode of the TMP. 0X: TMP is not used 10: TMP is used as the write temporary pointer 11: TMP is used as the read temporary pointer 3 Sz 0 R/W Transfer Size Selects data size of the bus cycle that is activated by the peripheral modules. 0: Byte transfer 1: Word transfer Rev. 3.00 Jan 25, 2006 page 173 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Bit 2 1 0 Bit Name BUD2 BUD1 BUD0 Initial Value 1 1 0 R/W R/W R/W R/W Description Boundary 2 to 0 These bits select the FIFO size and the existence of boundary overflow. 000: 32 bytes 001: 64 bytes 010: 128 bytes 011: 256 bytes 100: 512 bytes 101: 1024 bytes 110: 2048 bytes 111: Boundary is not set Legend: X: Don't care Table 8.1 shows how to make settings for BAR, RAR, WAR, and TMP. In BAR, the bits upper than the boundary become valid depending on the number of FIFO bytes set in the BUD2 to BUD0 bits. Since the lower bits become invalid, 0 should be written to these bits. In RAR, WAR, and TMP, the bits lower than the boundary become valid. Since the upper bits become invalid, 0 should be written to these bits. Table 8.1 Valid Bits in BAR, RAR, WAR, and TMP BAR Invalid Section (Should be set to 0) A4 A5 and A4 A6 to A4 A7 to A4 A8 to A4 A9 to A4 A10 to A4 Invalid Sections in RAR, WAR, and TMP Valid Sections (Should be set to 0, in RAR, WAR, no carry) and TMP A10 to A5 A10 to A6 A10 to A7 A10 to A8 A10 and A9 A10 -- A4 to A0 A5 to A0 A6 to A0 A7 to A0 A8 to A0 A9 to A0 A10 to A0 Number of FIFO Bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes BAR Valid Section A19 to A5 A19 to A6 A19 to A7 A19 to A8 A19 to A9 A19 to A10 A19 to A11 Rev. 3.00 Jan 25, 2006 page 174 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.11 Data Transfer Control Register B (DTCRB) DTCRB is a register provided in each pointer set that controls the operation of the interrupt flag in each pointer set and the data transfer between pointers. Bit 7 Bit Name BOVF_RE Initial Value 0 R/W R/W Description Boundary Overflow Enable (at reading) Selects whether to reflect RAR boundary overflow to the BOVF_R flag in DTSTRC. 0: Boundary overflow (at reading) is not reflected to the BOVF_R flag 1: Boundary overflow (at reading) is reflected to the BOVF_R flag 6 BOVF_WE 0 R/W Boundary Overflow Enable (at writing) Selects whether to reflect WAR boundary overflow to the BOVF_W flag in DTSTRC. 0: Boundary overflow (at writing) is not reflected to the BOVF_W flag 1: Boundary overflow (at writing) is reflected to the BOVF_W flag 5 FULLE 0 R/W FIFO Full Enable Selects whether to reflect detection of FIFO full (generation of WAR = RAR or TMP = WAR (when the read temporary pointer is selected) according to the write bus cycle) to the FULL flag in DTSTRC. 0: FIFO full detection is not reflected to the FULL flag 1: FIFO full detection is reflected to the FULL flag 4 EMPTYE 0 R/W FIFO Empty Enable Selects whether to reflect detection of FIFO empty (generation of RAR = WAR or TMP = RAR (when the write temporary pointer is selected) according to the read bus cycle) to the EMPTY flag in DTSTRC. 0: FIFO empty detection is not reflected to the EMPTY flag 1: FIFO empty detection is reflected to the EMPTY flag Rev. 3.00 Jan 25, 2006 page 175 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Bit 3 Bit Name LOAD Initial Value 0 R/W W Description Pointer Reload If this bit is set to 1 when the TMP settings are made, this bit copies the contents of TMP to RAR or WAR. When the read temporary pointer is used, the contents of TMP are copied to RAR. When the write temporary pointer is used, the contents of TMP are copied to WAR. 2 MARK 0 W Pointer Mark If this bit is set to 1 when the TMP settings are made, this bit copies the contents of RAR or WAR to TMP. When the read temporary pointer is used, the contents of RAR are copied to TMP. When the write temporary pointer is used, the contents of WAR are copied to TMP. 1 REST 0 W Pointer Reset When this bit is set to 1, this bit initializes RAR, WAR, and TMP, and also returns the status to FIFO empty state. 0 STCLR 0 W Status Clear Clears information of FIFO full and FIFO empty. Note: Do not set bits 1 and 0 to 1 simultaneously. 8.2.12 Data Transfer Status Register C (DTSTRC) DTSTRC is a register provided in each pointer set. DTSTRC includes the interrupt flags for each pointer set. When any one bit of bits 7 to 4 is set to 1, a flag corresponding to the pointer set number in DTSTRA is set. When any one bit of bits 3 and 2 is set to 1, a flag corresponding to the pointer set number in DTSTRB is set. Rev. 3.00 Jan 25, 2006 page 176 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Bit 7 Bit Name BOVF_R Initial Value 0 R/W R/(W) Description Boundary Overflow (at reading) Indicates detection of boundary overflow in RAR or TMP (when the read temporary pointer is selected). This flag can be masked by the BOVF_RE bit in DTCRB. 6 BOVF_W 0 R/(W) Boundary Overflow (at writing) Indicates detection of boundary overflow in WAR or TMP (when the write temporary pointer is selected). This flag can be masked by the BOVF_WE bit in DTCRB. 5 FULL 0 R/(W) FIFO Full Indicates detection of FIFO full (generation of WAR = RAR or TMP = WAR (when the read temporary pointer is selected) according to the write bus cycle). This flag can be masked by the FULLE bit in DTCRB. 4 EMPTY 0 R/(W) FIFO Empty Indicates detection of FIFO empty (generation of WAR = RAR or TMP = RAR (when the write temporary pointer is selected) according to the read bus cycle). This flag can be masked by the EMPTYE bit in DTCRB. 3 OVER_R 0 R/(W) FIFO Over Read Indicates detection of FIFO empty (when a read request is generated while RAR = WAR or TMP = RAR (when the write temporary pointer is selected)). 2 OVER_W 0 R/(W) FIFO Over Write Indicates detection of FIFO full (when a write request is generated while WAR = RAR or TMP = WAR (when the read temporary pointer is selected)). 1, 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 177 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.13 Data Transfer ID Register (DTIDR) DTIDR is a register provided in each pointer set. DTIDR selects the peripheral module, which is an activation source of each pointer set. A 4-bit ID has been assigned to the peripheral modules. DTIDR selects two IDs. The ID selected by DTIDR is enabled by setting the IDE-A and IDE-B bits in DTCRA to 1. When selecting an ID, the following two points should be noted: * To select two IDs, the IDs should be combined such that the data transfer direction is read and write. * The same IDs should not be selected over several pointer sets. Bit 7 6 5 4 3 2 1 0 Bit Name ID-A3 ID-A2 ID-A1 ID-A0 ID-B3 ID-B2 ID-B1 ID-B0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description ID-A Select These bits write the ID number to be selected by the IDE-A bit. ID-B Select These bits write the ID number to be selected by the IDE-B bit. 8.2.14 Data Transfer ID Read/Write Select Register A (DTIDSRA) DTIDSRA selects the direction for transferring ID15 to ID8. As IDs have already been assigned for the peripheral modules, the transfer direction is fixed. For details, refer to section 8.8, Operation. Bit 7 6 5 4 3 2 1 0 Bit Name IDRW15 IDRW14 IDRW13 IDRW12 IDRW11 IDRW10 IDRW9 IDRW8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description ID15 R/W to ID8 R/W These bits select the direction for transferring peripheral modules with ID numbers 15 to 8. 0: RAM Peripheral modules (write) 1: Peripheral modules (read) RAM Rev. 3.00 Jan 25, 2006 page 178 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.15 Data Transfer ID Read/Write Select Register B (DTIDSRB) DTIDSRB selects the direction for transferring ID7 to ID0. As IDs have already been assigned for the peripheral modules, the transfer direction is fixed. For details, refer to section 8.8, Operation. Bit 7 6 5 4 3 2 1 0 Bit Name IDRW7 IDRW6 IDRW5 IDRW4 IDRW3 IDRW2 IDRW1 IDRW0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description ID7 R/W to ID0 R/W These bits select the direction for transferring peripheral modules with ID numbers 7 to 0. 0: RAM Peripheral modules (write) 1: Peripheral modules (read) RAM 8.2.16 Data Transfer Status Register A (DTSTRA) DTSTRA includes interrupt flags for each pointer set. Bit 7 to 4 3 2 1 0 Bit Name -- DTF3 DTF2 DTF1 DTF0 Initial Value All 0 0 0 0 0 R/W R/(W) R/(W)* R/(W)* R/(W)* R/(W)* Description Reserved The initial value should not be changed. Data Transfer Interrupt Flags 3 to 0 These are interrupt flags for pointer set numbers 3 to 0. 0: No interrupt source 1: Any one flag of BOVF_R, BOVF_W, FULL, or EMPTY is set to 1 Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Jan 25, 2006 page 179 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.17 Data Transfer Status Register B (DTSTRB) DTSTRB includes error interrupt flags for each pointer set. Bit 7 to 4 3 2 1 Bit Name -- DTEF3 DTEF2 DTEF1 Initial Value All 0 0 0 0 R/W R/(W) R/(W)* R/(W)* R/(W)* Description Reserved The initial value should not be changed. Data Transfer Error Interrupt Flags 3 to 1 These are error interrupt flags for pointer set numbers 3 to 1. 0: No interrupt source 1: Either flag of OVER_R or OVER_W is set to 1 0 DTEIE 0 R/W Data Transfer Error Interrupt Enable 0: Disables an interrupt generated by DTEF3 to DTEF1. 1: Enables an interrupt generated by DTEF3 to DTEF 1. Note: * Only 0 can be written, to clear the flag. 8.2.18 Data Transfer Control Register C (DTCRC) DTCRC includes a bit to assign the ID-6 and ID-7 functions. Bit 7, 6 5 to 0 Bit Name -- -- Initial Value All 0 All 0 R/W R/(W) R Description Reserved The initial value should not be changed. Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 180 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.2.19 Data Transfer Control Register D (DTCRD) DTCRD includes enable bits for each pointer set. When the DTE bit is cleared to 0 and then reset to 1, the empty information is restored. Bit 7 to 4 3 2 1 0 Bit Name -- DTE3 DTE2 DTE1 DTE0 Initial Value All 0 0 0 0 0 R/W R/(W) R/W R/W R/W R/W Description Reserved The initial value should not be changed. Data Transfer Enable 3 to 0 These are enable bits for pointer set numbers 3 to 0. 0: Disables pointer set 1: Enables pointer set 8.2.20 Bit 7 to 4 3 2 1 0 Data Transfer Interrupt Enable Register (DTIER) Bit Name -- DTIE3 DTIE2 DTIE1 DTIE0 Initial Value All 0 0 0 0 0 R/W R/(W) R/W R/W R/W R/W Description Reserved The initial value should not be changed. Data Transfer Interrupt Enable 3 to 0 These are interrupt enable bits for pointer set numbers 3 to 0. 0: Disables an interrupt generated by DTF 1: Enables an interrupt generated by DTF 8.2.21 Data Transfer Register Select Register (DTRSR) DTRSR specifies the pointer set number or FIFO status/register/pointer accessed by FSTR. The resource of the specified pointer number can be accessed from FSTR, DTCRA, DTCRB, DTCRC, DTIDR, and DTSTRC by specifying the pointer set number. Rev. 3.00 Jan 25, 2006 page 181 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Bit 7 6 5 4 Bit Name CHS2 CHS1 CHS0 RS Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Pointer Number Select These bits represent the pointer set number to be accessed from FSTR, DTCRA, DTCRB, DTIDR, and DTSTRC. Register Select Selects whether to access register/pointer or FIFO status by FSTR. 0: FSTR accesses register/pointer 1: FSTR accesses FIFO status 3 2 POS1 POS0 0 0 R/W R/W Register/Pointer Select 1, 0 These bits select the register/pointer to be accessed by FSTR while the RS bit is 0. 00: The base address register (BAR) is accessed by FSTR 01: The read address pointer (RAR) is accessed by FSTR 10: The write address pointer (WAR) is accessed by FSTR 11: The temporary pointer (TMP) is accessed by FSTR 1 0 STS1 STS0 0 0 R/W R/W FIFO Status Selects 1, 0 These bits select the FIFO status to be accessed by FSTR while the RS bit is 1. 00: The valid data byte number (DATATN) is accessed by FSTR 01: The free area byte number (FREEN) is accessed by FSTR 10: The read start address (NRA) is accessed by FSTR 11: The write start address (NWA) is accessed by FSTR To access NWA, NRA, FREEN, or DATATN while the RS bit is 0, write 1 to the RS bit twice. Rev. 3.00 Jan 25, 2006 page 182 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.3 Activation Source and Priority The RFU operates upon a request from the peripheral modules regarding it as an activation source. In SCI, the request from the peripheral modules is an event that indicates 1-byte data transfer completion, such as setting the TDRE and RDRF bits. However, in USB, the request from the peripheral modules is an internal event that cannot be referenced by a CPU instruction. A total of 14 ID numbers have been assigned to the request from the peripheral modules. A peripheral module to which an ID number has not been assigned cannot use the RFU. Table 8.2 summarizes the correspondence between the ID numbers and activation sources. When the RFU accepts multiple activation sources simultaneously, the RFU selects the ID with the highest priority. The ID is classified into two groups, and the priority inter-groups is fixed. The initial priority in the group is as shown in table 8.2. However, the priority is changed whenever the RFU performs processing. The priority in the group is like a loop, that is, the priority of the processed ID number becomes the lowest, and the priority of the next ID number becomes the highest. Table 8.2 Correspondence between Activation Sources and ID Numbers Activation Source EP4 EP5 EP9 EP10 EP11 EP12 EP6I EP6O RDRF TDRE RDRF TDRE MCIF Multimedia card Multimedia card MCIF Transfer Direction RAM USB USB RAM RAM USB USB RAM RAM USB USB RAM RAM USB USB RAM SCI_0 RAM RAM SCI_0 SCI_2 RAM RAM SCI_2 RAM Multimedia card Multimedia card RAM Transfer Size Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Lowest Lowest Lowest Highest B Priority in Priority Group (Initial Inter-Groups Value) Group (Fixed) Highest A Highest ID Peripheral Number Module 0 1 2 3 4 5 6 7 8 9 10 11 12 13 USB USB USB USB USB USB USB USB SCI_0 SCI_0 SCI_2 SCI_2 MCIF MCIF Rev. 3.00 Jan 25, 2006 page 183 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.4 RAM-FIFO Location The RAM-FIFO should be allocated at the addresses H'(FF)E080 to H'(FF)EFFF and H'FF0800 to H'FF1FFF in on-chip RAM. Do not allocate the RAM-FIFO at the external address space. 8.5 RAM-FIFO Pointer The RAM-FIFO specifies the start address by BAR, and the size by the BUD2 to BUD0 bits in DTCRA. BAR and the BUD2 to BUD0 bits in DTCRA should be set so that the RAM-FIFO areas of all pointer sets are stored in the on-chip RAM area, and the RAM-FIFO areas do not overlap inter-pointer sets. The RAM-FIFO can be accessed when the value of the sum of the contents of BAR and either the contents of RAR, WAR, TMP, is output to the address bus. 8.6 RAM-FIFO Manipulation and RFU Bus Cycles Table 8.4 summarizes the requests from the peripheral modules to the RFU and manipulations of the RFU bus cycle and pointer. The RFU returns an acknowledge signal for a request from the peripheral modules to clear the request. All RFU bus cycles are executed in two states. In the RFU bus cycle, data transfer is executed or the error status is notified in addition to clearing a request and the RFU pointer is manipulated simultaneously. In data transfer in the RFU bus cycle, the RAM address is output to the address bus, the ID of the peripheral module is specified, and data transfer from RAM to the peripheral module or from peripheral module to RAM is executed in one bus cycle, simultaneously. An RFU bus cycle other than the read/write cycle is two states. There are four types of requests from the peripheral modules: Data transfer, pointer mark (RAR/WAR TMP), pointer reload (TMP RAR/WAR), and pointer reset (0 RAR, WAR, TMP). When data transfer is executed, either RAR or WAR is added for the number of transfer bytes, according to the settings of the transfer direction and the byte/word transfer. As one TMP is provided in a pointer set, TMP is used as either the read temporary pointer or write temporary pointer. If the added contents exceed the FIFO size specified by bits BUD2 to BUD0 in DTCRA, the pointer is set to a value from which the FIFO size is decremented (remainder of the FIFO size). Rev. 3.00 Jan 25, 2006 page 184 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) All peripheral modules perform a handshake following data transfer to update the pointer, depending on approval/refusal of the handshake. In this case, TMP is used during data transfer until a handshake. When the handshake is approved, the contents of RAR/WAR are regarded as the formal contents of the pointer, and are sent to TMP (mark operation). When the handshake is refused, the contents of RAR/WAR are restored to the previous contents, so the contents of TMP are sent to RAR or WAR (reload operation). In the pointer reset operation, RAR, WAR, and TMP are all cleared to 0. Table 8.3 RFU Bus Cycle Types USB O O O O SCI O -- -- -- MCIF O -- -- -- Peripheral Module Request Data transfer Pointer mark Pointer reload Reset Rev. 3.00 Jan 25, 2006 page 185 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Table 8.4 Requests from Peripheral Modules and RFU Bus Cycle Transfer Condition and FIFO Pointer Status RAM peripheral modules TMP is not used Other than the following RAR = WAR after RAR addition RFU Bus Cycle Contents RAM read, peripheral module write cycle RAM read, peripheral module write cycle Notification of FIFO empty state RAR = WAR RAM peripheral modules TMP is used as a read temporary pointer Other than the following RAR = WAR after RAR addition Notification of FIFO overread state RAM read, peripheral module write cycle RAM read, peripheral module write cycle Notification of FIFO empty state RAR = WAR Peripheral modules RAM TMP is not used Other than the following WAR = RAR after WAR addition Notification of FIFO overread state RAM read, peripheral module write cycle Peripheral module read, RAM write cycle Notification of FIFO full state WAR = RAR Peripheral modules RAM TMP is used as a write temporary pointer Other than the following WAR = RAR after WAR addition Notification of FIFO overwrite state RAM read, peripheral module write cycle Peripheral module read, RAM write cycle Notification of FIFO full state WAR = RAR Notification of FIFO overwrite state No pointer manipulations No pointer manipulations Adds WAR Adds WAR No pointer manipulations Adds WAR Adds WAR No pointer manipulations Adds RAR Adds RAR Pointer Manipulation Adds RAR Adds RAR Requests from Peripheral Modules Data transfer Rev. 3.00 Jan 25, 2006 page 186 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Requests from Peripheral Modules Pointer mark Transfer Condition and FIFO Pointer Status TMP is not used TMP is used as a read temporary pointer TMP is used as a write temporary pointer RFU Bus Cycle Contents Acknowledge only Acknowledge only Acknowledge only Acknowledge only Acknowledge only Acknowledge only Acknowledge only Pointer Manipulation No pointer manipulations RAR TMP WAR TMP No pointer manipulations TMP RAR TMP WAR No pointer manipulations Pointer reload TMP is not used TMP is used as a read temporary pointer TMP is used as a write temporary pointer Pointer reset -- Rev. 3.00 Jan 25, 2006 page 187 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.7 8.7.1 RFU Bus Cycle Clock Division As this LSI supports medium-speed mode, current consumption can be reduced by dividing the operating clock of the bus master. On the other hand, high-speed response may be requested of the RFU, which is one of the bus masters. In particular, if the RFU is used as a slave of a host interface, such as the USB, transfer data should be supplied with a sufficient transfer rate. The RFU does not support medium-speed mode. The clock division in the medium-speed mode should be temporarily suspended to switch the clock to high-speed mode by setting the DTSPEED bit in SBYCR to 1 during DTC and RFU operations (and during CPU operation when transfer request is generated). The clock division is restored to high-speed mode from medium-speed mode after high-speed 1- to 2-state clocks when the RFU activation request is generated. CPU bus cycle T1 T2 CPU bus cycle T1 T2 RFU bus cycle T1 T2 T1 CPU bus cycle T2 Bus master clock RFU activation request 1 state CPU bus cycle T1 T2 CPU bus cycle T1 T2 RFU bus cycle T1 T2 T1 CPU bus cycle T2 Bus master clock 2 states RFU activation request Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode Rev. 3.00 Jan 25, 2006 page 188 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.7.2 RFU Bus Cycle Insertion The RFU bus cycle can be inserted at a break in the bus cycle under almost all conditions. Table 8.5 summarizes a comparison of enabling/disabling bus cycle insertion for the DTC and RFU. The RFU bus cycle can be inserted with the same condition as the DTC when the BUSDIVE bit in BCR2 is cleared to 0. Table 8.5 Bus Cycle Insertion RFU Enabled Enabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Enabled Disabled Enabled Disabled DTC Enabled Enabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled -- -- -- -- -- Bus Cycle Condition CPU internal operation cycle The end of CPU bus cycle The end of upper-byte CPU bus cycle for divided word access The end of upper-word CPU bus cycle for divided long word access The end of each CPU bus cycle for EEPMOV instruction The end of each CPU bus cycle for STM/LDM instruction The end of each CPU bus cycle for bit manipulation instruction The end of CPU bus cycle for CCR manipulation instruction The end of each CPU bus cycle for stacking/unstacking processing The end of each CPU bus cycle for vector address read The end of each DTC bus cycle for vector address read The end of accessing DTC control register (32 bits x 3) The end of the first and second long word bus cycles for accessing DTC control register (32 bits x 3) The end of DTC bus cycle The end of upper-byte DTC bus cycle for divided word access 8.7.3 RFU Response Time Figure 8.3 shows an example of the RFU response time. The RFU response time consists of the following: * Cycle to synchronize peripheral module signals with the system clock: 1 and 2 states * Cycle to output a request from the peripheral modules: 1 to 5 states * Cycle to wait for the end of the current bus cycle: 0 to 2 states (except for wait states for external extension) Rev. 3.00 Jan 25, 2006 page 189 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) * RFU bus cycle: 2 states * Cycle to synchronize the RFU signal with the peripheral module clock: 1 and 2 states (depending on the peripheral module clock) The total of the above cycles is 5 to 13 states. Cycles for synchronization of the peripheral module clock with the system clock are needed even when the hardware FIFO is used instead of the RFU. Therefore, RAM-FIFO overhead by the RFU is 3 to 10 states (except for wait states for external extension). To reduce the RFU response time, it is recommended to set the external extension area access to 3 states/no waits. CPU bus cycle T1 T2 CPU bus cycle T1 T2 CPU bus cycle T1 T2 RFU bus cycle T1 T2 CPU bus cycle T1 T2 CPU bus cycle T1 T2 12-MHz clock for the USB SB0V*1 SB1V*2 RFU activation request RFU bus cycle System clock Request output Cycle to wait RFU bus cycle Synchronization System clock synchronization cycle cycle for the end of cycle with synchronizatioin the current the peripheral cycle bus cycle module clock Notes: 1. USB SENDBUFCR SB0V bit: Transmit buffer 0 valid bit 2. USB SENDBUFCR SB1V bit: Transmit buffer 1 valid bit Figure 8.3 Example of RFU Response Time Rev. 3.00 Jan 25, 2006 page 190 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.8 Operation The RFU is presupposed to operate with the following procedure: * Enable ID to be written to the RFU, and store data received by the peripheral module into FIFO. * Enable ID to be read from the RAM-FIFO, and supply data transmitted by the peripheral module from FIFO. Two IDs can be enabled simultaneously. However, when OVER-READ or OVER-WRITE error status occurs, sufficient error processing may not be made. Thus, the processing should be made with a sufficient number of valid data bytes and free area bytes. When the CPU reads and uses the received data, the read start address of the pointer status and the number of valid data bytes are used. When the CPU generates data to be transmitted, data is written to on-chip RAM, and then the RAM address where data is stored in the pointer is written. 8.8.1 Transmission/Reception of Single Data Block To transmit a single data block or to receive a data block with a known number of bytes, boundary overflow is convenient. Even if the peripheral module does not include a function to generate an interrupt at the completion of the specified number of bytes of transfer data, the completion of data block transmission/reception can be acknowledged by an interrupt from the RFU side. This interrupt is generated when the RFU pointer reaches the boundary of the FIFO size specified by bits BUD2 to BUD0 in DTCRA. Table 8.6 summarizes the settings when boundary overflow is used. Rev. 3.00 Jan 25, 2006 page 191 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Table 8.6 Settings when Using Boundary Overflow (Transmission/Reception of Single Data Block) RAM Peripheral Modules -- BUD2 to BUD0 BAR N_R Sz Clear the bits lower than the boundary to 0 according to the FIFO size. Sz - N_R 0 Peripheral Modules RAM N_W Sz Clear the bits lower than the boundary to 0 according to the FIFO size. Sz - N_W Sz - N_W Transfer Condition Number of transfer data bytes FIFO size Base address Read pointer Write pointer RAR WAR When the number of transfer data bytes has been transmitted from RAM to the peripheral modules the read pointer becomes 0, and boundary overflow occurs. At this time, the BOVF_R flag in DTSTRC is set to 1. When the number of transfer data bytes has been received from the peripheral modules to RAM, the write pointer becomes 0, and boundary overflow occurs. At this time, the BOVF_W flag in DTSTRC is set to 1. 8.8.2 Transmission/Reception of Consecutive Data Blocks If the peripheral module includes a function to generate an interrupt request at the completion of the specified number of bytes of transfer data, data blocks can be processed consecutively according to the following procedure. An example in which the ID to be written to the RFU is enabled and receive data is processed by the CPU is shown below. 1. The pointer set is initialized. 2. ID of RFU write is enabled. 3. Data transfer of the corresponding peripheral module is initiated. 4. Data block receive end interrupt (peripheral module). 5. RAR and DATAN are read from, and receive data block processing is started by the CPU. When FIFO has sufficient free area after starting the CPU processing at the 5th step, the next block transfer can be started, returning to the 3rd step. At this time, the RFU is the FIFO-size ring buffer, specified by bits BUD2 to BUD0 in DTCRA. If the contents of the RFU pointer exceed the FIFO size, it automatically becomes the remainder of Rev. 3.00 Jan 25, 2006 page 192 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) the FIFO size. Programming should be such that the CPU access does not deviate from the FIFO area. 8.8.3 RFU Manipulation by USB Figure 8.4 is a block diagram of the RFU interface in the USB. The USB can use the RFU for data transfer with end point 4 (EP4) and end point 5 (EP5). The USB has a 2-byte transmit buffer in end point 4 dedicated for IN transfer. The USB also has a 2byte receive buffer in end point 5 dedicated for OUT transfer. Figure 8.5 shows the operational flow for IN transfer. EP4 is bulk IN transfer. When the transmit data is written to the FIFO, and start of transmission is triggered (the PTTE bit is set to1), the USB issues a data transfer request to the RFU, and the 2-byte transmit buffer is filled and enters an output enable state. When the host issues an IN transfer request, the USB transmits data in the transmit buffer. The USB issues data transfer requests until data of MAX_PACKET_SIZE bytes is transferred to the transmit buffer, and operates such that the transmit buffer is always filled. When the transmission for MAX_PACKET_SIZE bytes is completed, the USB issues a mark/reload (rewind) request to the RFU according to the ACK/NACK handshake received from the host. If the FIFO underruns (OVER-R) during transmission, transmission ends correctly by regarding the data packet as a short packet. If the transmit buffer underruns, the USB transmits abnormal data to lead to the NACK handshake from the host. Figure 8.6 shows the operational flow for OUT transfer. EP5 is bulk OUT transfer. The USB writes the received data to the receive buffer. When data is stored in the receive buffer, the USB issues the data transfer request, and operates such that the receive buffer is always empty. When the reception for MAX_PACKET_SIZE bytes completes, and all data in the receive buffer is transferred to the FIFO, the USB transmits the ACK handshake to the host, and requests a mark to the RFU. If an error is detected from the received data or all received data cannot be transferred to the FIFO, the USB transmits the NACK handshake to the host, and requests a reload (rewind) to the RFU. FIFO overrun (OVER-W) and receive buffer overrun can be regarded as the error status. Rev. 3.00 Jan 25, 2006 page 193 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) USB host (12 Mbps) Function core section (USB protocol processing section) Re-reception request Data clear request Data mark/rewind request Re-reception request Approval/refusal Re-transmission request Transmission data (12 MHz) Transmission data (12 MHz) EP4 transmit buffer (2-byte buffer) EP5 receive buffer (2-byte buffer) USB Data mark/rewind request Data caching request Data clear request Approval/refusal Re-transmission request Transmisison data Reception data (8 MHz to 24 MHz) (8 MHz to 24 MHz) Internal data bus RFU Data area for Data area for communication On-chip RAM communication (10 kbytes) pipe 1 pipe 2 (32 to 2048 bytes) (32 to 2048 bytes) This LSI Figure 8.4 RFU Interface of USB Rev. 3.00 Jan 25, 2006 page 194 of 872 REJ09B0286-0300 Approval/refusal Approval/refusal Section 8 RAM-FIFO Unit (RFU) Hardware (USB, RFU) IDLE (A) Receive IN token From the host No Is EP4 stalled? Token phase Firmware (CPU) Start USBID interrupt handling Yes Does EP4 transmit buffer perform look-ahead processing? Yes Has the EP4 transmit buffer completed look-ahead processing? Yes The case of 0 data packet transmission can be regarded as look-ahead processing completion. No Read USBIFR0 and USBIFR1 to judge an interrupt source TS Read TSFR0 to confirm the EP4TS interrupt TF Read TFFR0 to confirm the EP4TF interrupt No Does RFU/FIFO have data? Yes No No Is it necessary to write data to RFU/FIFO? Yes Write data to RFU/FIFO (MMC, etc.) No data phase Data phase Does the EP4 transmit buffer underrun? Yes No Does the RFU/FIFO underrun? Yes Transmit MaxPacketSize data Transmit ShortPacketSize data No Including 0 data packet Transmit bit stuff error packet to the host to cause timeout error No data phase Start data transmission to the host Set the EP4TE bit to 1 in PTTER0 Request EP4 transmit buffer look-ahead processing End data trasmission to the host Handshake phase Clear interrupt flag Is ACK handshake packet received from the host? Yes Receive ACK packet From the host End data transmission correctly Transmit STALL packet Transmit NAK packet No End USBID interrupt processing From the device No handshake (timeout) From the device End data transmission abnormally Is look-ahead processing complete? No Yes Start look-ahead processing Lock the transmit buffer No Abnormally end during data phase? Yes Manipulate pointer update to the RFU Manipulate pointer rewind to the RFU Write 0- to 2-byte data to the transmit buffer Set the EP4TF interrupt flag Cancel transmit buffer lock End look-ahead processing Writing 0-byte data means 0-data packet transmission. Set the EP4TS interrupt flag Request USBID interrupt To (A) IDLE Figure 8.5 Operation Flow of USB IN Transfer Rev. 3.00 Jan 25, 2006 page 195 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Hardware (USB, RFU) IDLE Firmware (CPU) (B) Receive OUT token from the host Start USBID interrupt handling Read from USBIFR0 and USBIFR1 to judge an interrupt source TS Read TSFR0 to confirm the EP5TS interrupt TF Read TFFR0 to confirm the EP5TF interrupt UDTR Read UDTRFR to confirm the EP5UDTR interrupt No Is EP5 stalled? Token phase Yes Is EP5 receive buffer empty? Yes No For instance, the RFU update processing of previous data communication is not completed No Is it necessary to read data from RFU/FIFO? Yes No Is receive buffer busy ? Yes Start data reception from the host The host transmits data but it is not received by the device side No When the interrupt is EP5UDTR request The host transmits data but it is not received by the device side Read data from RFU/FIFO (MMC, etc.) Does the EP5 receive buffer overrun? Yes Data phase Clear interrupt flag End USBID interrupt processing Does received data include any errors? Yes End data reception from the host No From the device Handshake phase From the device Transmit STALL packet Transmit NAK packet No handshake (timeout) Transmit ACK packet From the device Is EP5 receive buffer empty? Yes No End data transmission abnormally Does RFU/FIFO overrun? Yes Write data to RFU/FIFO End data transmission correctly Set the EP5UTDR interrupt flag Manipulate pointer update to the RFU Set the EP5TF interrupt flag No Abnormally end during data phase? Yes Manipulate pointer rewind to the RFU No Set the EP5TS interrupt flag Request USBID interrupt To (B) IDLE Figure 8.6 Operation Flow of USB OUT Transfer Rev. 3.00 Jan 25, 2006 page 196 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.8.4 RFU Manipulation by SCI Figure 8.7 is a block diagram of the RFU interface in the SCI. The SCI can use the RFU for data transmission and reception. The RFU is activated by setting the TDRE flag and the RDRF flag. Figure 8.8 shows the operational flow for transmission. When the transmitted data is written to the FIFO, and start of transmission is triggered (the TDRE and RDRF flags in SSR are set to 1), the SCI issues a data transfer request to the RFU. Figure 8.9 shows the operational flow for reception. TxD This LSI SCI RxD RFU interface TSR RSR TDR RDR Transmit data Receive data Transmission request Reception request Approval Data bus RFU On-chip RAM Figure 8.7 RFU Interface of SCI Rev. 3.00 Jan 25, 2006 page 197 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Prepare transmit data in RAM Initialize the RFU Initialize the SCI Set TDRE_DTE in SCIDTER to 1 Set TE in SCR to 1 RFU activation request Overread RAM data? Yes No Transfer transmit data from RAM to TDR Start transmission TDRE = 1 Yes No TDRE_DTE in SCIDTER are automatically cleared to 0 TEND = 1 Yes End No Figure 8.8 Operation Flow of SCI Transmission Rev. 3.00 Jan 25, 2006 page 198 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Initialize the RFU Initialize the SCI Set RDRF_DTE in SCIDTER to 1 Set RE in SCR to 1 Start reception RDRF = 1 Yes No RFU activation request Overwrite RAM? Yes No Transfer receive data from RDR to RAM RDRF_DTE in SCIDTER are automatically cleared to 0 End Figure 8.9 Operation Flow of SCI Reception Rev. 3.00 Jan 25, 2006 page 199 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.8.5 RFU Manipulation by MCIF Figure 8.10 is a block diagram of the RFU interface in the MCIF. The MCIF can use the RFU for data transmission and reception. Figure 8.11 shows the operational flow for transmission. When the transmitted data is written to the RFU, and start of transmission is triggered (the DATAEN bit in OPCR is set), the MCIF issues a data transfer request to the RFU. Figure 8.12 shows the operational flow for reception. Multimedia card This LSI MCIF Multimedia card bus (Max. 20 Mbps) Data transmission/reception control Transmit data (Max. 20 MHz) Receive data (Max. 20 MHz) RFU interface Transmit buffer (1byte) Receive buffer (1byte) Read data Write request Write data Read request Approval Internal data bus RFU On-chip RAM Figure 8.10 RFU Interface of MCIF Rev. 3.00 Jan 25, 2006 page 200 of 872 REJ09B0286-0300 Approval Section 8 RAM-FIFO Unit (RFU) When the RFU is emptied during data transmission, the transmission resume trigger (the DATAEN bit in OPCR is set) is set once the RFU empty is cancelled (after the necessary data is written), and data transmission is resumed. When data reception is started, data is automatically written to the RFU. When the RFU is filled during data reception, the reception resume trigger (the RD_CONTI bit in OPCR is set) is set once the RFU full is cancelled (after the necessary data is read from the RFU), and data reception is resumed. Hardware (MCIF, RFU) Command transmission (data transmission to multimedia card) (Data transmission start) NO Firmware (CPU) Command transmission (data transmission to multimedia card) Data transmission start instruction Data transmission start instruction? YES Previous data read sequence Card clock stop (reception halted) NO FIFO empty Data transmission command sequence ended? NO NO Data read from RFU ended? YES YES 1-byte data transmission to multimedia card FIFO empty cancellation (data write to RFU) Command sequence end YES All data transmission ended? NO YES Data transmission end Data transmission resumption instruction (Transmission resumption) YES FIFO empty cancellation waiting fo card clock stop (transmission halted) FIFO empty NO Empty cancellation 1-byte data read from RFU Figure 8.11 Operation Flow of MCIF Transmission Rev. 3.00 Jan 25, 2006 page 201 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) Hardware (MCIF, RFU) Command transmission (data transmission to multimedia card) Firmware (CPU) Command transmission (data reception from multimedia card) NO Data start bit received? NO FIFO full Data reception command sequence ended? YES NO YES 1-byte data reception from multimedia card Card clock stop (reception halted) Previous data write sequence YES FIFO full cancellation (data read from RFU) Command sequence end NO Data read from RFU ended? YES 1-byte data write to RFU Data reception resumption instruction All data reception ended? NO YES Data reception end (Reception resumption) YES FIFO full cancellation waiting for card clock stop (reception halted) FIFO full NO Full cancellation Figure 8.12 Operation Flow of MCIF Reception 8.9 Interrupt Sources The RFU supports six interrupts: Boundary overflow (at reading), boundary overflow (at writing), FIFO full, FIFO empty, FIFO overread, and FIFO overwrite. Identical interrupt vector addresses are assigned to boundary overflow (at reading), boundary overflow (at writing), FIFO full, and FIFO empty. When an interrupt is generated, the interrupt source can be judged by reading the interrupt flag in DTSTRC. In addition, FIFO overread and FIFO overwrite have common interrupt vector addresses. When an interrupt is generated, the interrupt source can be judged by reading the interrupt flag in DTSTRC. Rev. 3.00 Jan 25, 2006 page 202 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.10 RFU Initialization Figure 8.13 shows the initialization flow of the RFU. Clear DTE bit in DTCRD Disable the relevant pointer set Clear RAR, WAR, TMP Clear the pointer Clear DTSTRA, DTSTRB, DTSTRC Clear each setting Set BAR Set the base address Set DTCRA (Sz, BUD(2-0), PMD1, PMD0) Transfer word/byte data and set the boundary size and pointer mode Set DTCRB Enable use of status flags Set DTIDR, DTIDSRA, DTIDSRSB Assign an ID and set the transfer direction Set DTIER Set the interrupt enable bits Set DTCRA (IDE-A, IDE-B) Enable the ID Set DTE bit in DTCRD Set the pointer set enable bit Figure 8.13 RFU Initialization Flow 1. The initial state of the FIFO is the FIFO empty state. When a single data block is transferred from RAM to the peripheral module, first initialize the RFU and then clear the FIFO empty state by writing 1 to the STCLR bit in DTCRB. 2. If the DTE bit is cleared to 0, the FIFO full state is automatically canceled and then the FIFO empty state is entered. 3. In medium-speed mode, the DTSPEED bit in SBYCR should be set to 1. Rev. 3.00 Jan 25, 2006 page 203 of 872 REJ09B0286-0300 Section 8 RAM-FIFO Unit (RFU) 8.11 Usage Notes 1. Conflict between CPU write to DTRSR and RFU activation request If conflict occurs between a CPU write to the RS bit in DTRSR while it is 0 and an RFU activation request, data transfer by the RFU cannot be performed correctly. In order to access the FIFO state, the RS bit must be set to 1 at RFU initialization in advance. When the RS bit is cleared to 0, the CPU should not write to DTRSR during RFU data processing. 2. FIFO full and FIFO empty states When using a temporary pointer, the FIFO full and FIFO empty states during RFU data processing cannot be retained successfully, and overread or overwrite of data may occur. If making use of a temporary pointer, be sure to check on the number of bytes of valid data and free area for the FIFO, and the EMPTY and FULL flag states before data processing. 3. DATAN/FREEN read value If DATAN or FREEN is read in the FIFO full or FIFO empty state when the conditions listed in table 8.7 are satisfied, the read values may not be correct. When DATAN or FREEN is read as 0, whether the FIFO is full or empty needs to be checked by using the FULL and EMPTY bits in DTSTRC. Table 8.7 DATAN/FREEN Read Value Condition Write until the FIFO is full and request a mark (when TMP = RAR) Read until the FIFO is empty (when WAR = RAR) Read temporary pointer Write until the FIFO is full (when WAR = RAR) Read until the FIFO is empty and request a mark (when TMP = WAR) Temporary pointer not used Write until the FIFO is full Read until the FIFO is empty DATAN/FREEN Read Value DATAN = 0 even though the FIFO is full FREEN = 0 even though the FIFO is empty DATAN = 0 even though the FIFO is full FREEN = 0 even though the FIFO is empty DATAN = 0 even though the FIFO is full FREEN = 0 even though the FIFO is empty Pointer Mode Write temporary pointer 4. RFU operation in medium-speed mode This LSI does not support medium-speed mode operation of the RFU. When using the RFU in medium-speed mode, the DTSPEED bit in SBYCR must be set to 1. If the RFU is activated with the DTSPEED bit cleared to 0, the program may get out of control. Rev. 3.00 Jan 25, 2006 page 204 of 872 REJ09B0286-0300 Section 9 I/O Ports Section 9 I/O Ports Table 9.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data. DDR and DR are not provided for an input-only port. Ports 1 to 3, 6, and A have built-in input pull-up MOSs. For port A, the on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up MOSs. Ports 1 to 6, 9, and A can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Port 8 is an NMOS push-pull output. Table 9.1 Port Port Functions Extended Mode Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 Built-in input pull-up MOSs LED drive capability (sink current 5 mA) I/O Status Built-in input pull-up MOSs LED drive capability (sink current 5 mA) Description Mode 2, Mode 3 (EXPE = 1) P17/A7/CPA7 P16/A6/CPA6 P15/A5/CPA5 P14/A4/CPA4 P13/A3/CPA3 P12/A2/CPA2 P11/A1/CPA1 P10/A0/CPA0 Port General I/O port 1 also functioning as PWM output, CompactFlash address output, and address output Port General I/O port 2 also functioning as PWM output, CompactFlash address output, and address output P27/A15 P26/A14 P25/A13 P24/A12 P23/A11/CPREG P22/A10/CPA10 P21/A9/CPA9 P20/A8/CPA8 Rev. 3.00 Jan 25, 2006 page 205 of 872 REJ09B0286-0300 Section 9 I/O Ports Extended Mode Port Description Mode 2, Mode 3 (EXPE = 1) D15/CPD15 D14/CPD14 D13/CPD13 D12/CPD12 D11/CPD11 D10/CPD10 D9/CPD9 D8/CPD8 Port General I/O port 4 also functioning as interrupt input, TMR_0, TMR_1, TMR_X, TMR_Y, timer connection input/output, and MCIF inputs/ outputs Port General I/O port 5 also functioning as interrupt input, PWMX output, and SCI_0, SCI_1, and SCI_2 inputs/outputs P47/IRQ7/TMOY P46/IRQ6/TMOX P45/IRQ5/TMIY P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO P42/IRQ2/TMO0/ExMCDAT/ExMCRxD P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI P40/IRQ0/TMI0/ExMCCLK P57/IRQ15/PWX1 P56/IRQ14/PWX0 P55/IRQ13/RxD2 P54/IRQ12/TxD2 P53/IRQ11/RxD1/IrRxD P52/IRQ10/TxD1/IrTxD P51/IRQ9/RxD0 P50/IRQ8/TxD0 Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) P37/WUE15 P36/WUE14 P35/WUE13 I/O Status Built-in input pull-up MOSs LED drive capability Port General I/O port 3 also functioning as bidirectional data bus, CompactFlash bidirectional data bus, wake-up event input, and MCIF input/ output P34/WUE12/MCCMDDIR/ (sink current MCCSB 5 mA) P33/WUE11/MCDATDIR/ MCCSA P32/WUE10/MCDAT/ MCRxD P31/WUE9/MCCMD/ MCTxD P30/WUE8/MCCLK Rev. 3.00 Jan 25, 2006 page 206 of 872 REJ09B0286-0300 Section 9 I/O Ports Extended Mode Port Description Mode 2, Mode 3 (EXPE = 1) P67/CIN7/ 1 KIN7* 2 Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O Status Built-in input pull-up MOSs Port General I/O port 6 also functioning as bidirectional data bus, CompactFlash bidirectional data bus, FRT input/output, enhanced A/D conversion input, keyboard input, timer connection input/output, and external USB driver/receiver input/output D7/CPD7* P67/CIN7/KIN7/DPLS 2 P66/FTOB/CIN6/ D6/CPD6* P66/FTOB/CIN6/KIN6/ 1 KIN6/CBLANK* CBLANK/DMNS P65/FTID/CIN5/ D5/CPD5* P65/FTID/CIN5/KIN5/ 1 KIN5/CSYNCI* CSYNCI/XVERDATA 2 P64/FTIC/CIN4/ D4/CPD4* P64/FTIC/CIN4/KIN4/ 1 KIN4/CLAMPO* CLAMPO/TXDPLS 2 P63/FTIB/CIN3/ D3/CPD3* P63/FTIB/CIN3/KIN3/ 1 KIN3/VFBACKI* VFBACKI/TXDMNS 2 P62/FTIA/CIN2/ 1 KIN2/VSYNCI* D2/CPD2* P62/FTIA/CIN2/KIN2/ VSYNCI/TXENL 2 2 P61/FTOA/CIN1/ D1/CPD1* P61/FTOA/CIN1/KIN1/ 1 KIN1/VSYNCO* VSYNCO/SUSPEND P60/FTCI/CIN0/ D0/CPD0* P60/FTCI/CIN0/KIN0/ HFBACKI/SPEED KIN0/HFBACKI* 2 1 Port General input 7 port also functioning as A/D converter analog input, D/A converter analog output, and interrupt input P77/ExIRQ7/AN7/DA1 P76/ExIRQ6/AN6/DA0 P75/ExIRQ5/AN5 P74/ExIRQ4/AN4 P73/ExIRQ3/AN3 P72/ExIRQ2/AN2 Rev. 3.00 Jan 25, 2006 page 207 of 872 REJ09B0286-0300 Section 9 I/O Ports Extended Mode Port Description Mode 2, Mode 3 (EXPE = 1) P86/ExIRQ14/SCK2/ExTMIX P85/ExIRQ13/SCK1/ExTMI1 P84/ExIRQ12/SCK0/ExTMI0 P83/ExIRQ11/SDA1 P82/ExIRQ10/SCL1 P81/ExIRQ9/SDA0 P80/ExIRQ8/SCL0 Single-Chip Mode Mode 2, Mode 3 (EXPE = 0) I/O Status P87 to P80 are NMOS push-pull outputs. SDA1, SCL1, SDA0, and SCL0 are NMOS open drain outputs. Port General I/O port 8 also functioning as A/D converter external trigger input pin, SCI_0, SCI_1, and SCI_2 clock inputs/outputs, IIC_0 and IIC_1 inputs/outputs, ExTMR_0, ExTMR_1, ExTMR_X, and ExTMR_Y inputs, USB external clock input, and interrupt input Port General I/O port 9 also functioning as bus control input/output, CompactFlash control input/ output, system clock output, and external subclock input Port General I/O port A also functioning as address output, keyboard input, and SCI_0 and SCI_2 external control pins Notes: 1. 2. 3. 4. P87/ExIRQ15/ADTRG/ExTMIY/USEXCL P97/WAIT/CPWAIT/CS256 P96//EXCL AS/IOS HWR/CPWE RD/CPOE P92/CPCS1 P91/CPCS2 P90/LWR PA1/A17/ 3 KIN9/SSE2I* PA0/A16/ 3 KIN8/SSE0I* P97 P95 P94 P93 P92 P91 P90 PA1/KIN9/ PA1/KIN9/SSE2I 4 SSE2I* PA0/KIN8/SSE0I PA0/KIN8/ 4 SSE0I* Built-in input pull-up MOSs 8-bit data bus is selected. 16-bit data bus is selected. Extended mode (mode 2) Extended mode (mode 3) Rev. 3.00 Jan 25, 2006 page 208 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus, PWM output pins, and CompactFlash address output pins. Port 1 functions change according to the operating mode. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) 9.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In extended mode: The corresponding port 1 pins are address output or CompactFlash address output ports when P1DDR bits are set to 1, and input ports when cleared to 0. In single-chip mode: The corresponding port 1 pins are output ports or PWM outputs when the P1DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Jan 25, 2006 page 209 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P1DR stores output data for the port 1 pins that are used as the general output port. If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read. 9.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the port 1 built-in input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. Rev. 3.00 Jan 25, 2006 page 210 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.1.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. In the tables, the symbol "--" stands for Don't care. Extended Mode: The function of port 1 pins is switched as shown below according to the P1nDDR bit. P1nDDR Pin function Note: n = 7 to 0 0 P17 to P10 input pins 1 A7 to A0 output pins, CPA7 to CPA0 output pins Single-Chip Mode: The function of port 1 pins is switched as shown below according to the combination of the OEn bit in PWOERA of PWM and the P1nDDR bit. P1nDDR OEn Pin function Note: n = 7 to 0 0 -- P17 to P10 input pins 0 P17 to P10 output pins 1 1 PW7 to PW0 output pins 9.1.5 Port 1 Input Pull-Up MOS Port 1 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 9.2 summarizes the input pull-up MOS states. Table 9.2 Reset Off Port 1 Input Pull-Up MOS States Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off. Rev. 3.00 Jan 25, 2006 page 211 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.2 Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as an address bus, PWM output pins, and CompactFlash address output pins. Port 2 functions change according to the operating mode. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) 9.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In extended mode: The corresponding port 2 pins are address output or CompactFlash address output ports when the P2DDR bits are set to 1, and input ports when cleared to 0. Pins function as the address output port depending on the setting of bits IOSE and CS256E in SYSCR. In single-chip mode: The corresponding port 2 pins are output ports or PWM outputs when the P2DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Jan 25, 2006 page 212 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P2DR stores output data for the port 2 pins that are used as the general output port. If a port 2 read is performed while the P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while the P2DDR bits are cleared to 0, the pin states are read. 9.2.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 built-in input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1. Rev. 3.00 Jan 25, 2006 page 213 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.2.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. In the tables, the symbol "--" stands for Don't care. Extended Mode: The function of port 2 pins is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE and CPCSE bits in BCR2 of BSC, and the P2nDDR bit. Addresses 13 and 11 in the following table are expressed by the following logical expressions: Address 13 = 1:ADFULLE CS256E IOSE Address 11 = 1:ADFULLE CS256E CPCSE IOSE P2nDDR Address 13 Pin function 0 -- P27 to P25 input pins 0 A15 to A13 output pins 1 1 P27 to P25 output pins Notes: n = 7 to 5 Even if P2nDDR = 1 and CPCSE = 1, pins P27 to P25 can be used as output pins only when IOSE = 1. P24DDR Address 11 Pin function P23DDR Address 11 Pin function 0 -- P24 input pin 0 -- P23 input pin 0 A11 output pin, CPREG output pin 0 A12 output pin 1 1 P23 output pin 1 1 P24 output pin P2nDDR Pin function Note: n = 2 to 0 0 P22 to P20 input pins 1 A10 to A8 output pins, CPA10 to CPA8 output pins Rev. 3.00 Jan 25, 2006 page 214 of 872 REJ09B0286-0300 Section 9 I/O Ports Single-Chip Mode: The function of port 2 pins is switched as shown below according to the combination of the OEm bit in PWOERB of PWM and the P2nDDR bit. P2nDDR OEm Pin function Notes: n = 7 to 0 m = 15 to 8 0 -- P27 to P20 input pins 0 P27 to P20 input pins 1 1 PW15 to PW8 output pins 9.2.5 Port 2 Input Pull-Up MOS Port 2 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 9.3 summarizes the input pull-up MOS states. Table 9.3 Reset Off Port 2 Input Pull-Up MOS States Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off. 9.3 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, CompactFlash bidirectional data bus, wake-up event input, and MCIF input/output pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) Rev. 3.00 Jan 25, 2006 page 215 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In extended mode: The port functions as the data bus regardless of the values in these bits. In single-chip mode: The corresponding port 3 pins are output ports when the P3DDR bits are set to 1, and input ports when cleared to 0. 9.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In extended mode: If a port 3 read is performed while the P3DDR bits are set to 1, the P3DR values are read. When the P3DDR bits are cleared to 0, 1 is read. In single-chip mode: P3DR stores output data for the port 3 pins that are used as the general output port. If a port 3 read is performed while the P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while the P3DDR bits are cleared to 0, the pin states are read. Rev. 3.00 Jan 25, 2006 page 216 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.3.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 built-in input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In extended mode: Operation is not affected. In single-chip mode: When the pins are in input state, the corresponding input pull-up MOS is turned on when a P3PCR bit is set to 1. 9.3.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. Note that MMC mode stands for MultiMediaCard mode, and the symbol "--" stands for Don't care in the tables. Extended Mode: Port 3 pins automatically function as the data bus. Single-Chip Mode: * P37/WUE15 The pin function is switched as shown below according to the P37DDR bit. When the WUEM15 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE15 input pin. To use this pin as the WUE15 input pin, clear the P37DDR bit to 0. P37DDR Pin function 0 P37 input pin WUE15 input pin 1 P37 output pin Rev. 3.00 Jan 25, 2006 page 217 of 872 REJ09B0286-0300 Section 9 I/O Ports * P36/WUE14 The pin function is switched as shown below according to the P36DDR bit. When the WUEM14 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin. To use this pin as the WUE14 input pin, clear the P36DDR bit to 0. P36DDR Pin function 0 P36 input pin WUE14 input pin 1 P36 output pin * P35/WUE13 The pin function is switched as shown below according to the P35DDR bit. When the WUEM13 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE13 input pin. To use this pin as the WUE13 input pin, clear the P35DDR bit to 0. P35DDR Pin function 0 P35 input pin WUE13 input pin 1 P35 output pin Rev. 3.00 Jan 25, 2006 page 218 of 872 REJ09B0286-0300 Section 9 I/O Ports * P34/WUE12/MCCMDDIR/MCCSB The pin function is switched as shown below according to the combination of the MCIF operating mode and the P34DDR bit. When the WUEM12 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE12 input pin. To use this pin as the WUE12 input pin, clear the P34DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or MMCS in PTCNT0 is 1 MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 (MMC mode (SPI in MODER is 0) DIRME in IOMCR is 0) or (SPI mode (SPI in MODER is 1) SPCNUM in IOMCR is 0) P34DDR Pin function 0 P34 input pin 1 P34 output pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 MMC mode (SPI in MODER is 0) DIRME in IOMCR is 1 SPI mode (SPI in MODER is 1) SPCNUM in IOMCR is 1 -- MCCMDDIR output pin -- MCCSB output pin WUE12 input pin Rev. 3.00 Jan 25, 2006 page 219 of 872 REJ09B0286-0300 Section 9 I/O Ports * P33/WUE11/MCDATDIR/MCCSA The pin function is switched as shown below according to the combination of the MCIF operating mode and the P33DDR bit. When the WUEM11 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin. To use this pin as the WUE11 input pin, clear the P33DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or MMCS in PTCNT0 is 1 MCIF Enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 MMC mode (SPI in MODER is 0) DIRME in IOMCR is 0 P33DDR Pin function 0 P33 input pin 1 P33 output pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 MMC mode (SPI in MODER is 0) DIRME in IOMCR is 1 -- SPI mode (SPI in MODER is 1) -- MCDATDIR output MCCSA output pin pin WUE11 input pin * P32/WUE10/MCDAT/MCRxD The pin function is switched as shown below according to the combination of the MCIF operating mode and the P32DDR bit. When the WUEM10 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE10 input pin. To use this pin as the WUE10 input pin, clear the P32DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or MMCS in PTCNT0 is 1 0 P32 input pin 1 P32 output pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 MMC mode (SPI in MODER is 0) -- MCDAT input/output pin SPI mode (SPI in MODER is 1) -- MCRxD input pin P32DDR Pin function WUE10 input pin Rev. 3.00 Jan 25, 2006 page 220 of 872 REJ09B0286-0300 Section 9 I/O Ports * P31/WUE9/MCCMD/MCTxD The pin function is switched as shown below according to the combination of the MCIF operating mode and the P31DDR bit. When the WUEM9 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin. To use this pin as the WUE9 input pin, clear the P31DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or MMCS in PTCNT0 is 1 MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 MMC mode (SPI in MODER is 0) -- MCCMD input/output pin SPI mode (SPI in MODER is 1) -- MCTxD output pin P31DDR Pin function 0 P31 input pin 1 P31 output pin WUE9 input pin * P30/WUE8/MCCLK The pin function is switched as shown below according to the combination of the MCIF operating mode and the P30DDR bit. When the WUEM8 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE8 input pin. To use this pin as the WUE8 input pin, clear the P30DDR bit to 0. MCIF operating mode P30DDR Pin function MCIF disable (MMCPE in IOMCR is 0) or MMCS in PTCNT0 is 1 0 P30 input pin 1 P30 output pin WUE8 input pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 0 -- MCCLK output pin Rev. 3.00 Jan 25, 2006 page 221 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.3.5 Port 3 Input Pull-Up MOS Port 3 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in single-chip mode. Table 9.4 summarizes the input pull-up MOS states. Table 9.4 Mode Extended mode (EXPE = 1) Single-chip mode (EXPE = 0) Port 3 Input Pull-Up MOS States Reset Off Off Hardware Standby Mode Off Off Software Standby Mode Off On/Off In Other Operations Off On/Off Legend: Off: Always off. On/Off: On when input state and P3PCR = 1; otherwise off. 9.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as interrupt input pins, TMR_0, TMR_1, TMR_X, and TMR_Y input/output pins, timer connection input/output pins, and MCIF input/output pins. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) Rev. 3.00 Jan 25, 2006 page 222 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.4.1 Port 4 Data Direction Register (P4DDR) The individual bits of P4DDR specify input or output for the pins of port 4. Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 4 pins are specified for use as the general I/O port, the corresponding port 4 pins are output ports when the P4DDR bits are set to 1, and input ports when cleared to 0. 9.4.2 Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P4DR stores output data for the port 4 pins that are used as the general output port. If a port 4 read is performed while the P4DDR bits are set to 1, the P4DR values are read. If a port 4 read is performed while the P4DDR bits are cleared to 0, the pin states are read. Rev. 3.00 Jan 25, 2006 page 223 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.4.3 Pin Functions The relationship between register setting values and pin functions are as follows. Note that MMC mode stands for MultiMediaCard mode, and the symbol "--" stands for Don't care in the tables. * P47/IRQ7/TMOY The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_Y and the P47DDR bit. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin. To use this pin as the IRQ7 input pin, clear the P47DDR bit to 0. OS3 to OS0 P47DDR Pin function 0 P47 input pin All bits are set as 0 1 P47 output pin IRQ7 input pin One bit is set as 1 -- TMOY output pin * P46/IRQ6/TMOX The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X and the P46DDR bit. When the ISS6 bit in ISSR is cleared to 0 and the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ6 input pin. To use this pin as the IRQ6 input pin, clear the P46DDR bit to 0. OS3 to OS0 P46DDR Pin function 0 P46 input pin All bits are set as 0 1 P46 output pin IRQ6 input pin One bit is set as 1 -- TMOX output pin * P45/IRQ5/TMIY The pin function is switched as shown below according to the P45DDR bit. When the TMIYS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_Y, this pin is used as the TMCIY input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_Y are set to 1, this pin is used as the TMRIY input pin. When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin. To use this pin as the IRQ5 input pin, clear the P45DDR bit to 0. Rev. 3.00 Jan 25, 2006 page 224 of 872 REJ09B0286-0300 Section 9 I/O Ports P45DDR Pin function 0 P45 input pin 1 P45 output pin TMIY (TMCIY/TMRIY) input pin/IRQ5 input pin * P44/IRQ4/TMIX/ExMCCMDDIR/ExMCCSB The pin function is switched as shown below according to the combination of the MCIF operating mode and the P44DDR bit. When the TMIXS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_X, this pin is used as the TMCIX input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_X are set to 1, this pin is used as the TMRIX input pin. When the ISS4 bit in ISSR is cleared to 0 and the IRQ4E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ4 input pin. To use this pin as the IRQ4 input pin, clear the P44DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 (MMC mode (SPI in MODER is 0) DIRME in IOMCR is 0) or (SPI mode (SPI in MODER is 1) SPCNUM in IOMCR is 0) P44DDR Pin function 0 P44 input pin 1 P44 output pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 or Extended mode (EXPE = 1) MMC mode (SPI in MODER is 0) DIRME in IOMCR is 1 SPI mode (SPI in MODER is 1) SPCNUM in IOMCR is 1 -- ExMCCMDDIR output pin -- ExMCCSB output pin TMIX (TMCIX/TMRIX) input pin/IRQ4 input pin * P43/IRQ3/TMO1/ExMCDATDIR/ExMCCSA/HSYNCO The pin function is switched as shown below according to the combination of the MCIF operating mode, the HOE bit in TCONRO of the timer connection, the OS3 to OS0 bits in TCSR of TMR_1, and the P43DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ3 input pin. To use this pin as the IRQ3 input pin, clear the P43DDR bit to 0. Rev. 3.00 Jan 25, 2006 page 225 of 872 REJ09B0286-0300 Section 9 I/O Ports MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 MMC mode (SPI in MODER is 0) DIRME in IOMCR is 0) HOE OS3 to OS0 0 All bits are set as 0 0 P43 input pin 1 P43 output pin One bit is set as 1 -- TMO1 output pin 1 -- MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 or Extended mode (EXPE = 1) MMC mode (SPI in MODER is 0) DIRME in IOMCR is 1 -- -- SPI mode (SPI in MODER is 1) P43DDR Pin function -- HSYNC O output pin ExMCDATDIR output pin -- ExMCCSA output pin IRQ3 input pin * P42/IRQ2/TMO0/ExMCDAT/ExMCRxD The pin function is switched as shown below according to the combination of the MCIF operating mode, the OS3 to OS0 bits in TCSR of TMR_1, and the P42DDR bit. When the ISS2 bit in ISSR is cleared to 0 and the IRQ2E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ2 input pin. To use this pin as the IRQ2 input pin, clear the P42DDR bit to 0. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 or Extended mode (EXPE = 1) MMC mode (SPI in MODER is 0) OS3 to OS0 P42DDR Pin function All bits are set as 0 One bit is set as 1 0 P42 input pin 1 P42 output pin -- TMO0 output pin ExMCDAT input/output pin -- -- ExMCRxD input pin SPI mode (SPI in MODER is 1) IRQ2 input pin Rev. 3.00 Jan 25, 2006 page 226 of 872 REJ09B0286-0300 Section 9 I/O Ports * P41/IRQ1/TMI1/ExMCCMD/ExMCTxD/HSYNCI The pin function is switched as shown below according to the combination of the MCIF operating mode and the P41DDR bit. When the TMI1S bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_1, this pin is used as the TMCI1 input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. When the ISS1 bit in ISSR is cleared to 0 and the IRQ1E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ1 input pin. To use this pin as the IRQ1 input pin, clear the P41DDR bit to 0. When the SIMOD1 bit (IHI signal) in TCONRI of the timer connection module is set to 1, this pin is used as the HSYNCI input pin. MCIF operating mode MCIF disable (MMCPE in IOMCR is 0) or (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 or Extended mode (EXPE = 1) MMC mode (SPI in MODER is 0) P41DDR Pin function 0 P41 input pin 1 P41 output pin ExMCCMD input/output pin -- ExMCTxD output pin SPI mode (SPI in MODER is 1) TMI1 (TMCI1/TMRI1) input pin/IRQ1 input pin/HSYNCI input pin * P40/IRQ0/TMI0/ExMCCLK The pin function is switched as shown below according to the combination of the MCIF operating mode and the P40DDR bit. When the TMIOS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_0, this pin is used as the TMCI0 input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_0 are set to 1, this pin is used as the TMRI0 input pin. When the ISS0 bit in ISSR is cleared to 0 and the IRQ0E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ0 input pin. To use this pin as the IRQ0 input pin, clear the P40DDR bit to 0. Rev. 3.00 Jan 25, 2006 page 227 of 872 REJ09B0286-0300 Section 9 I/O Ports MCIF operating mode P40DDR Pin function MCIF disable (MMCPE in IOMCR is 0) or (Single-chip mode (EXPE = 0) MMCS in PTCNT0 is 0) 0 P40 input pin 1 P40 output pin MCIF enable (MMCPE in IOMCR is 1) MMCS in PTCNT0 is 1 or Extended mode (EXPE = 1) -- ExMCCLK output pin TMI0 (TMCI0/TMRI0) input pin/IRQ0 input pin 9.5 Port 5 Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin, SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) 9.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. Bit 7 6 5 4 3 2 1 0 Bit Name P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 5 pins are specified for use as the general I/O port, the corresponding port 5 pins are output ports when the P5DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Jan 25, 2006 page 228 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.5.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P57DR P56DR P55DR P54DR P53DR P52DR P51DR P50DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P5DR stores output data for the port 5 pins that are used as the general output port. If a port 5 read is performed while the P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while the P5DDR bits are cleared to 0, the pin states are read. 9.5.3 Pin Functions The relationship between register setting values and pin functions are as follows. In the tables, the symbol "--" stands for Don't care. * P57/IRQ15/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR of PWMX and the P57DDR bit. When the IRQ15E bit in IER16 of the interrupt controller is set to 1 or the ISS15 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ15 input pin. To use this pin as the IRQ15 input pin, clear the P57DDR bit to 0. OEB P57DDR Pin function 0 P57 input pin 0 1 P57 output pin IRQ15 input pin 1 -- PWX1 output pin Rev. 3.00 Jan 25, 2006 page 229 of 872 REJ09B0286-0300 Section 9 I/O Ports * P56/IRQ14/PWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of PWMX and the P56DDR bit. When the IRQ14E bit in IER16 of the interrupt controller is set to 1 or the ISS14 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ14 input pin. To use this pin as the IRQ14 input pin, clear the P56DDR bit to 0. OEA P56DDR Pin function 0 P56 input pin 0 1 P56 output pin IRQ14 input pin 1 -- PWX0 output pin * P55/IRQ13/RxD2 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_2 and the P55DDR bit. When the IRQ13E bit in IER16 of the interrupt controller is set to 1 or the ISS13 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ13 input pin. To use this pin as the IRQ13 input pin, clear the P55DDR bit to 0. RE P55DDR Pin function 0 P55 input pin 0 1 P55 output pin IRQ13 input pin 1 -- RxD2 input pin * P54/IRQ12/TxD2 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P54DDR bit. When the IRQ12E bit in IER16 of the interrupt controller is set to 1 or the ISS12 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ12 input pin. To use this pin as the IRQ12 input pin, clear the P54DDR bit to 0. TE P54DDR Pin function 0 P54 input pin 0 1 P54 output pin IRQ12 input pin 1 -- TxD2 output pin Rev. 3.00 Jan 25, 2006 page 230 of 872 REJ09B0286-0300 Section 9 I/O Ports * P53/IRQ11/RxD1/IrRxD The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P53DDR bit. When the IRQ11E bit in IER16 of the interrupt controller is set to 1 or the ISS11 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ11 input pin. To use this pin as the IRQ11 input pin, clear the P53DDR bit to 0. RE P53DDR Pin function 0 P53 input pin 0 1 P53 output pin IRQ11 input pin 1 -- RxD1/IrRxD input pin * P52/IRQ10/TxD1/IrTxD The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P52DDR bit. When the IRQ10E bit in IER16 of the interrupt controller is set to 1 or the ISS10 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ10 input pin. To use this pin as the IRQ10 input pin, clear the P52DDR bit to 0. TE P52DDR Pin function 0 P52 input pin 0 1 P52 output pin IRQ10 input pin 1 -- TxD1/IrTxD output pin * P51/IRQ9/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit. When the IRQ9E bit in IER16 of the interrupt controller is set to 1 or the ISS9 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ9 input pin. To use this pin as the IRQ9 input pin, clear the P51DDR bit to 0. RE P51DDR Pin function 0 P51 input pin 0 1 P51 output pin IRQ9 input pin 1 -- RxD0 input pin Rev. 3.00 Jan 25, 2006 page 231 of 872 REJ09B0286-0300 Section 9 I/O Ports * P50/IRQ8/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit. When the IRQ8E bit in IER16 of the interrupt controller is set to 1 or the ISS8 bit in ISSR16 is cleared to 0, this pin can be used as the IRQ8 input pin. To use this pin as the IRQ8 input pin, clear the P50DDR bit to 0. TE P50DDR Pin function 0 P50 input pin 0 1 P50 output pin IRQ8 input pin 1 -- TxD0 output pin 9.6 Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT input/output pin, enhanced A/D conversion input pin, keyboard input pin, timer connection input/output pins, and external USB driver/receiver input/output pin. Port 6 functions change according to the operating mode. The port can be used as the extended data bus (lower eight bits). Port 6 has the following registers. * Port 6 data direction register (P6DDR) * Port 6 data register (P6DR) * Port 6 pull-up MOS control register (KMPCR6) * System control register 2 (SYSCR2) Rev. 3.00 Jan 25, 2006 page 232 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Extended mode (16-bit data bus): The port functions as the data bus regardless of the values in these bits. Single-chip mode/extended mode (8-bit data bus): If port 6 pins are specified for use as the general I/O port, the corresponding port 6 pins are output ports when the P6DDR bits are set to 1, and input ports when cleared to 0. 9.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Extended mode (16-bit data bus): If a port 6 read is performed while the P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while the P6DDR bits are cleared to 0, 1 is read. Single-chip mode/extended mode (8-bit data bus): P6DR stores output data for the port 6 pins that are used as the general output port. If a port 6 read is performed while the P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while the P6DDR bits are cleared to 0, the pin states are read. Rev. 3.00 Jan 25, 2006 page 233 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.6.3 Port 6 Pull-Up MOS Control Register (KMPCR6) KMPCR6 controls the port 6 built-in input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Extended mode (16-bit data bus): Operation is not affected. Single-chip mode/extended mode (8-bit data bus): When the pins are in input state, the corresponding input pull-up MOS is turned on when a KMPCR6 bit is set to 1. Rev. 3.00 Jan 25, 2006 page 234 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.6.4 System Control Register 2 (SYSCR2) SYSCR2 selects the port 6 input level and current specification for the input pull-up MOSs. Bit 7 6 Bit Name KWUL1 KWUL0 Initial Value 0 0 R/W R/W R/W Description Key Wakeup Level 1, 0: Select the port 6 input level. 00: Standard input level is selected 01: Input level 1 is selected 10: Input level 2 is selected 11: Input level 3 is selected 5 P6PUE 0 R/W Port 6 Input Pull-Up Extra Selects the current specification for the input pullup MOS connected by means of KMPCR settings. 0: Standard current specification is selected 1: Current-limit specification is selected 4, 3 2 1 0 -- CKCHGE -- PLCKS All 0 0 0 0 R/(W) R/W R/(W) R/W Reserved The initial value should not be changed. For details, refer to section 27.1.3, System Control Register 2 (SYSCR2). Reserved The initial value should not be changed. For details, refer to section 27.1.3, System Control Register 2 (SYSCR2). Rev. 3.00 Jan 25, 2006 page 235 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.6.5 Pin Functions The relationship between the operating modes, register setting values, and pin functions are as follows. In the tables, the symbol "--" stands for Don't care. In extended mode, port 6 pins also function as the bidirectional data bus, CompactFlash bidirectional data bus, FRT input/output pin, enhanced A/D conversion input pin, keyboard input pin, timer connection input/output pins, or I/O port. The extended data bus width can be specified by bits ABW and ABW256 in WSCR of BSC and bit ABWCP in BCR2. When the 16-bit bus interface is specified, port 6 pins function as the bidirectional data bus (D7 to D0/CPD7 to CPD0). When the 8-bit bus interface is specified, port 6 pins function as the FRT input/output pin, enhanced A/D conversion input pin, keyboard input pin, timer connection input/output pins, or I/O port. In single-chip mode, port 6 pins function as the FRT input/output pin, enhanced A/D conversion input pin, keyboard input pin, timer connection input/output pins, or external USB driver/receiver input/output pin, or I/O port Extended Mode with 16-Bit Data Bus Specified: Port 6 pins function as the lower 8 bits of the data bus. Note: When the 16-bit data bus interface is specified in extended mode, USB should not be enabled. If USB is enabled, port 6 cannot operate as a data bus. Extended Mode with 8-Bit Data Bus Specified: * P67/CIN7/KIN7 The function of port 6 pins is switched as shown below according to the P67DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'111, this pin can be used as the CIN7 input pin. When the KMIM7 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. To use this pin as the KIN7 input pin, clear the P67DDR bit to 0. P67DDR Pin function 0 P67 input pin CIN7 input pin/KIN7 input pin 1 P67 output pin Rev. 3.00 Jan 25, 2006 page 236 of 872 REJ09B0286-0300 Section 9 I/O Ports * P66/FTOB/CIN6/KIN6/CBLANK The function of port 6 pins is switched as shown below according to the combination of the CBOE bit in TCONRO of the timer connection, the OEB bit in TOCR of FRT, and the P66DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'110, this pin can be used as the CIN6 input pin. When the KMIM6 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN6 input pin. To use this pin as the KIN6 input pin, clear the P66DDR bit to 0. CBOE OEB P66DDR Pin function 0 P66 input pin 0 1 P66 output pin 0 1 -- FTOB output pin 1 -- -- CBLANK output pin CIN6 input pin/KIN6 input pin * P65/FTID/CIN5/KIN5/CSYNCI The function of port 6 pins is switched as shown below according to the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'101, this pin can be used as the CIN5 input pin. When the KMIM5 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN5 input pin. To use this pin as the KIN5 input pin, clear the P65DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer connection are set to B'01, this pin can be used as the CSYNCI input pin. P65DDR Pin function 0 P65 input pin 1 P65 output pin FTID input pin/CIN5 input pin/KIN5 input pin/CSYNCI input pin * P64/FTIC/CIN4/KIN4/CLAMPO The function of port 6 pins is switched as shown below according to the combination of the CLOE bit in TCONRO of the timer connection and the P64DDR bit. When the ICICE bit in TIER of FRT is set to 1, this pin can be used as the FTIC input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'100, this pin can be used as the CIN4 input pin. When the KMIM4 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN4 input pin. To use this pin as the KIN4 input pin, clear the P64DDR bit to 0. Rev. 3.00 Jan 25, 2006 page 237 of 872 REJ09B0286-0300 Section 9 I/O Ports CLOE P64DDR Pin function 0 0 P64 input pin 0 1 P64 output pin FTIC input pin/CIN4 input pin/KIN4 input pin 1 -- CLAMPO output pin * P63/FTIB/CIN3/KIN3/VFBACKI The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'011, this pin can be used as the CIN3 input pin. When the KMIM3 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN3 input pin. To use this pin as the KIN3 input pin, clear the P63DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection are cleared to B'00, this pin can be used as the VFBACKI input pin. P63DDR Pin function 0 P63 input pin 1 P63 output pin FTIB input pin/CIN3 input pin/KIN3 input pin/VFBACKI input pin * P62/FTIA/CIN2/KIN2/VSYNCI The function of port 6 pins is switched as shown below according to the P62DDR bit. When the ICIAE bit in TIER of FRT is set to 1, this pin can be used as the FTIA input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'010, this pin can be used as the CIN2 input pin. When the KMIM2 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN2 input pin. To use this pin as the KIN2 input pin, clear the P62DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection are set to B'11, this pin can be used as the VSYNCI input pin. P62DDR Pin function 0 P62 input pin 1 P62 output pin FTIA input pin/CIN2 input pin/KIN2 input pin/VSYNCI input pin Rev. 3.00 Jan 25, 2006 page 238 of 872 REJ09B0286-0300 Section 9 I/O Ports * P61/FTOA/CIN1/KIN1/VSYNCO The function of port 6 pins is switched as shown below according to the combination of the VOE bit in TCONRO of the timer connection, the OEA bit in TOCR of FRT, and the P61DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'001, this pin can be used as the CIN1 input pin. When the KMIM1 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN1 input pin. To use this pin as the KIN1 input pin, clear the P61DDR bit to 0. VOE OEA P61DDR Pin function 0 P61 input pin 0 1 P61 output pin 0 1 -- FTOA output pin 1 -- -- VSYNCO output pin CIN1 input pin/KIN1 input pin * P60/FTCI/CIN0/KIN0/HFBACKI The function of port 6 pins is switched as shown below according to the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the FTCI input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are cleared to B'000, this pin can be used as the CIN0 input pin. When the KMIM0 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN0 input pin. To use this pin as the KIN0 input pin, clear the P60DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer connection are cleared to B'00, this pin can be used as the HFBACKI input pin. P60DDR Pin function 0 P60 input pin 1 P60 output pin FTCI input pin/CIN0 input pin/KIN0 input pin/HFBACKI input pin Rev. 3.00 Jan 25, 2006 page 239 of 872 REJ09B0286-0300 Section 9 I/O Ports Single-Chip Mode: * P67/CIN7/KIN7/DPLS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P67DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'111, this pin can be used as the CIN7 input pin. When the KMIM7 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. To use this pin as the KIN7 input pin, clear the P67DDR bit to 0. FADSEL P67DDR Pin function 0 P67 input pin 0 1 P67 output pin CIN7 input pin/KIN7 input pin 1 -- DPLS input pin * P66/FTOB/CIN6/KIN6/CBLANK/DMNS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB, the CBOE bit in TCONRO of the timer connection, the OEB bit in TOCR of FRT, and the P66DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'110, this pin can be used as the CIN6 input pin. When the KMIM6 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN6 input pin. To use this pin as the KIN6 input pin, clear the P66DDR bit to 0. FADSEL CBOE OEB P66DDR Pin function 0 P66 input pin 0 1 P66 output pin 0 1 -- FTOB output pin 0 1 -- -- CBLANK output pin 1 -- -- -- DMNS input pin CIN6 input pin/KIN6 input pin Rev. 3.00 Jan 25, 2006 page 240 of 872 REJ09B0286-0300 Section 9 I/O Ports * P65/FTID/CIN5/KIN5/CSYNCI/XVERDATA The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'101, this pin can be used as the CIN5 input pin. When the KMIM5 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN5 input pin. To use this pin as the KIN5 input pin, clear the P65DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer connection are set to B'01, this pin can be used as the CSYNCI input pin. FADSEL P65DDR Pin function 0 P65 input pin 0 1 P65 output pin 1 -- XVERDATA input pin FTID input pin/CIN5 input pin/KIN5 input pin/CSYNCI input pin * P64/FTIC/CIN4/KIN4/CLAMPO/TXDPLS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB, the CLOE bit in TCONRO of the timer connection, and the P64DDR bit. When the ICICE bit in TIER of FRT is set to 1, this pin can be used as the FTIC input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'100, this pin can be used as the CIN4 input pin. When the KMIM4 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN4 input pin. To use this pin as the KIN4 input pin, clear the P64DDR bit to 0. FADSEL CLOE P64DDR Pin function 0 P64 input pin 0 1 P64 output pin 0 1 -- CLAMPO output pin 1 -- -- TXDPLS output pin FTIC input pin/CIN4 input pin/KIN4 input pin Rev. 3.00 Jan 25, 2006 page 241 of 872 REJ09B0286-0300 Section 9 I/O Ports * P63/FTIB/CIN3/KIN3/VFBACKI/TXDMNS The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'011, this pin can be used as the CIN3 input pin. When the KMIM3 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN3 input pin. To use this pin as the KIN3 input pin, clear the P63DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection are cleared to B'00, this pin can be used as the VFBACKI input pin. FADSEL P63DDR Pin function 0 P63 input pin 0 1 P63 output pin 1 -- TXDMNS output pin FTIB input pin/CIN3 input pin/KIN3 input pin/VFBACKI input pin * P62/FTIA/CIN2/KIN2/VSYNCI/TXENL The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P62DDR bit. When the ICIAE bit in TIER of FRT is set to 1, this pin can be used as the FTIA input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'010, this pin can be used as the CIN2 input pin. When the KMIM2 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN2 input pin. To use this pin as the KIN2 input pin, clear the P62DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IVI signal) in TCONRI of the timer connection are set to B'11, this pin can be used as the VSYNCI input pin. FADSEL P62DDR Pin function 0 P62 input pin 0 1 P62 output pin 1 -- TXENL output pin FTIA input pin/CIN2 input pin/KIN2 input pin/VSYNCI input pin Rev. 3.00 Jan 25, 2006 page 242 of 872 REJ09B0286-0300 Section 9 I/O Ports * P61/FTOA/CIN1/KIN1/VSYNCO/SUSPEND The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB, the VOE bit in TCONRO of the timer connection, the OEA bit in TOCR of FRT, and the P61DDR bit. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are set to B'001, this pin can be used as the CIN1 input pin. When the KMIM1 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN1 input pin. To use this pin as the KIN1 input pin, clear the P61DDR bit to 0. FADSEL VOE OEA P61DDR Pin function 0 P61 input pin 0 1 P61 output pin 0 1 -- FTOA output pin 0 1 -- -- VSYNCO output pin 1 -- -- -- SUSPEND output pin CIN1 input pin/KIN1 input pin * P60/FTCI/CIN0/KIN0/HFBACKI/SPEED The function of port 6 pins is switched as shown below according to the combination of the FADSEL bit in USBCR0 of USB and the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the FTCI input pin. When the KBADE bit in KBCOMP of the A/D converter is set to 1 while the KBCH2 to KBCH0 bits are cleared to B'000, this pin can be used as the CIN0 input pin. When the KMIM0 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN0 input pin. To use this pin as the KIN0 input pin, clear the P60DDR bit to 0. When the SIMOD1 and SIMOD0 bits (IHI signal) in TCONRI of the timer connection are cleared to B'00, this pin can be used as the HFBACKI input pin. FADSEL P60DDR Pin function 0 P60 input pin 0 1 P60 output pin 1 -- SPEED output pin FTCI input pin/CIN0 input pin/KIN0 input pin/HFBACKI input pin Rev. 3.00 Jan 25, 2006 page 243 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.6.6 Port 6 Input Pull-Up MOS Port 6 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 9.5 summarizes the input pull-up MOS states. Table 9.5 Reset Off Port 6 Input Pull-Up MOS States Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Always off. On/Off: On when input state and KMPCR = 1; otherwise off. 9.7 Port 7 Port 7 is a 6-bit input port. Port 7 pins also function as the A/D converter analog input pins, D/A converter analog output pins, and interrupt input pins. When the ISS bit in ISSR is set to 1, these pins can be used as the interrupt input pins. Port 7 has the following register. * Port 7 input data register (P7PIN) 9.7.1 Port 7 Input Data Register (P7PIN) P7PIN indicates the pin states. Bit 7 6 5 4 3 2 1, 0 Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN -- Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* All 1 R/W R R R R R R R Reserved These bits are always read as 1 and cannot be modified. Note: * The initial values of bits 7 to 2 are determined according to the pin states of P77 to P72. Description When a P7PIN read is performed, the pin states are always read. Rev. 3.00 Jan 25, 2006 page 244 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.8 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as the A/D converter external trigger input pin, SCI_0, SCI_1, and SCI_2 clock input/output pins, IIC_0 and IIC_1 input/output pins, ExTMR_0, ExTMR_1, ExTMR_X, and ExTMR_Y input pins, USB external clock input pin, and interrupt input pins. Port 8 is an NMOS push-pull output. Port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) 9.8.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. Bit 7 6 5 4 3 2 1 0 Bit Name P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 8 pins are specified for use as the general I/O port, the corresponding port 8 pins are output ports when the P8DDR bits are set to 1, and input ports when cleared to 0. Rev. 3.00 Jan 25, 2006 page 245 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P87DR P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P8DR stores output data for the port 8 pins that are used as the general output port. If a port 8 read is performed while the P8DDR bits are set to 1, the P8DR values are read. If a port 8 read is performed while the P8DDR bits are cleared to 0, the pin states are read. 9.8.3 Pin Functions The relationship between register setting values and pin functions are as follows. In the tables, the symbol "--" stands for Don't care. * P87/ExIRQ15/ADTRG/ExTMIY/USEXCL The pin function is switched as shown below according to the P87DDR bit. When the TRGS1 and TRGS0 bits in ADCR of the A/D converter are both set to 1, this pin can be used as the ADTRG input pin. When the CKSEL2 to CKSEL0 bits in UPLLCR of the USB are all set to 1, this pin can be used as the USEXCL input pin. When the ISS15 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin. When the TMIYS bit in PTCNT0 is set to 1, this pin can be used as the TMIY (TMCIX/TMRIY) input pin. To use this pin as the ExIRQ15 input pin, clear the P87DDR bit to 0. When this pin is used as the P87 output pin, the output format is NMOS push-pull output. P87DDR Pin function 0 P87 input pin 1 P87 output pin ExIRQ15 input pin/ADTRG input pin/ExTMIY input pin/USEXCL input pin Rev. 3.00 Jan 25, 2006 page 246 of 872 REJ09B0286-0300 Section 9 I/O Ports * P86/ExIRQ14/SCK2/ExTMIX The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_2, the CKE1 and CKE0 bits in SCR, and the P86DDR bit. When the ISS14 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ14 input pin. When the TMIXS bit in PTCNT0 is set to 1, this pin can be used as the TMIX (TMCIX/TMRIX) input pin. To use this pin as the ExIRQ14 input pin, clear the P86DDR bit to 0. When this pin is used as the P86 output pin, the output format is NMOS push-pull output. CKE1 C/A CKE0 P86DDR Pin function 0 P86 input pin 0 1 P86 output pin 0 1 -- SCK2 output pin 0 1 -- -- SCK2 output pin 1 -- -- -- SCK2 input pin ExIRQ14 input pin/ExTMIX input pin * P85/ExIRQ13/SCK1/ExTMI1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit. When the ISS13 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin. When the TMI1S bit in PTCNT0 is set to 1, this pin can be used as the TMI1 (TMI1/TMRI1) input pin. To use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0. When this pin is used as the P85 output pin, the output format is NMOS push-pull output. CKE1 C/A CKE0 P85DDR Pin function 0 P85 input pin 0 1 P85 output pin 0 1 -- SCK1 output pin 0 1 -- -- SCK1 output pin 1 -- -- -- SCK1 input pin ExIRQ13 input pin/ExTMI1 input pin Rev. 3.00 Jan 25, 2006 page 247 of 872 REJ09B0286-0300 Section 9 I/O Ports * P84/ExIRQ12/SCK0/ExTMI0 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_0, the CKE1 and CKE0 bits in SCR, and the P84DDR bit. When the ISS12 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin. When the TMI0S bit in PTCNT0 is set to 1, this pin can be used as the TMI0 (TMI0/TMRI0) input pin. To use this pin as the ExIRQ12 input pin, clear the P84DDR bit to 0. When this pin is used as the P84 output pin, the output format is NMOS push-pull output. CKE1 C/A CKE0 P84DDR Pin function 0 P84 input pin 0 1 P84 output pin 0 1 -- SCK0 output pin 0 1 -- -- SCK0 output pin 1 -- -- -- SCK0 input pin ExIRQ12 input pin/ExTMI0 input pin * P83/ExIRQ11/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P83DDR bit. When the ISS11 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin. To use this pin as the ExIRQ11 input pin, clear the P83DDR bit to 0. When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output, and direct bus drive is possible. ICE P83DDR Pin function 0 P83 input pin 0 1 P83 output pin ExIRQ11 input pin 1 -- SDA1 input/output pin * P82/ExIRQ10/SCL1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P82DDR bit. When the ISS10 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ10 input pin. To use this pin as the ExIRQ10 input pin, clear the P82DDR bit to 0. When this pin is used as the P82 output pin, the output format is NMOS push-pull output. The output format for SCL1 is NMOS open-drain output, and direct bus drive is possible. Rev. 3.00 Jan 25, 2006 page 248 of 872 REJ09B0286-0300 Section 9 I/O Ports ICE P82DDR Pin function 0 P82 input pin 0 1 P82 output pin ExIRQ10 input pin 1 -- SCL1 input/output pin * P81/ExIRQ9/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit. When the ISS9 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ9 input pin. To use this pin as the ExIRQ9 input pin, clear the P81DDR bit to 0. When this pin is used as the P81 output pin, the output format is NMOS push-pull output. The output format for SDA0 is NMOS open-drain output, and direct bus drive is possible. ICE P81DDR Pin function 0 P81 input pin 0 1 P81 output pin ExIRQ9 input pin 1 -- SDA0 input/output pin * P80/ExIRQ8/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P80DDR bit. When the ISS8 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ8 input pin. To use this pin as the ExIRQ8 input pin, clear the P80DDR bit to 0. When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The output format for SCL0 is NMOS open-drain output, and direct bus drive is possible. ICE P80DDR Pin function 0 P80 input pin 0 1 P80 output pin ExIRQ8 input pin 1 -- SCL0 input/output pin Rev. 3.00 Jan 25, 2006 page 249 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.9 Port 9 Port 9 is an 8-bit I/O port. However note that pin P96 cannot be used as a general output port. Port 9 pins also function as the bus control I/O pins, CompactFlash control I/O pins, the system clock output pin, and the external subclock input pin. Pin functions are switched depending on the operating mode. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR) 9.9.1 Port 9 Data Direction Register (P9DDR) The individual bits of P9DDR specify input or output for the pins of port 9. Bit 7 Bit Name P97DDR Initial Value 0 R/W W Description If port 9 pins are specified for use as the general I/O port, the corresponding port 9 pins are output ports when the P9DDR bits are set to 1, and input ports when cleared to 0. When this bit is set to 1, the corresponding port 9 pin is the system clock output pin (), and as a general input port when cleared to 0. If port 9 pins are specified for use as the general I/O port, the corresponding port 9 pins are output ports when the P9DDR bits are set to 1, and input ports when cleared to 0. 6 P96DDR 0 W 5 4 3 2 1 0 P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR 0 0 0 0 0 0 W W W W W W Rev. 3.00 Jan 25, 2006 page 250 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.9.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description P9DR stores output data for the port 9 pins that are used as the general output port except for bit 6. If a port 9 read is performed while the P9DDR bits are set to 1, the P9DR values are read. If a port 9 read is performed while the P9DDR bits are cleared to 0, the pin states are read. The initial value of bit 6 is determined according to the P96 pin state. 9.9.3 Pin Functions The relationship between the operating mode, register setting values, and pin functions are as follows. In the tables, the symbol "--" stands for Don't care. * P97/WAIT/CPWAIT/CS256 The pin function is switched as shown below according to the combination of the operating mode, the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and the P97DDR bit. Operating Mode WMS1, WMS21 CS256E P97DDR Pin function 0 Extended Mode All bits are set as 0 0 1 1 -- One bit is set as 1 -- -- WAIT (WMS1 = 1) and CPWAIT (WMS21 = 1) input pins 0 P97 input pin Single-Chip Mode -- -- 1 P97 output pin P97 input P97 output CS256 pin pin output pin Rev. 3.00 Jan 25, 2006 page 251 of 872 REJ09B0286-0300 Section 9 I/O Ports * P96//EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR EXCLE Pin function 0 P96 input pin 0 1 EXCL input pin 1 0 output pin * P95/AS/IOS The pin function is switched as shown below according to the combination of the operating mode, the IOSE bit in SYSCR, and the P95DDR bit. Operating Mode P95DDR IOSE Pin function 0 AS output pin Extended Mode -- 1 IOS output pin P95 input pin 0 -- P95 output pin Single-Chip Mode 1 * P94/HWR/CPWE The pin function is switched as shown below according to the combination of the operating mode and the P94DDR bit. Operating Mode P94DDR Pin function Extended Mode -- HWR/CPWR output pin 0 P94 input pin Single-Chip Mode 1 P94 output pin * P93/RD/CPOE The pin function is switched as shown below according to the combination of the operating mode and the P93DDR bit. Operating Mode P93DDR Pin function Extended Mode -- RD/CPOE output pin 0 P93 input pin Single-Chip Mode 1 P93 output pin Rev. 3.00 Jan 25, 2006 page 252 of 872 REJ09B0286-0300 Section 9 I/O Ports * P92/CPCS1 The pin function is switched as shown below according to the combination of the operating mode, the CPCSE bit in BCR2 of BSC, and the P92DDR bit. Operating Mode CPCSE P92DDR Pin function 0 P92 input pin Extended Mode 0 1 1 -- 0 P92 input pin P92 output pin CPCS1 output pin Single-Chip Mode -- 1 P92 output pin * P91/CPCS2 The pin function is switched as shown below according to the combination of the operating mode, the CPCSE bit in BCR2 of BSC, the CFE bit in BCR, and the P91DDR bit. Operating Mode CPCSE and CFE P91DDR Pin function 0 P91 input pin Extended Mode Either bit is 0 1 Both bits are 1 -- 0 P91 input pin Single-Chip Mode -- 1 P91 output pin P91 output pin CPCS2 output pin * P90/LWR The pin function is switched as shown below according to the combination of the operating mode, the ABW and ABW256 bits in WSCR, the ABWCP bit in BCR2, and the P90DDR bit. Operating Mode ABW, ABW256, ABWCP P90DDR Pin function 0 P90 input pin Extended Mode All bits are 1 One bit is 0 Single-Chip Mode -- 1 P90 output pin -- LWR output pin 0 P90 input pin 1 P90 output pin Rev. 3.00 Jan 25, 2006 page 253 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.10 Port A Port A is a 2-bit I/O port. Port A pins also function as the address output, keyboard input, SCI_0 and SCI_2 external control pins. Pin functions are switched depending on the operating mode. Port A has the following registers. PADDR and PAPIN have the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) 9.10.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. Bit 7 to 2 1 0 Bit Name -- PA1DDR PA0DDR Initial Value All 0 0 0 R/W (W) W W Description Reserved These bits cannot be modified. In extended mode (mode 2): The corresponding port A pins are address output ports when the PADDR bits are set to 1, and input ports when cleared to 0. Pins function as the address output port depending on the setting of bits IOSE and CS256E in SYSCR. In single-chip mode or extended mode (mode 3): The corresponding port A pins are output ports when the PADDR bits are set to 1, and input ports when cleared to 0. 9.10.2 Port A Output Data Register (PAODR) PAODR stores output data for the port A pins. Bit 7 to 2 Bit Name -- Initial Value All 1 R/W R/(W) Description Reserved These bits are always read as 1. The initial value should not be changed. 1 0 PA1ODR PA0ODR 0 0 R/W R/W PAODR stores output data for the port A pins that are used as the general output port. Rev. 3.00 Jan 25, 2006 page 254 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the pin states. Bit 7 to 2 1 0 Note: Bit Name -- PA1PIN PA0PIN * Initial Value All 1 Undefined* Undefined* R/W R R R Description Reserved These bits are always read as 1. When a PAPIN read is performed, the pin states are always read. The initial values of bits 1 and 0 are determined according to the pin states of PA1 and PA0. 9.10.4 Pin Functions The relationship between the operating mode, register setting values, and pin functions are as follows. In the tables, the symbol "--" stands for Don't care. Extended Mode (Mode 2): * PA1/A17/KIN9/SSE2I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of BSC, and the PA1DDR bit. Address 13 in the following table is expressed by the following logical expression: Address 13 = 1:ADFULLE CS256E IOSE When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0. SSE C/A CKE1 PA1DDR Address 13 Pin function PA1 input pin 0 1 PA1 output pin KIN9 input pin Note: Even if SSE = 0, PA1DDR = 1 and CPCSE = 1, pin PA1 can be used as an output pin only when IOSE = 1. 0 -- -- 1 1 0 A17 output pin 1 1 1 -- -- SSE2I Rev. 3.00 Jan 25, 2006 page 255 of 872 REJ09B0286-0300 Section 9 I/O Ports * PA0/A16/KIN8/SSE0I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, the CS256E and IOSE bits in SYSCR, the ADFULLE bit in BCR2 of BSC, and the PA0DDR bit. Address 13 in the following table is expressed by the following logical expression: Address 13 = 1:ADFULLE CS256E IOSE When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0. SSE C/A CKE1 PA0DDR Address 13 Pin function PA0 input pin 0 1 PA0 output pin KIN8 input pin Note: Even if SSE = 0, PA0DDR = 1 and CPCSE = 1, pin PA0 can be used as an output pin only when IOSE = 1. 0 -- -- 1 1 0 A16 output pin 1 1 1 -- -- SSE0I Single-Chip Mode and Extended Mode (Mode 3): * PA1/KIN9/SSE2I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, and the PA1DDR bit. When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0. SSE C/A CKE1 PA1DDR Pin function 0 PA1 input pin 0 -- -- 1 PA1 output pin KIN9 input pin 1 1 1 -- SSE2I Rev. 3.00 Jan 25, 2006 page 256 of 872 REJ09B0286-0300 Section 9 I/O Ports * PA0/KIN8/SSE0I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, and the PA0DDR bit. When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0. SSE C/A CKE1 PA0DDR Pin function 0 PA0 input pin 0 -- -- 1 PA0 output pin KIN8 input pin 1 1 1 -- SSE0I 9.10.5 Input Pull-Up MOS Port A has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAODR bit to 1 turns on the input pull-up MOS. The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 9.6 summarizes the input pull-up MOS states. Table 9.6 Reset Off Port A Input Pull-Up MOS States Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Always off. On/Off: On when PADDR = 0 and PAODR = 1; otherwise off. Rev. 3.00 Jan 25, 2006 page 257 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.11 Change of Peripheral Function Pins I/O ports that also function as peripheral modules, such as the external interrupts, 8-bit timers, and MCIF, can be changed. I/O ports that also function as the external interrupt pins are changed according to the setting of ISSR16 and ISSR. I/O ports that also function as the 8-bit timer input pins and MCIF I/O pins are changed according to the setting of PTCNT0. The pin name of the peripheral function is indicated by adding `Ex' at the head of the original pin name. In each peripheral function description, the original pin name is used. 9.11.1 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select ports that also function as IRQ15 to IRQ0 input pins. ISSR16 Bit 15 14 13 12 11 10 9 8 Bit Name ISS15 ISS14 ISS13 ISS12 ISS11 ISS10 ISS9 ISS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P57/IRQ15 is selected 1: P87/ExIRQ15 is selected 0: P56/IRQ14 is selected 1: P86/ExIRQ14 is selected 0: P55/IRQ13 is selected 1: P85/ExIRQ13 is selected 0: P54/IRQ12 is selected 1: P84/ExIRQ12 is selected 0: P53/IRQ11 is selected 1: P83/ExIRQ11 is selected 0: P52/IRQ10 is selected 1: P82/ExIRQ10 is selected 0: P51/IRQ9 is selected 1: P81/ExIRQ9 is selected 0: P50/IRQ8 is selected 1: P80/ExIRQ8 is selected Rev. 3.00 Jan 25, 2006 page 258 of 872 REJ09B0286-0300 Section 9 I/O Ports ISSR Bit 7 6 5 4 3 2 1 0 Bit Name ISS7 ISS6 ISS5 ISS4 ISS3 ISS2 ISS1 ISS0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P47/IRQ7 is selected 1: P77/ExIRQ7 is selected 0: P46/IRQ6 is selected 1: P76/ExIRQ6 is selected 0: P45/IRQ5 is selected 1: P75/ExIRQ5 is selected 0: P44/IRQ4 is selected 1: P74/ExIRQ4 is selected 0: P43/IRQ3 is selected 1: P73/ExIRQ3 is selected 0: P42/IRQ2 is selected 1: P72/ExIRQ2 is selected P41/IRQ1 is always selected P40/IRQ0 is always selected Rev. 3.00 Jan 25, 2006 page 259 of 872 REJ09B0286-0300 Section 9 I/O Ports 9.11.2 Port Control Register 0 (PTCNT0) PTCNT0 selects ports that also function as 8-bit timer input pins and MCIF I/O pins. Bit 7 6 5 4 3 Bit Name TMI0S TMI1S TMIXS TMIYS MMCS Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description 0: P40/TMI0 is selected 1: P84/ExTMI0 is selected 0: P41/TMI1 is selected 1: P85/ExTMI1 is selected 0: P44/TMIX is selected 1: P86/ExTMIX is selected 0: P45/TMIY is selected 1: P87/ExTMIY is selected 0: P30/MCCLK, P31/MCCMD/MCTxD, P32/MCDAT/MCRxD, P33/MCDATDIR/MCCSA, P34/MCCMDDIR/MCCSB are selected 1: P40/ExMCCLK, P41/ExMCCMD/ExMCTxD, P42/ExMCDAT/ExMCRxD, P43/ExMCDATDIR/ExMCCSA, P44/ExMCCMDDIR/ExMCCSB are selected In extended mode, the MCIF pin function is multiplexed with port 4 regardless of the MMCS setting. 2 to 0 -- All 0 R/(W) Reserved The initial value should not be changed. Rev. 3.00 Jan 25, 2006 page 260 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) Section 10 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. 10.1 Features Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20- MHz operation) * Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) * Direct or inverted PWM output, and PWM output enable/disable control PWM0800A_000020020300 Rev. 3.00 Jan 25, 2006 page 261 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) Figure 10.1 shows a block diagram of the PWM timer. P10/PW0 P11/PW1 P12/PW2 P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 Port/PWM output control Comparator 0 Comparator 1 Comparator 2 Comparator 3 Comparator 4 Comparator 5 Comparator 6 Comparator 7 Comparator 8 Comparator 9 Comparator 10 Comparator 11 Comparator 12 Comparator 13 Comparator 14 Comparator 15 PWDR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 Module data bus Bus interface PWDR6 PWDR7 PWDR8 PWDR9 PWDR10 PWDR11 PWDR12 PWDR13 PWDR14 PWDR15 Internal data bus PWDPRB PWOERB P2DDR P2DR PWDPRA PWOERA P1DDR P1DR Clock counter Select clock PWSL PCSR Legend: PWSL PWDR PWDPRA PWDPRB PWOERA PWOERB PCSR P1DDR P2DDR P1DR P2DR : PWM register select : PWM data register : PWM data polarity register A : PWM data polarity register B : PWM output enable register A : PWM output enable register B : Peripheral clock select register : Port 1 data direction register : Port 2 data direction register : Port 1 data register : Port 2 data register /2 /4 /8 /16 Internal clock Figure 10.1 Block Diagram of PWM Timer Rev. 3.00 Jan 25, 2006 page 262 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) 10.2 Input/Output Pins Table 10.1 shows the PWM output pins. Table 10.1 Pin Configuration Name PWM output 15 to 0 Abbreviation PW15 to PW0 I/O Output Function PWM timer pulse output 15 to 0 10.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR). * PWM register select (PWSL) * PWM data registers 0 to 15 (PWDR0 to PWDR15) * PWM data polarity register A (PWDPRA) * PWM data polarity register B (PWDPRB) * PWM output enable register A (PWOERA) * PWM output enable register B (PWOERB) * Peripheral clock select register (PCSR) Rev. 3.00 Jan 25, 2006 page 263 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) 10.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit 7 6 Bit Name PWCKE PWCKS Initial Value 0 0 R/W R/W R/W Description PWM Clock Enable PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 10.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution x 256 Carrier frequency = 16/PWM conversion period With a 20-MHz system clock (), the resolution, PWM conversion period, and carrier frequency are as shown in table 10.3. 5 4 -- -- 1 0 R R Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 264 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) Bit 3 2 1 0 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Register Select These bits select the PWM data register. 0000: PWDR0 selected 0001: PWDR1 selected 0010: PWDR2 selected 0011: PWDR3 selected 0100: PWDR4 selected 0101: PWDR5 selected 0110: PWDR6 selected 0111: PWDR7 selected 1000: PWDR8 selected 1001: PWDR9 selected 1010: PWDR10 selected 1011: PWDR11 selected 1100: PWDR12 selected 1101: PWDR13 selected 1110: PWDR14 selected 1111: PWDR15 selected Table 10.2 Internal Clock Selection PWSL PWCKE 0 1 PWCKS -- 0 1 PWCKB -- -- 0 1 PCSR PWCKA -- -- 0 1 0 1 Description Clock input is disabled (system clock) is selected /2 is selected /4 is selected /8 is selected /16 is selected (Initial value) Rev. 3.00 Jan 25, 2006 page 265 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) Table 10.3 Resolution, PWM Conversion Period, and Carrier Frequency when = 20 MHz Internal Clock Frequency /2 /4 /8 /16 Resolution 50 ns 100 ns 200 ns 400 ns 800 ns PWM Conversion Period 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s Carrier Frequency 1250 kHz 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz 10.3.2 PWM Data Registers (PWDR0 to PWDR15) PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower four bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used. 10.3.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB) Each PWDPR selects the PWM output phase. PWDPRA Bit 7 6 5 4 3 2 1 0 Bit Name OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 7 to 0 These bits select the PWM output phase. Bits OS7 to OS0 correspond to outputs PW7 to PW0. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) Rev. 3.00 Jan 25, 2006 page 266 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) PWDPRB Bit 7 6 5 4 3 2 1 0 Bit Name OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 15 to 8 These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) 10.3.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) Each PWOER switches between PWM output and port output. PWOERA Bit 7 6 5 4 3 2 1 0 Bit Name OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 7 to 0 These bits, together with P1DDR, specify the P1n/PWn pin state. Bits OE7 to OE0 correspond to outputs PW7 to PW0. P1nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 267 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) PWOERB Bit 7 6 5 4 3 2 1 0 Bit Name OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 15 to 8 These bits, together with P2DDR, specify the P2n/PWn pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8. P2nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) Legend: X: Don't care To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output. The corresponding pin can be set as port output in single-chip mode or when IOSE = 1 and CS256E = 0 in SYSCR in extended mode with on-chip ROM. Otherwise, it should be noted that an address bus is output to the corresponding pin. DR data is output when the corresponding pin is used as port output. A value corresponding to PWM 256/256 output is determined by the OS bit, so the value should have been set to DR beforehand. Rev. 3.00 Jan 25, 2006 page 268 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) 10.3.5 Peripheral Clock Select Register (PCSR) PCSR selects the PWM input clock. Bit Bit Name Initial Value All 0 0 0 0 0 0 R/W Description The initial value should not be changed. 5 4 3 2 1 PWCKXB PWCKXA -- PWCKB PWCKA R/W R/W R R/W R/W See section 11.3.4, Peripheral Clock Select Register (PCSR). Reserved This bit is always read as 0 and cannot be modified. PWM Clock Select B, A Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to the clock counter. For details, see table 10.2. The initial value should not be changed. 7, 6 -- R/(W) Reserved 0 -- 0 R/(W) Reserved Rev. 3.00 Jan 25, 2006 page 269 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) 10.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 10.4 shows the duty cycles of the basic pulse. Table 10.4 Duty Cycle of Basic Pulse Upper 4 Bits B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Basic Pulse Waveform (Internal) 0123456789ABCDEF0 Rev. 3.00 Jan 25, 2006 page 270 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 10.5 shows the positions of the additional pulses added to the basic pulses, and figure 10.2 shows an example of additional pulse timing. Table 10.5 Position of Pulses Added to Basic Pulses Lower 4 Bits B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Basic Pulse No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No additional pulse Resolution width With additional pulse Basic pulse Figure 10.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) Rev. 3.00 Jan 25, 2006 page 271 of 872 REJ09B0286-0300 Section 10 8-Bit PWM Timer (PWM) Rev. 3.00 Jan 25, 2006 page 272 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) Section 11 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 11.1 Features * Division of pulse into multiple base cycles to reduce ripple * Four resolution settings The resolution can be set equal to one, two, 64, or 128 system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Eight operating speeds * Eight operation clocks (by combination of four resolution settings and two base cycle settings) Figure 11.1 shows a block diagram of the PWM (D/A) module. Internal clock /2, /64, /128 Select clock Clock Base cycle compare match A PWX0 PWX1 Fine-adjustment pulse addition Internal data bus Bus interface Comparator Comparator DADRA DADRB Base cycle compare match B Fine-adjustment pulse addition Control logic Base cycle overflow DACNT DACR Module data bus Legend: DACR : PWM D/A control register (6 bits) DADRA : PWM D/A data register A (15 bits) DADRB : PWM D/Adata register B (15 bits) DACNT : PWM D/A counter (14 bits) Figure 11.1 PWM (D/A) Block Diagram PWM1411A_000020020300 Rev. 3.00 Jan 25, 2006 page 273 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.2 Input/Output Pins Table 11.1 lists the PWM (D/A) module input and output pins. Table 11.1 Pin Configuration Name PWM output pin X0 PWM output pin X1 Abbreviation PWX0 PWX1 I/O Output Output Function PWM output of PWMX channel A PWM output of PWMX channel B 11.3 Register Descriptions The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). To access PCSR, the FLSHE bit in STCR must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * PWM (D/A) counter H (DACNTH) * PWM (D/A) counter L (DACNTL) * PWM (D/A) data register AH (DADRAH) * PWM (D/A) data register AL (DADRAL) * PWM (D/A) data register BH (DADRBH) * PWM (D/A) data register BL (DADRBL) * PWM (D/A) control register (DACR) * Peripheral clock select register (PCSR) Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. Rev. 3.00 Jan 25, 2006 page 274 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.3.1 PWM D/A Counter H, L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed in 8-bit units. DACNT should always be accessed in 16-bit units. For details, see section 11.4, Bus Master Interface. DACNTH Bit (CPU) : 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 0 REGS Bit (counter) : DACNTH Bit 7 to 0 Bit Name UC7 to UC0 Initial Value All 0 R/W R/W Description Upper Up-Counter DACNTL Bit 7 to 2 1 0 Bit Name UC8 to UC13 -- REGS Initial Value All 0 R/W R/W Description Lower Up-Counter 1 1 R R/W Reserved This bit is always read as 1 and cannot be modified. Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Rev. 3.00 Jan 25, 2006 page 275 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.3.2 PWM (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed in 16-bit units. For details, see section 11.4, Bus Master Interface. DADRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT. Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFF 0 -- 1 R Reserved This bit is always read as 1 and cannot be modified. 1 CFS 1 R/W Rev. 3.00 Jan 25, 2006 page 276 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) DADRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping both the DA0 and DA1 bits cleared to 0. This 2bit data is not compared with the UC12 and UC13 bits in DACNT. Carrier Frequency Select 0: Base cycle = Resolution (T) x 64 Range of values in DA13 to DA0 = H'0100 to H'3FFF 1: Base cycle = Resolution (T) x 256 Range of values in DA13 to DA0 = H'0040 to H'3FFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. This bit specifies which registers can be accessed. Make this bit setting before changing the address register. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed 1 CFS 1 R/W 11.3.3 PWM (D/A) Control Register (DACR) DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed. Rev. 3.00 Jan 25, 2006 page 277 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) Bit 7 6 Bit Name -- PWME Initial Value 0 0 R/W Description The initial value should not be changed. R/W PWM Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 OEB 0 R/W Output Enable B Enables or disables output on PWM (D/A) channel B. 0: PWM (D/A) channel B output (at the PWX1 pin) is disabled 1: PWM (D/A) channel B output (at the PWX1 pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWM (D/A) channel A. 0: PWM (D/A) channel A output (at the PWX0 pin) is disabled 1: PWM (D/A) channel A output (at the PWX0 pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWM (D/A) output. 0: Direct PWM (D/A) output 1: Inverted PWM (D/A) output 0 CKS 0 R/W Clock Select Selects the PWM (D/A) resolution. If the system clock () frequency is 10 MHz, resolutions of 100 ns, 200 ns, 6,400 ns, and 12,800 ns can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2, x 64, and x 128 R/(W) Reserved Rev. 3.00 Jan 25, 2006 page 278 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.3.4 Peripheral Clock Select Register (PCSR) PCSR selects the operating speed of DACR. Bit Bit Name Initial Value All 0 0 0 R/W Description The initial value should not be changed. 5 4 PWCKXB PWCKXA R/W R/W PWMX Clock Select Select the clock when the CKS bit in DACR of PWMX is set to 1. 00: Operates at resolution (T) = system clock cycle time (tcyc) x 2 01: Operates at resolution (T) = system clock cycle time (tcyc) x 64 10: Operates at resolution (T) = system clock cycle time (tcyc) x 128 11: Setting prohibited 3 2 1 0 -- PWCKB PWCKA -- 0 0 0 0 R R/W R/W Reserved This bit is always read as 0 and cannot be modified. See section 10.3.5, Peripheral Clock Select Register (PCSR). The initial value should not be changed. 7, 6 -- R/(W) Reserved R/(W) Reserved Rev. 3.00 Jan 25, 2006 page 279 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. * Write When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 11.2 Read and Write Access Methods for 16-Bit Registers Read Register Name DADRA and DADRB DACNT Legend: Word Yes Yes Byte Yes x Word Yes Yes Write Byte x x Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). x: This type of access may give incorrect results. Rev. 3.00 Jan 25, 2006 page 280 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 11.5 Operation A PWM waveform like the one shown in figure 11.2 is output from the PWMX pin. The value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 11.3 and 11.4 show the types of waveform output available. 1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256) tL T: Resolution TL = tLn (OS = 0) n=1 m (When CFS = 0, m = 256 When CFS = 1, m = 64) Figure 11.2 PWM (D/A) Operation Table 11.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Rev. 3.00 Jan 25, 2006 page 281 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) Table 11.3 Settings and Operation (Examples when = 25 MHz) PCSR Resolution CKS CFS T (s) PWCKXB PWCKXA 0 0.04 0 Base Cycle Conversion (s)/ Cycle (s)/ Frequency Frequency 2.56/ 391 kHz 655.36/ 1.53 kHz Fixed DADR Bits TL/TH (OS = 0/OS = 1) 1. Always low/high output (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1 10.24/ 97.7 kHz 1. Always low/high output (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 0 0 1 0.08 0 5.12/ 195 kHz 1310.72/ 763 Hz 1. Always low/high output (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1 20.48/ 48.8 kHz 1. Always low/high output (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 0 1 1 2.56 0 163.84/ 6.10 kHz 41.943/ 23.84 Hz 1. Always low/high output (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1 655.36/ 1.53 kHz 1. Always low/high output (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 1 0 1 5.12 0 327.68/ 3.05 kHz 83.886/ 11.92 Hz 1. Always low/high output (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1 1310.72/ 763 Hz 1. Always low/high output (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) Conversion Accuracy (Bits) 14 12 10 0 0 0 0 0 0 Bit Data 3 2 1 0 Conversion Cycle* (s) 655.36 163.84 40.96 14 12 10 0 0 0 0 0 0 655.36 163.84 40.96 14 12 10 0 0 0 0 0 0 1310.72 327.68 81.92 14 12 10 0 0 0 0 0 0 1310.72 327.68 81.92 14 12 10 0 0 0 0 0 0 41.943 10.486 2.621 14 12 10 0 0 0 0 0 0 41.943 10.486 2.621 14 12 10 0 0 0 0 0 0 83.886 20.972 5.243 14 12 10 0 0 0 0 0 0 83.886 20.972 5.243 Note: * Indicates the conversion cycle when specific DADR bits are fixed. Rev. 3.00 Jan 25, 2006 page 282 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256] Figure 11.3 Output Waveform (OS = 0, DADR corresponds to TL) Rev. 3.00 Jan 25, 2006 page 283 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256] Figure 11.4 Output Waveform (OS = 1, DADR corresponds to TH) An example of the additional pulses when CFS = 1 (base cycle = resolution (T) x 256) and OS = 1 (inverted PWMX output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0) determine the locations of the additional pulses as shown in figure 11.5. Table 11.4 lists the locations of the additional pulses. DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Duty cycle of base pulse Location of additional pulses Figure 11.5 D/A Data Register Configuration when CFS = 1 Rev. 3.00 Jan 25, 2006 page 284 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 11.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 x T. Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 11.4. Thus, an additional pulse of 1/256 x T is to be added to the base pulse. 1 conversion cycle Base cycle No. 0 Base cycle No. 1 Base cycle No. 63 Base pulse High width: 2/256 x T Base pulse 2/256 x T Additional pulse output location Additional pulse 1/256 x T Figure 11.6 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) x 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above. Rev. 3.00 Jan 25, 2006 page 285 of 872 REJ09B0286-0300 Section 11 14-Bit PWM Timer (PWMX) Rev. 3.00 Jan 25, 2006 page 286 of 872 REJ09B0286-0300 Base pulse No. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 012 345 678 Table 11.4 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lower 6 bits 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Section 12 16-Bit Free-Running Timer (FRT) Section 12 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 12.1 Features * Selection of four clock sources One of the three internal clocks (/2, /8, or /32), or an external clock input can be selected (enabling use as an external event counter). * Two independent comparators Two independent waveforms can be output. * Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. * Counter clearing The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted. Figure 12.1 shows a block diagram of the FRT. TIM8FR1A_000020020300 Rev. 3.00 Jan 25, 2006 page 287 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) External clock Internal clock FTCI Clock selector /2 /8 /32 Clock OCRAR/F (H/L) OCRA (H/L) Compare-match A Bus interface FTOA FTOB FTIA FTIB FTIC FTID Input capture Overflow Module data bus Comparator A Internal data bus FRC (H/L) Clear Compare-match B Control logic Comparator B OCRB (H/L) ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L) Comparator M Compare-match M x1 x2 OCRDM L TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt signal Legend: OCRA, OCRB OCRAR,OCRAF OCRDM FRC ICRA to D : Output compare register A, B (16 bits) : Output compare register AR, AF (16 bits) : Output compare register (16 bits) : Free-running counter (16 bits) : Input capture registers A to D (16 bits) TCSR TIER TCR TOCR : Timer control/status register (8 bits) : Timer interrupt enable register (8 bits) : Timer control register (8 bits) : Timer output compare control register (8 bits) Figure 12.1 Block Diagram of 16-Bit Free-Running Timer Rev. 3.00 Jan 25, 2006 page 288 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.2 Input/Output Pins Table 12.1 lists the FRT input and output pins. Table 12.1 Pin Configuration Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input 12.3 Register Descriptions The FRT has the following registers. * Free-running counter (FRC) * Output compare register A (OCRA) * Output compare register B (OCRB) * Input capture register A (ICRA) * Input capture register B (ICRB) * Input capture register C (ICRC) * Input capture register D (ICRD) * Output compare register AR (OCRAR) * Output compare register AF (OCRAF) * Output compare register DM (OCRDM) * Timer interrupt enable register (TIER) * Timer control/status register (TCSR) * Timer control register (TCR) * Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR. Rev. 3.00 Jan 25, 2006 page 289 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 12.3.2 Output Compare Registers A and B (OCRA and OCRB) The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 12.3.3 Input Capture Registers A to D (ICRA to ICRD) The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks () for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (). ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. Rev. 3.00 Jan 25, 2006 page 290 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 12.3.5 Output Compare Register DM (OCRDM) OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000. Rev. 3.00 Jan 25, 2006 page 291 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled Rev. 3.00 Jan 25, 2006 page 292 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Bit 2 Bit Name OCIBE Initial Value 0 R/W R/W Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled 0 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 12.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit 7 Bit Name ICFA Initial Value 0 R/W Description This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA R/(W)* Input Capture Flag A Rev. 3.00 Jan 25, 2006 page 293 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Bit 6 Bit Name ICFB Initial Value 0 R/W Description This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] 5 ICFC 0 Read ICFB when ICFB = 1, then write 0 to ICFB * Input Capture Flag C R/(W) This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC 4 ICFD 0 R/(W)* Input Capture Flag D This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD R/(W)* Input Capture Flag B Rev. 3.00 Jan 25, 2006 page 294 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Bit 3 Bit Name OCFA Initial Value 0 R/W Description This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB 1 OVF 0 R/(W)* Overflow Flag This status flag indicates that the FRC has overflowed. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF 0 CCLRA 0 R/W Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A Note: * Only 0 can be written to clear the flag. R/(W)* Output Compare Flag A Rev. 3.00 Jan 25, 2006 page 295 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB Rev. 3.00 Jan 25, 2006 page 296 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1, 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: External clock source (counting at FTCI rising edge) 12.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C. Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected Rev. 3.00 Jan 25, 2006 page 297 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Bit 4 Bit Name OCRS Initial Value 0 R/W R/W Description Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled 2 OEB 0 R/W Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled 1 OLVLA 0 R/W Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A 0 OLVLB 0 R/W Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B Rev. 3.00 Jan 25, 2006 page 298 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.4 12.4.1 Operation Pulse Output Figure 12.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 12.2 Example of Pulse Output Rev. 3.00 Jan 25, 2006 page 299 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5 12.5.1 Operation Timing FRC Increment Timing Figure 12.3 shows the FRC increment timing with an internal clock source. Figure 12.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (). Internal clock FRC input clock FRC N-1 N N+1 Figure 12.3 Increment Timing with Internal Clock Source External clock input pin FRC input clock FRC N N+1 Figure 12.4 Increment Timing with External Clock Source Rev. 3.00 Jan 25, 2006 page 300 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 12.5 shows the timing of this operation for compare-match A. FRC N N+1 N N+1 OCRA N N Compare-match A signal Clear* OLVLA Output compare A output pin FTOA Note: * Indicates instruction execution by software. Figure 12.5 Timing of Output Compare A Output 12.5.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 12.6 shows the timing of this operation. Compare-match A signal FRC N H'0000 Figure 12.6 Clearing of FRC by Compare-Match A Signal Rev. 3.00 Jan 25, 2006 page 301 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 12.7 shows the usual input capture timing when the rising edge is selected. Input capture input pin Input capture signal Figure 12.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (). Figure 12.8 shows the timing for this case. Read cycle of ICRA to ICRD T1 T2 Input capture input pin Input capture signal Figure 12.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read) Rev. 3.00 Jan 25, 2006 page 302 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 12.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 12.9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (). Figure 12.10 shows the timing when BUFEA = 1. Rev. 3.00 Jan 25, 2006 page 303 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) CPU read cycle of ICRA or ICRC T1 T2 FTIA Input capture signal Figure 12.10 Buffered Input Capture Timing (BUFEA = 1) 12.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 12.11 shows the timing of setting the ICFA to ICFD flag. Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting Rev. 3.00 Jan 25, 2006 page 304 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 12.12 shows the timing of setting the OCFA or OCFB flag. FRC N N+1 OCRA, OCRB N Compare-match signal OCFA, OCFB Figure 12.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 12.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 12.13 shows the timing of setting the OVF flag. Rev. 3.00 Jan 25, 2006 page 305 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) FRC H'FFFF H'0000 Overflow signal OVF Figure 12.13 Timing of Overflow Flag (OVF) Setting 12.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 12.14 shows the OCRA write timing. FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 12.14 OCRA Automatic Addition Timing Rev. 3.00 Jan 25, 2006 page 306 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 12.15 shows the timing of setting the mask signal. Figure 12.16 shows the timing of clearing the mask signal. Input capture signal Input capture mask signal Figure 12.15 Timing of Input Capture Mask Signal Setting FRC N N+1 ICRD + OCRDM x 2 N Compare-match signal Input capture mask signal Figure 12.16 Timing of Input Capture Mask Signal Clearing Rev. 3.00 Jan 25, 2006 page 307 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 12.2 lists the sources and priorities of these interrupts. The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources. Table 12.2 FRT Interrupt Sources Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag ICFA ICFB ICFC ICFD OCFA OCFB OVF DTC Activation Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High Rev. 3.00 Jan 25, 2006 page 308 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.7 12.7.1 Usage Notes Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 12.17 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 12.17 FRC Write-Clear Conflict Rev. 3.00 Jan 25, 2006 page 309 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 12.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 12.18 FRC Write-Increment Conflict Rev. 3.00 Jan 25, 2006 page 310 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) 12.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 12.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 12.20 shows the timing for this type of conflict. Write cycle of OCR T1 T2 Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare-match signal Disabled Figure 12.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) Rev. 3.00 Jan 25, 2006 page 311 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Old data New data Compare-match signal Disabled FRC N N+1 OCR N Automatic addition is not performed because compare-match signals are disabled. Figure 12.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Used) 12.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 12.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 12.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also cause FRC to increment. Rev. 3.00 Jan 25, 2006 page 312 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Table 12.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low No. 1 FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite 3 Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite Rev. 3.00 Jan 25, 2006 page 313 of 872 REJ09B0286-0300 Section 12 16-Bit Free-Running Timer (FRT) Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high No. 4 FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev. 3.00 Jan 25, 2006 page 314 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels, which can be used through connection to the timer connection. 13.1 Features The counter input clock can be selected from six internal clocks and an external clock * Selection of clock sources TMR_0, TMR_1: TMR_Y, TMR_X: The counter input clock can be selected from three internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A or compare-match B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of two channels Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, comparematch B, and overflow TMR_X: Four types of interrupts: Compare-match A, comparematch B, overflow, and input capture Figures 13.1 and 13.2 show block diagrams of 8-bit timers. TIMH261A_000020020300 Rev. 3.00 Jan 25, 2006 page 315 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) An input capture function is added to TMR_X. For details, see section 14, Timer Connection. External clock TMCI0 TMCI1 Internal clock TMR_0 /2, /8 /32, /64 /256, /1024 TMR_1 /2, /8 /64, /128 /1024, /2048 Clock 1 Clock 0 Select clock TCORA_0 Compare match A1 Compare match A0 TMO0 TMRI0 Overflow 1 Overflow 0 Clear 0 Clear 1 Control logic Compare match B1 Compare match B0 Comparator B_0 Comparator B_1 TCORA_1 Comparator A_0 Comparator A_1 TMO1 TMRI1 TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Legend: TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 TCR_1 : Time constant register A_0 : Time constant register B_0 : Timer counter_0 : Timer control/status register_0 : Timer control register_0 TCORA_1 TCORB_1 TCNT_1 TCSR_1 TCR_1 : Time constant register A_1 : Time constant register B_1 : Timer counter_1 : Timer control/status register_1 : Timer control register_1 Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) Rev. 3.00 Jan 25, 2006 page 316 of 872 REJ09B0286-0300 Internal bus TCNT_0 TCNT_1 Section 13 8-Bit Timer (TMR) External clock TMCIY TMCIX Internal clock TMR_Y /4 /256 /2048 TMR_X /2 /4 Clock X Clock Y Select clock TCORA_Y Compare match AX Compare match AY Overflow X Overflow Y Clear Y Clear X TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X TMOY TMRIY IVG signal Compare match BX Compare match BY Comparator B_Y Comparator B_X TCORB_Y TCORB_X Control logic TMOX TMRIX Input capture TICRR TICRF TICR Compare match C Comparator C TCORC TCSR_Y TCR_Y TISR Interrupt signals CMIAX CMIBX OVIX CMIAY CMIBY OVIY ICIX Legend: TCORA_Y : Time constant register A_Y TCORB_Y : Time constant register B_Y TCNT_Y : Timer counter_Y TCSR_Y : Timer control / status register_Y TCR_Y : Timer control register_Y TISR : Timer input select register TCORA_X : Time constant register A_X TCORB_X : Time constant register B_X TCNT_X : Timer counter_X TCSR_X : Timer control / status register_X TCR_X : Timer control register_X TICR : Input capture register TCORC TICRR TICRF : Time constant register : Input capture register R : Input capture register F TCSR_X TCR_X Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) Rev. 3.00 Jan 25, 2006 page 317 of 872 REJ09B0286-0300 Internal bus Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel TMR_0 Name Timer output Timer clock/reset input TMR_1 Timer output Timer clock/reset input TMR_Y Timer output Timer clock/reset input TMR_X Timer output Timer clock/reset input Symbol TMO0 TMI0/ExTMI0 TMO1 TMI1/ExTMI1 TMOY TMIY/ExTMIY TMOX TMIX/ExTMIX I/O Output Input Output Input Output Input Output Input Function Output controlled by compare-match External clock input (TMCI0)/external reset input (TMRI0) for the counter Output controlled by compare-match External clock input (TMCI1)/external reset input (TMRI1) for the counter Output controlled by compare-match External clock input (TMCIY)/external reset input (TMRIY) for the counter Output controlled by compare-match External clock input (TMCIX)/external reset input (TMRIX) for the counter 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). For details on timer connection register S, see section 14.3.3, Timer Connection Register S (TCONRS). TMR_0 * Timer counter_0 (TCNT_0) * Time constant register A_0 (TCORA_0) * Time constant register B_0 (TCORB_0) * Timer control register_0 (TCR_0) * Timer control/status register_0 (TCSR_0) Rev. 3.00 Jan 25, 2006 page 318 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) TMR_1 * Timer counter_1 (TCNT_1) * Time constant register A_1 (TCORA_1) * Time constant register B_1 (TCORB_1) * Timer control register_1 (TCR_1) * Timer control/status register_1 (TCSR_1) TMR_Y * Timer counter_Y (TCNT_Y) * Time constant register A_Y (TCORA_Y) * Time constant register B_Y (TCORB_Y) * Timer control register_Y (TCR_Y) * Timer control/status register_Y (TCSR_Y) * Timer input select register (TISR) TMR_X * Timer counter_X (TCNT_X) * Time constant register A_X (TCORA_X) * Time constant register B_X (TCORB_X) * Timer control register_X (TCR_X) * Timer control/status register_X (TCSR_X) * Input capture register (TICR) * Time constant register (TCORC) * Input capture register R (TICRR) * Input capture register F (TICRF) Rev. 3.00 Jan 25, 2006 page 319 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_Y and TCNT_X) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_Y and TCORA_X) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_Y and TCORB_X) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 3.00 Jan 25, 2006 page 320 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Bit 7 Bit Name CMIEB Initial Value R/W 0 R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1, 0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 13.2. Rev. 3.00 Jan 25, 2006 page 321 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Table 13.2 Clock Input to TCNT and Count Condition TCR Channel TMR_0 CKS2 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 TMR_Y 0 0 0 0 1 TMR_X 0 0 0 0 1 Common 1 1 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0* Disables clock input Increments at falling edge of internal clock /4 Increments at falling edge of internal clock /256 Increments at falling edge of internal clock /2048 Setting prohibited Disables clock input Increments at falling edge of internal clock Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /4 Setting prohibited Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock. Legend: : Don't care Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. Simultaneous setting of this condition should therefore be avoided. Rev. 3.00 Jan 25, 2006 page 322 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. TCSR_0 Bit 7 Bit Name Initial Value R/W CMFB 0 Description [Setting condition] * * 6 CMFA 0 When the values of TCNT_0 and TCORB_0 match Read CMFB when CMFB = 1, then write 0 in CMFB [Clearing condition] R/(W)* Compare-Match Flag A [Setting condition] * * 5 OVF 0 When the values of TCNT_0 and TCORA_0 match Read CMFA when CMFA = 1, then write 0 in CMFA [Clearing condition] R/(W)* Timer Overflow Flag [Setting condition] * * 4 ADTE 0 R/W When TCNT_0 overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition] A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled R/(W)* Compare-Match Flag B Rev. 3.00 Jan 25, 2006 page 323 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Bit 3 2 Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W Description Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. TCSR_1 Bit 7 Bit Name Initial Value CMFB 0 R/W Description [Setting condition] * When the values of TCNT_1 and TCORB_1 match [Clearing condition] 6 CMFA 0 * Read CMFB when CMFB = 1, then write 0 in CMFB * Compare-Match Flag A R/(W) [Setting condition] * * When the values of TCNT_1 and TCORA_1 match Read CMFA when CMFA = 1, then write 0 in CMFA [Clearing condition] R/(W)* Compare-Match Flag B Rev. 3.00 Jan 25, 2006 page 324 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Bit 5 Bit Name Initial Value OVF 0 R/W Description [Setting condition] * * 4 3 2 -- OS3 OS2 1 0 0 R R/W R/W When TCNT_1 overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition] Reserved This bit is always read as 1 and cannot be modified. Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. R/(W)* Timer Overflow Flag Rev. 3.00 Jan 25, 2006 page 325 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) TCSR_X Bit 7 Bit Name Initial Value CMFB 0 R/W Description [Setting condition] * * 6 CMFA 0 When the values of TCNT_X and TCORB_X match Read CMFB when CMFB = 1, then write 0 in CMFB [Clearing condition] R/(W)* Compare-Match Flag A [Setting condition] * * 5 OVF 0 When the values of TCNT_X and TCORA_X match Read CMFA when CMFA = 1, then write 0 in CMFA [Clearing condition] R/(W)* Timer Overflow Flag [Setting condition] * When TCNT_X overflows from H'FF to H'00 [Clearing condition] 4 ICF 0 * Read OVF when OVF = 1, then write 0 in OVF * Input Capture Flag R/(W) [Setting condition] * When a rising edge and falling edge is detected in the external reset signal in that order, after the ICST bit in TCONRI of the timer connection is set to 1 Read ICF when ICF = 1, then write 0 in ICF R/(W)* Compare-Match Flag B [Clearing condition] * 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Rev. 3.00 Jan 25, 2006 page 326 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Bit 1 0 Bit Name Initial Value OS1 OS0 0 0 R/W R/W R/W Description Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. TCSR_Y Bit 7 Bit Name Initial Value CMFB 0 R/W Description [Setting condition] * * 6 CMFA 0 When the values of TCNT_Y and TCORB_Y match Read CMFB when CMFB = 1, then write 0 in CMFB [Clearing condition] R/(W)* Compare-Match Flag A [Setting condition] * * 5 OVF 0 When the values of TCNT_Y and TCORA_Y match Read CMFA when CMFA = 1, then write 0 in CMFA [Clearing condition] R/(W)* Timer Overflow Flag [Setting condition] * * 4 ICIE 1 When TCNT_Y overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition] R/(W)* Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled R/(W)* Compare-Match Flag B Rev. 3.00 Jan 25, 2006 page 327 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Bit 3 2 Bit Name Initial Value OS3 OS2 0 0 R/W R/W R/W Description Output Select 3, 2 These bits specify how the TMOY pin output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. 13.3.6 Input Capture Register (TICR) TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the external reset input. TICR cannot be directly accessed by the CPU. The TICR function is used for the timer connection. For details, see section 14, Timer Connection. 13.3.7 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. The TCORC function is used for the timer connection. For details, see section 14, Timer Connection. Rev. 3.00 Jan 25, 2006 page 328 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.3.8 Input Capture Registers R and F (TICRR and TICRF) TICRR and TICRF are 8-bit read-only registers. The contents of TCNT are transferred at the rising edge and falling edge of the external reset input in that order, when the ICST bit in TCONRI of the timer connection is set to 1. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00. The TICRR and TICRF functions are used for timer connection. For details, see section 14, Timer Connection. 13.3.9 Timer Input Select Register (TISR) TISR selects a signal source of external clock/reset input for the counter. Bit 7 to 1 0 Bit Name Initial Value R/W -- All 1 Description The initial value should not be changed. IS 0 R/W Input Select Selects an internal synchronization signal (IVG signal) or timer clock/reset input pin (TMIY or ExTMIY) as the signal source of external clock/reset input for the TMRY counter. 0: IVG signal is selected 1: TMIY or ExTMIY (TMCIY/TMRIY) is selected R/(W) Reserved Rev. 3.00 Jan 25, 2006 page 329 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.4 13.4.1 Operation Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 13.3 Pulse Output Example Rev. 3.00 Jan 25, 2006 page 330 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.5 13.5.1 Operation Timing TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock TCNT input clock TCNT N-1 N N+1 Figure 13.4 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 13.5 Count Timing for External Clock Input Rev. 3.00 Jan 25, 2006 page 331 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 13.6 shows the timing of CMF flag setting. TCNT N N+1 TCOR Compare-match signal N CMF Figure 13.6 Timing of CMF Setting at Compare-Match 13.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 13.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. Compare-match A signal Timer output pin Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal Rev. 3.00 Jan 25, 2006 page 332 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match. Compare-match signal TCNT N H'00 Figure 13.8 Timing of Counter Clear by Compare-Match 13.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 13.9 shows the timing of clearing the counter by an external reset input. External reset input pin Clear signal TCNT N-1 N H'00 Figure 13.9 Timing of Counter Clear by External Reset Input Rev. 3.00 Jan 25, 2006 page 333 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Flag Setting Rev. 3.00 Jan 25, 2006 page 334 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of channel 1 (compare-match count mode). 13.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 13.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Rev. 3.00 Jan 25, 2006 page 335 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.7 Input Capture Operation TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture operation controlled by the ICST bit in TCONRI of the timer connection. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected while the ICST bit is set to 1, the value of TCNT_X at that time is transferred to both TICRR and TICRF, and the ICST bit is cleared to 0. The TMRIX input signal can be switched by the setting of the other bits in TCONRI. Input Capture Signal Input Timing: Figure 13.11 shows the timing of the input capture operation. TMRIX Input capture signal TCNT_X TICRR TICRF M m n n n+1 n m N N N+1 Figure 13.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock () cycle. Figure 13.12 shows the timing of this operation. Rev. 3.00 Jan 25, 2006 page 336 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) TICRR, TICRF read cycle T1 T2 TMRIX Input capture signal Figure 13.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read) Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is switched according to the setting of the bits in TCONRI of the timer connection. Input capture signal selections are shown in figure 13.13 and table 13.3. For details, see section 14.3.1, Timer Connection Register I (TCONRI). TMR_X TMIX pin Polarity inversion Signal selector TMRIX TMRI1 pin Polarity inversion TMCI1 pin Polarity inversion HFINV, HIINV SIMOD1, SIMOD0 ICST Figure 13.13 Input Capture Signal Selection Rev. 3.00 Jan 25, 2006 page 337 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Table 13.3 Input Capture Signal Selection TCONRI Bit 4 ICST 0 1 Bit 7 SIMOD1 -- 0 Bit 6 SIMOD0 -- 0 1 1 Legend: : Don't care 1 Bit 3 HFINV -- 0 1 -- -- -- -- Bit 1 HIINV -- -- -- 0 1 0 1 Description Input capture function not used TMIX pin input selection Inverted TMIX pin input selection TMRI1 pin input selection Inverted TMRI1 pin input selection TMCI1 pin input selection Inverted TMCI1 pin input selection 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.4 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as DTC activation interrupt sources. Rev. 3.00 Jan 25, 2006 page 338 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Table 13.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Channel Name TMR_X CMIAX CMIBX OVIX ICIX TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY Interrupt Source TCORA_X compare-match TCORB_X compare-match TCNT_X overflow Input capture TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Interrupt Flag CMFA CMFB OVF ICF CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF DTC Activation Possible Possible Not possible Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Low Interrupt Priority High 13.9 13.9.1 Usage Notes Conflict between TCNT Write and Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 13.14, clearing takes priority, so that the counter is cleared and the write is not performed. Rev. 3.00 Jan 25, 2006 page 339 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.14 Conflict between TCNT Write and Clear 13.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 13.15, the write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.15 Conflict between TCNT Write and Increment Rev. 3.00 Jan 25, 2006 page 340 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Disabled Figure 13.16 Conflict between TCOR Write and Compare-Match Rev. 3.00 Jan 25, 2006 page 341 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) 13.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 13.5. Table 13.5 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 13.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 13.6, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Rev. 3.00 Jan 25, 2006 page 342 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Table 13.6 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low 1 to low level* No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Clock switching from low 2 to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite 3 Clock switching from 3 high to low level Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 Rev. 3.00 Jan 25, 2006 page 343 of 872 REJ09B0286-0300 Section 13 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to high level No. 4 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 13.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. Rev. 3.00 Jan 25, 2006 page 344 of 872 REJ09B0286-0300 Section 14 Timer Connection Section 14 Timer Connection This LSI allows interconnection between a 16-bit free-running timer (FRT) and three 8-bit timer channels (TMR_1, TMR_X, and TMR_Y). This capability can be used to implement complex functions such as PWM decoding and clamp waveform output. 14.1 Features * Five input pins and four output pins, all of which can be designated for phase inversion. * Positive logic is assumed for all signals used within the timer connection facility. * An edge-detection circuit is connected to the input pins, simplifying signal input detection. * TMR_X can be used for PWM input signal decoding. * TMR_X can be used for clamp waveform generation. * An external clock signal divided by TMR_1 can be used as the FRT capture input signal. * An internal synchronization signal can be generated using the FRT and TMR_Y. * A signal generated/modified using an input signal and timer connection can be selected and output. Figure 14.1 shows a block diagram of the timer connection facility. TIMC0N01A_000020020300 Rev. 3.00 Jan 25, 2006 page 345 of 872 REJ09B0286-0300 Section 14 Timer Connection VSYNCI/ FTIA VFBACKI/ FTIB Edge detection Edge detection Phase inversion Phase inversion IVI signal selection Read flag IVI signal SET sync RES FTIA FRT input selection VSYNC modify IVO signal selection Phase inversion 16-bit FRT FTOA FRT output selection A VSYNC generation VSYNCO/ FTOA FTIC FTIB OCRA +VR, +VF CMA(R) ICRD +1M, +2M FTIC compare match CMA(F) FTID CM1M CM2M FTOB SET RES IVG signal IVO signal SET RES 2f H mask generation 2f H mask flag FRT output selection B Blank waveform generation Phase inversion CBLANK TMR_Y signal selection TMRI/TMCI 8-bit TMR_Y TMO IHG signal TMOY IHO signal selection Phase inversion TMO1 output selection B TMR_1 signal selection CMB TMCI 8-bit TMO TMR_1 TMRI PDC signal HSYNCO/ TMO1 HSYNCI/ TMI1 CSYNCI/ FTID HFBACKI/ FTCI Edge detection Edge detection Phase inversion Phase inversion IVI signal selection IHI signal TMR_X input selection PWM decoding 8-bit TMR_X TMCI/ TMRI ICR CMB TMO CMA CL1 signal CL2 signal CL3 signal CL4 generation CL4 signal TMOX Phase inversion Edge detection Read flag ICR +1C CM1C compare match Clamp waveform generation CLO signal selection Phase inversion CLAMPO/ FTIC TMIX Figure 14.1 Block Diagram of Timer Connection Rev. 3.00 Jan 25, 2006 page 346 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.2 Input/Output Pins Table 14.1 lists the timer connection input and output pins. Table 14.1 Pin Configuration Name Vertical synchronization signal input pin Horizontal synchronization signal input pin Composite synchronization signal input pin Spare vertical synchronization signal input pin Spare horizontal synchronization signal input pin Vertical synchronization signal output pin Horizontal synchronization signal output pin Clamp waveform output pin Blanking waveform output pin Abbreviation VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI VSYNCO HSYNCO CLAMPO CBLANK Input/ Output Input Input Input Input Input Output Output Output Output Function Vertical synchronization signal input pin or FTIA input pin Horizontal synchronization signal input pin or TMI1 input pin Composite synchronization signal input pin or FTID input pin Spare vertical synchronization signal input pin or FTIB input pin Spare horizontal synchronization signal input pin or FTCI input pin Vertical synchronization signal output pin or FTOA output pin Horizontal synchronization signal output pin or TMO1 output pin Clamp waveform output pin or FTIC input pin Blanking waveform output pin or FTOB output pin 14.3 Register Descriptions The timer connection has the following registers. * Timer connection register I (TCONRI) * Timer connection register O (TCONRO) * Timer connection register S (TCONRS) * Edge sense register (SEDGR) Rev. 3.00 Jan 25, 2006 page 347 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.3.1 Timer Connection Register I (TCONRI) TCONRI controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. Bit 7 6 Bit Name SIMOD1 SIMOD0 Initial Value 0 0 R/W R/W R/W Description Input Synchronization Mode Select 1, 0 These bits select the signal source of the IHI and IVI signals. * Mode 00: No signal 01: S-on-G mode 10: Composite mode 11: Separate mode * IHI Signal 00: HFBACKI input 01: CSYNCI input 1X: HSYNCI input * IVI Signal 00: VFBACKI input 01: PDC input 10: PDC input 11: VSYNCI input 5 SCONE 0 R/W Synchronization Signal Connection Enable Selects the signal source of the FIT input of the FRT, the TMI1 input of TMR_1, the TMIX input of TMR_X, and the TMIY input of TMR_Y. For details, see table 14.2. Rev. 3.00 Jan 25, 2006 page 348 of 872 REJ09B0286-0300 Section 14 Timer Connection Bit 4 Bit Name ICST Initial Value 0 R/W R/W Description Input Capture Start Bit The TMR_X external reset input (TMRIX) is connected to the IHI signal. TMR_X has input capture registers (TICR, TICRR, and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] * When a rising edge followed by a falling edge is detected on TMRIX When 1 is written in ICST after reading ICST = 0 [Setting condition] * Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 349 of 872 REJ09B0286-0300 Section 14 Timer Connection Bit 3 2 1 0 Bit Name HFINV VFINV HIINV VIINV Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Input Synchronization Signal Inversion These bits select inversion of the input phase of the spare horizontal synchronization signal (HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal synchronization signal (HSYNCI), composite synchronization signal (CSYNCI), and the vertical synchronization signal (VSYNCI). * HFINV 0: The HFBACKI pin state is used directly as the HFBACKI input 1: The HFBACKI pin state is inverted before use as the HFBACKI input * VFINV 0: The VFBACKI pin state is used directly as the VFBACKI input 1: The VFBACKI pin state is inverted before use as the VFBACKI input * HIINV 0: The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI inputs 1: The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and CSYNCI inputs * VIINV 0: The VSYNCI pin state is used directly as the VSYNCI input 1: The VSYNCI pin state is inverted before use as the VSYNCI input Rev. 3.00 Jan 25, 2006 page 350 of 872 REJ09B0286-0300 Section 14 Timer Connection Table 14.2 Synchronization Signal Connection Enable Bit 5 SCONE 0 1 Mode Description FTIA FTIB FTIB input TMO1 signal FTIC FTIC input FTID FTID input TMCI1 TMRI1 TMI1 input IHI signal TMI1 input IVI inverse signal Normal connection (Initial value) FTIA input Synchronization signal connection mode IVI signal VFBACKI IHI input signal Bit 5 SCONE 0 1 Mode Normal connection (Initial value) Synchronization signal connection mode IHI signal TMCIX Description TMRIX TMIX input IHI signal TMCIY TMIY input IVG signal TMRIY TMIY input IVG signal TMIX input Rev. 3.00 Jan 25, 2006 page 351 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.3.2 Timer Connection Register O (TCONRO) TCONRO controls output signal output, phase inversion, etc. Bit 7 6 5 4 Bit Name HOE VOE CLOE CBOE Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Output Enable These bits control enabling/disabling of output of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output. When output is disabled, the state of the relevant pin is determined by port DR and DDR, FRT, TMR, and PWM settings. Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some FRT and TMR input signal sources are determined by the SCONE bit in TCONRI. HOE: 0: The P43/TMO1/HSYNCO pin functions as the P43/TMO1 pin 1: The P43/TMO1/HSYNCO pin functions as the HSYNCO pin VOE: 0: The P61/FTOA/VSYNCO pin functions as the P61/FTOA pin 1: The P61/FTOA/VSYNCO pin functions as the VSYNCO pin CLOE: 0: The P64/FTIC/CLAMPO pin functions as the P64/FTIC pin 1: The P64/FTIC/CLAMPO pin functions as the CLAMPO pin CBOE: 0: The P66/FTOB/CBLANK pin functions as the P66/FTOB pin 1: The P66/FTOB/CBLANK pin functions as the CBLANK pin Rev. 3.00 Jan 25, 2006 page 352 of 872 REJ09B0286-0300 Section 14 Timer Connection Bit 3 2 1 0 Bit Name HOINV VOINV CLOINV CBOINV Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Output Synchronization Signal Inversion These bits select inversion of the output phase of the horizontal synchronization signal (HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO), and the blanking waveform (CBLANK). HOINV: 0: The IHO signal is used directly as the HSYNCO output 1: The IHO signal is inverted before use as the HSYNCO output VOINV: 0: The IVO signal is used directly as the VSYNCO output 1: The IVO signal is inverted before use as the VSYNCO output CLOINV: 0: The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO output 1: The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the CLAMPO output CBOINV: 0: The CBLANK signal is used directly as the CBLANK output 1: The CBLANK signal is inverted before use as the CBLANK output Rev. 3.00 Jan 25, 2006 page 353 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.3.3 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers, and the synchronization signal output signal source and generation method. Bit 7 Bit Name TMR_X/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 14.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 ISGENE 0 R/W Internal Synchronization Signal Selects internal synchronization signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals together with the HOMOD1, HOMOD0, VOMOD1, VOMOD0, CLMOD1, and CLMOD0 bits. 5 4 HOMOD1 HOMOD0 0 0 R/W R/W Horizontal Synchronization Output Mode Select 1, 0 These bits select the signal source and generation method for the IHO signal. * ISGENE = 0 00: The IHI signal (without 2fH modification) is selected 01: The IHI signal (with 2fH modification) is selected 1X: The CL1 signal is selected * ISGENE = 1 XX: The IHG signal is selected Rev. 3.00 Jan 25, 2006 page 354 of 872 REJ09B0286-0300 Section 14 Timer Connection Bit 3 2 Bit Name VOMOD1 VOMOD0 Initial Value 0 0 R/W R/W R/W Description Vertical Synchronization Output Mode Select 1, 0 These bits select the signal source and generation method for the IVO signal. * ISGENE = 0 00: The IVI signal (without fall modification or IHI synchronization) is selected 01: The IVI signal (without fall modification, with IHI synchronization) is selected 10: The IVI signal (with fall modification, without IHI synchronization) is selected 11: The IVI signal (with fall modification and IHI synchronization) is selected * 1 0 CLMOD1 CLMOD0 0 0 R/W R/W ISGENE = 1 XX: The IVG signal is selected Clamp Waveform Mode Select 1, 0 These bits select the signal source for the CLO signal (clamp waveform). * ISGENE = 0 00: The CL1 signal is selected 01: The CL2 signal is selected 1X: The CL3 signal is selected * Legend: X: Don't care ISGENE = 1 XX: The CL4 signal is selected Table 14.3 Registers Accessible by TMR_X/TMR_Y TMRX/Y 0 H'FFF0 TMR_X TCR_X 1 TMR_Y TCR_Y H'FFF1 TMR_X TCSR_X TMR_Y TCSR_Y H'FFF2 TMR_X TICRR TMR_Y H'FFF3 TMR_X TICRF TMR_Y H'FFF4 TMR_X TCNT TMR_Y H'FFF5 TMR_X TCORC TMR_Y TISR H'FFF6 TMR_X H'FFF7 TMR_X TCORA_X TCORB_X TCORA_Y TCORB_Y TCNT_Y Rev. 3.00 Jan 25, 2006 page 355 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.3.4 Edge Sense Register (SEDGR) SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH modification, and determines the phase of the IVI and IHI signals. Bit 7 Bit Name VEDG Initial Value 0 R/W Description Detects a rising edge on the VSYNCI pin. [Clearing condition] When 0 is written in VEDG after reading VEDG = 1 [Setting condition] When a rising edge is detected on the VSYNCI pin 6 HEDG 0 R/(W) * 1 1 R/(W)* VSYNCI Edge HSYNCI Edge Detects a rising edge on the HSYNCI pin. [Clearing condition] When 0 is written in HEDG after reading HEDG = 1 [Setting condition] 5 CEDG 0 When a rising edge is detected on the HSYNCI pin *1 CSYNCI Edge R/(W) Detects a rising edge on the CSYNCI pin. [Clearing condition] When 0 is written in CEDG after reading CEDG = 1 [Setting condition] When a rising edge is detected on the CSYNCI pin *1 HFBACKI Edge R/(W) Detects a rising edge on the HFBACKI pin. [Clearing condition] When 0 is written in HFEDG after reading HFEDG = 1 [Setting condition] When a rising edge is detected on the HFBACKI pin 4 HFEDG 0 Rev. 3.00 Jan 25, 2006 page 356 of 872 REJ09B0286-0300 Section 14 Timer Connection Bit 3 Bit Name VFEDG Initial Value 0 R/W Description Detects a rising edge on the VFBACKI pin. [Clearing condition] When 0 is written in VFEDG after reading VFEDG = 1 [Setting condition] When a rising edge is detected on the VFBACKI pin 2 PREDG 0 R/(W) *1 Pre-Equalization Flag Detects the occurrence of an IHI signal 2fH modification condition. The generation of a falling/rising edge in the IHI signal during a mask interval is expressed as the occurrence of a 2fH modification condition. For details, see section 14.4.4, IHI Signal and 2fH Modification. [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 [Setting condition] When an IHI signal 2fH modification condition is detected 1 IHI Undefined* 2 1 R/(W) * VFBACKI Edge R IHI Signal Level Indicates the current level of the IHI signal. Signal source and phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IHI signal at positive phase by modifying TCONRI. 0: The IHI signal is low 1: The IHI signal is high 0 IVI 2 Undefined * R IVI Signal Level Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. 0: The IVI signal is low 1: The IVI signal is high Notes: 1. Only 0 can be written, to clear the flag. 2. The initial value is undefined since it depends on the pin state. Rev. 3.00 Jan 25, 2006 page 357 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4 14.4.1 Operation PWM Decoding (PDC Signal Generation) The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1 are represented by the pulse width. To do this, a signal in which a rising edge is generated at regular intervals must be selected as the IHI signal. The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI signal (the result of the pulse width decision) at the first compare-match signal B timing after TCNT is reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using TICRR and TICRF of TMR_X can be used to determine the pulse width decision threshold. Examples of TCR and TCORB settings of TMR_X are shown in tables 14.4 and 14.5, and the PWM decoding timing chart is shown in figure 14.2. Table 14.4 Examples of TCR Settings Bit 7 6 5 4, 3 2 to 0 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 CKS2 to CKS0 Contents 0 0 0 11 001 TCNT is cleared by the rising edge of the external reset signal (IHI signal) Incremented on internal clock () Description Interrupts due to compare-match and overflow are disabled Table 14.5 Examples of TCORB (Pulse Width Threshold) Settings : 10 MHz H'07 H'0F H'1F H'3F H'7F 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s : 12 MHz 0.67 s 1.33 s 2.67 s 5.33 s 10.67 s : 16 MHz 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s : 20 MHz 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s Rev. 3.00 Jan 25, 2006 page 358 of 872 REJ09B0286-0300 Section 14 Timer Connection IHI signal is tested at compare-match IHI signal PDC signal TCNT TCORB (threshold) Counter reset caused by IHI signal Counter clear caused by TCNT overflow At the 2nd compare-match, IHI signal is not tested Figure 14.2 Timing Chart for PWM Decoding 14.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) The timer connection facility and TMR_X can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal). Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4 signal can be generated using TMR_Y. The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1 and CL2 signals can be specified by TCORA. The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3 signal can also fall when the IHI signal rises. TCNT in TMR_X is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (IHI signal). The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or more in TCORA when internal clock is selected as the TMR_X counter clock, and a value or H'01 or more when /2 is selected. When internal clock is selected, the CL1 signal pulse width is (TCORA set value + 3 0.5). When the CL2 signal is used, the setting must be made so that this pulse width is greater than the IHI signal pulse width. The value to be used as the CL3 signal pulse width is written in TCORC. TICR in TMR_X captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the Rev. 3.00 Jan 25, 2006 page 359 of 872 REJ09B0286-0300 Section 14 Timer Connection contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall. Examples of TCR settings of TMR_X are the same as those in table 14.4. The clamp waveform timing charts are shown in figures 14.3 and 14.4. Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to the resolution of the system clock. IHI signal CL1 signal CL2 signal TCNT TCORA Figure 14.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals) IHI signal CL3 signal TCNT TICR + TCORC TICR Figure 14.4 Timing Chart for Clamp Waveform Generation (CL3 Signal) Rev. 3.00 Jan 25, 2006 page 360 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4.3 8-Bit Timer Divided Waveform Period Measurement The timer connection facility, TMR_1, and the free-running timer (FRT) can be used to measure the period of an IHI signal divided waveform. Since TMR_1 can be cleared by a rising edge of the inverted IVI signal, the rise and fall of the IHI signal divided waveform can be synchronized with the IVI signal. This enables period measurement to be carried out efficiently. To measure the period of an IHI signal divided waveform, TCNT in TMR_1 is set to count the external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The value to be used as the division factor is written in TCORA, and the TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings in TMR_1, and TCR and TCSR settings in the FRT are shown in table 14.6, and the timing chart for measurement of the IVI signal and IHI signal divided waveform periods is shown in figure 14.5. The period of the IHI signal divided waveform is given by (ICRD(3) - ICRD(2)) x resolution. Rev. 3.00 Jan 25, 2006 page 361 of 872 REJ09B0286-0300 Section 14 Timer Connection Table 14.6 Examples of TCR and TCSR Settings Register TCR in TMR_1 Bit 7 6 5 4, 3 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 Contents 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output): Division by 512 When TCORB < TCORA, 1 output on compare-match B, and 0 output on compare-match A: Division by 256 0: FRC value is transferred to ICRB on falling edge of input capture input B (IHI divided signal waveform) 1: FRC value is transferred to ICRB on rising edge of input capture input B (IHI divided signal waveform) 1, 0 TCSR in FRT 0 CKS1, CKS0 CCLRA 01 0 FRC is incremented on internal clock: /8 FRC clearing is disabled Description Interrupts due to compare-match and overflow are disabled 2 to 0 TCSR in TMR_1 3 to 0 CKS2 to CKS0 OS3 to OS0 101 0011 1001 TCR in FRT 6 IEDGB 0/1 Rev. 3.00 Jan 25, 2006 page 362 of 872 REJ09B0286-0300 Section 14 Timer Connection IVI signal IHI signal divided waveform ICRB(4) ICRB(3) ICRB(2) ICRB(1) FRC ICRB Figure 14.5 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 14.4.4 IHI Signal and 2fH Modification By using the timer connection facility and FRT, even if there is a part of the IHI signal with twice the frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of the IHI signal must be approximately 30% or less, or approximately 70% or above. The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data captured in ICRD in the FRT, and compare-matches generated at these points. The interval between the two compare-matches is called a mask interval. A value equivalent to approximately 1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the rise of the IHI signal. Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When 2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture is also disabled during these intervals. Examples of TCR, TCSR, TOCR, and OCRDM settings in the FRT are shown in table 14.7, and the 2fH modification timing chart is shown in figure 14.6. Rev. 3.00 Jan 25, 2006 page 363 of 872 REJ09B0286-0300 Section 14 Timer Connection Table 14.7 Examples of TCR, TCSR, TOCR, and OCRDM Settings Register TCR in FRT Bit 4 Abbreviation IEDGD Contents 1 Description FRC value is transferred to ICRD on the rising edge of input capture input D (IHI signal) FRC is incremented on internal clock: /8 FRC clearing is disabled ICRD is set to the operating mode in which OCRDM is used 1, 0 TCSR in FRT TOCR in FRT OCRDM in FRT 0 7 7 to 0 CKS1, CKS0 CCLRA ICRDMS OCRDM7 to OCRDM0 01 0 1 H'01 to H'FF Specifies the period during which ICRD operation is masked IHI signal (without 2fH modification) IHI signal (with 2fH modification) Mask interval ICRD + OCRDM x 2 ICRD + OCRDM FRC ICRD Figure 14.6 2fH Modification Timing Chart Rev. 3.00 Jan 25, 2006 page 364 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4.5 IVI Signal Fall Modification and IHI Synchronization By using the timer connection facility and TMR_1, the fall of the IVI signal can be shifted backward by the specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized with the rise of the IHI signal. To perform 8-bit timer divided waveform period measurement, TCNT in TMR_1 is set to count external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is written in TCORB. Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When fall modification is selected, a reset is performed on a TMR_1 TCORB compare-match in TMR_1. The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal, regardless of whether or not fall modification is selected. Examples of TCR, TCSR, and TCORB settings in TMR_1 are shown in table 14.8, and the fall modification/IHI synchronization timing chart is shown in figure 14.7. Rev. 3.00 Jan 25, 2006 page 365 of 872 REJ09B0286-0300 Section 14 Timer Connection Table 14.8 Examples of TCR, TCSR, and TCORB Settings Register TCR in TMR_1 Bit 7 6 5 4, 3 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 CKS2 to CKS0 OS3 to OS0 Contents 0 0 0 11 TCNT is cleared by the rising edge of the external reset signal (inverse of the IVI signal) TCNT is incremented on the rising edge of the external clock (IHI signal) Not changed by compare-match B; output inverted by compare-match A (toggle output) When TCORB < TCORA, 1 output on compare-match B, 0 output on comparematch A Compare-match on the 4th (example) rise of the IHI signal after the rise of the inverse of the IVI signal Description Interrupts due to compare-match and overflow are disabled 2 to 0 TCSR in TMR_1 3 to 0 101 0011 1001 TCORB in TMR_1 H'03 (example) IHI signal IVI signal (PDC signal) IVO signal (without fall modification, with IHI synchronization) IVO signal (with fall modification, without IHI synchronization) IVO signal (with fall modification and IHI synchronization) TCNT 0 1 2 3 4 5 TCNT = TCORB (3) Figure 14.7 Fall Modification and IHI Synchronization Timing Chart Rev. 3.00 Jan 25, 2006 page 366 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) By using the timer connection facility, FRT, and TMR_Y, it is possible to automatically generate internal signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in synchronization with the IHG signal. The contents of OCRA in the FRT are updated by the automatic addition of the contents of OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the 0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR addition, and reset by a compare-match after an OCRAF addition. The IHG signal is the TMR_Y timer output. TMR_Y is set to count internal clock pulses, and to be cleared on a TCORA compare-match, to fix the period and set the timer output. TCORB is set so as to reset the timer output. The IVG signal is connected as the TMR_Y reset input (TMRI), and the rise of the IVG signal can be treated in the same way as a TCORA compare-match. The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG signal, and has an interval of 1 for 6 system clock periods. Examples of TCR, TCSR, TCORA, and TCORB settings in TMR_Y, and TCR, OCRAR, OCRAF, and TOCR settings in the FRT are shown in table 14.9, and the IHG signal/IVG signal timing chart is shown in figure 14.8. Rev. 3.00 Jan 25, 2006 page 367 of 872 REJ09B0286-0300 Section 14 Timer Connection Table 14.9 Examples of TCR, TCSR, TCORA, TCORB, OCRAR, OCRAF, and TOCR Settings Register TCR in TMR_Y Bit 7 6 5 4, 3 2 to 0 TCSR in TMR_Y TCORA in TMR_Y TCORB in TMR_Y TCR in FRT OCRAR in FRT OCRAF in FRT TOCR in FRT 6 OCRAMS 1, 0 CKS1, CKS0 3 to 0 Abbreviation CMIEB CMIEA OVIE CCLR1, CCLR0 Contents 0 0 0 01 TCNT is cleared by compare-match A TCNT is incremented on internal clock: /4 0 output on compare-match B 1 output on compare-match A IHG signal period = x 256 IHG signal 1 interval = x 16 FRC is incremented on internal clock: /8 IVG signal 0 interval = x 262016 IVG signal 1 interval = x 128 OCRA is set to the operating mode in which OCRAR and OCRAF are used IVG signal period = x 262144 (1024 times IHG signal) Description Interrupts due to compare-match and overflow are disabled CKS2 to CKS0 001 OS3 to OS0 0110 H'3F (example) H'03 (example) 01 H'7FEF (example) H'000F (example) 1 Rev. 3.00 Jan 25, 2006 page 368 of 872 REJ09B0286-0300 Section 14 Timer Connection IVG signal OCRA (1) = OCRA (0) + OCRAF OCRA FRC OCRA (2) = OCRA (1) + OCRAR OCRA (3) = OCRA (2) + OCRAF OCRA (4) = OCRA (3) + OCRAR 6 system clocks CL4 signal IHG signal TCORA TCORB TCNT 6 system clocks 6 system clocks Figure 14.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart Rev. 3.00 Jan 25, 2006 page 369 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4.7 HSYNCO Output With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IHI signal source and the waveform required by external circuitry. The HSYNCO output modes are shown in table 14.10. Table 14.10 HSYNCO Output Modes Mode No signal IHI Signal HFBACKI input IHO Signal IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal S-on-G mode CSYNCI input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal Meaning of IHO Signal HFBACKI input is output directly Meaningless unless there is a double-frequency part in the HFBACKI input HFBACKI input 1 interval is changed before output Internal synchronization signal is output CSYNCI input (composite synchronization signal) is output directly Double-frequency part of CSYNCI input (composite synchronization signal) is eliminated before output CSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (composite synchronization signal) is output directly Double-frequency part of HSYNCI input (composite synchronization signal) is eliminated before output HSYNCI input (composite synchronization signal) horizontal synchronization signal part is separated before output Internal synchronization signal is output HSYNCI input (horizontal synchronization signal) is output directly Meaningless unless there is a double-frequency part in the HSYNCI input (horizontal synchronization signal) HSYNCI input (horizontal synchronization signal) 1 interval is changed before output Internal synchronization signal is output IHG signal Composite HSYNCI mode input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal Separate mode HSYNCI input IHI signal (without 2fH modification) IHI signal (with 2fH modification) CL1 signal IHG signal Rev. 3.00 Jan 25, 2006 page 370 of 872 REJ09B0286-0300 Section 14 Timer Connection 14.4.8 VSYNCO Output With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of modification varies according to the IVI signal source and the waveform required by external circuitry. The VSYNCO output modes are shown in table 14.11. Table 14.11 VSYNCO Output Modes Mode No signal IVI Signal VFBACKI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal S-on-G PDC signal mode or composite mode IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) Meaning of IVO Signal VFBACKI input is output directly Meaningless unless VFBACKI input is synchronized with HFBACKI input VFBACKI input fall is modified before output VFBACKI input fall is modified and signal is synchronized with HFBACKI input before output Internal synchronization signal is output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with CSYNCI/HSYNCI input before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output CSYNCI/HSYNCI input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with CSYNCI/HSYNCI input before output Internal synchronization signal is output IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal Rev. 3.00 Jan 25, 2006 page 371 of 872 REJ09B0286-0300 Section 14 Timer Connection Mode Separate mode IVI Signal VSYNCI input IVO Signal IVI signal (without fall modification or IHI synchronization) IVI signal (without fall modification, with IHI synchronization) IVI signal (with fall modification, without IHI synchronization) IVI signal (with fall modification and IHI synchronization) IVG signal Meaning of IVO Signal VSYNCI input (vertical synchronization signal) is output directly Meaningless unless VSYNCI input (vertical synchronization signal) is synchronized with HSYNCI input (horizontal synchronization signal) VSYNCI input (vertical synchronization signal) fall is modified before output VSYNCI input (vertical synchronization signal) fall is modified and signal is synchronized with HSYNCI input (horizontal synchronization signal) before output Internal synchronization signal is output 14.4.9 CBLANK Output Using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs, with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the IVO signal. The logic of CBLANK output waveform generation is shown in figure 14.9. HFBACKI input (positive) VFBACKI input (positive) Falling edge sensing Rising edge sensing IVO signal (positive) Reset Q Set CBLANK signal (positive) Figure 14.9 CBLANK Output Waveform Generation Rev. 3.00 Jan 25, 2006 page 372 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) Section 15 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT is shown in figure 15.1. 15.1 Features * Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated. * When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated. WDT0102A_000020020300 Rev. 3.00 Jan 25, 2006 page 373 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock TCNT_0 TCSR_0 Module bus Bus interface WDT_0 WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 TCNT_1 TCSR_1 Module bus Bus interface Legend: TCSR_0 : Timer control/status register_0 TCNT_0 : Timer counter_0 TCSR_1 : Timer control/status register_1 TCNT_1 : Timer counter_1 WDT_1 Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1. Figure 15.1 Block Diagram of WDT Rev. 3.00 Jan 25, 2006 page 374 of 872 REJ09B0286-0300 Internal bus Internal bus Section 15 Watchdog Timer (WDT) 15.2 Input/Output Pins The WDT has the pins listed in table 15.1. Table 15.1 Pin Configuration Name Reset output pin External sub-clock input pin Symbol RESO EXCL I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode Inputs the clock pulses to the WDT_1 prescaler counter 15.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 15.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). * Timer counter_0 (TCNT_0) * Timer control/status register_0 (TCSR_0) * Timer counter_1 (TCNT_1) * Timer control/status register_1 (TCSR_1) 15.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0. Rev. 3.00 Jan 25, 2006 page 375 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0 Bit 7 Bit Name Initial Value R/W OVF 0 Description Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * 6 WT/IT 0 R/W When TCSR is read when OVF = 1, then 0 is written to OVF When 0 is written to TME R/(W)* Overflow Flag Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 3 -- RST/NMI 0 0 R/(W) R/W Reserved The initial value should not be changed. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested Rev. 3.00 Jan 25, 2006 page 376 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) Bit 2 1 0 Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to. The overflow frequency for = 25 MHz is enclosed in parentheses. 000: /2 (frequency: 20.4 s) 001: /64 (frequency: 655.3 s) 010: /128 (frequency: 1.3 ms) 011: /512 (frequency: 5.2 ms) 100: /2048 (frequency: 20.9 ms) 101: /8192 (frequency: 83.8 ms) 110: /32768 (frequency: 335.5 ms) 111: /131072 (frequency: 1.34 s) Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Jan 25, 2006 page 377 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) * TCSR_1 Bit 7 Bit Name Initial Value R/W OVF 0 R/(W) *1 Description Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * 6 WT/IT 0 R/W When TCSR is read when OVF = 1* , then 0 is written to OVF 2 When 0 is written to TME Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested Rev. 3.00 Jan 25, 2006 page 378 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) Bit 2 1 0 Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 25 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 20.4 s) 001: /64 (frequency: 655.3 s) 010: /128 (frequency: 1.3 ms) 011: /512 (frequency: 5.2 ms) 100: /2048 (frequency: 20.9 ms) 101: /8192 (frequency: 83.8 ms) 110: /32768 (frequency: 335.5 ms) 111: /131072 (frequency: 1.34 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: /256 (cycle: 2 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. 15.4 15.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. Rev. 3.00 Jan 25, 2006 page 379 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 15.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Internal reset signal 518 System clocks Legend: WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Write H'00 to TCNT OVF = 1* Time WT/IT = 1 Write H'00 to TME = 1 TCNT Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation NMI Rev. 3.00 Jan 25, 2006 page 380 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 15.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 15.4. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Internal timer interrupt request occurrence Figure 15.3 Interval Timer Mode Operation TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 15.4 OVF Flag Set Timing Rev. 3.00 Jan 25, 2006 page 381 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.4.3 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 15.5. TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal 132 states Internal reset signal 518 states Figure 15.5 Output Timing of RESO Signal 15.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow. Table 15.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Not possible Rev. 3.00 Jan 25, 2006 page 382 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.6 15.6.1 Usage Notes Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 15.6 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the higher bytes must contain the value H'A5 and the lower bytes must contain the write data. 15 Address: H'FFA8 0 H'5A 87 Write data 0 15 Address: H'FFA8 0 H'A5 87 Write data 0 Figure 15.6 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. Rev. 3.00 Jan 25, 2006 page 383 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 15.7 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 15.7 Conflict between TCNT Write and Increment 15.6.3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 15.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 3.00 Jan 25, 2006 page 384 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) 15.6.5 System Reset by RESO Signal Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 15.8. This LSI Reset input RES Reset signal for entire system RESO Figure 15.8 Sample Circuit for Resetting the System by the RESO Signal 15.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and sub-active or watch mode, the counter does not display the correct value due to internal clock switching. Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing timing is delayed for approximately two to three clock cycles. Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not supplied until stabilized internal oscillation is available because the main clock pulse generator is halted in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value differences for this time. Special care must be taken when using WDT_1 as a clock counter. Note that no counter value difference is produced while operated in the same mode. Rev. 3.00 Jan 25, 2006 page 385 of 872 REJ09B0286-0300 Section 15 Watchdog Timer (WDT) Rev. 3.00 Jan 25, 2006 page 386 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Section 16 Serial Communication Interface (SCI, IrDA, and CRC) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous communication function. SCI_1 can handle communication using the waveform based on the Infrared Data Association (IrDA) standard version 1.0. SCI_0 and SCI_2 provide high-speed communication at an average transfer rate of a specific system clock frequency. Reliable fast data transfers are secured using the internal cyclic redundancy check (CRC) operation circuit. Since the CRC operation circuit is not connected to the SCI, data is transferred to the circuit using the MOV instruction to be operated there. 16.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The External clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. The transmit-data-empty and receive-data-full interrupt sources can activate DTC. SCI_0 and SCI_2 can activate the RFU using the transmit-data-empty and receive-data-full interrupt sources. * Module stop mode availability SCI0022A_000020020300 Rev. 3.00 Jan 25, 2006 page 387 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Asynchronous Mode: * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Average transfer rate generator (SCI_0 and SCI_2): 460.606 kbps or 115.152 kbps selectable at 10.667-MHz operation; 720 kbps, 460.784 kbps, 230.392 kbps, or 115.196 kbps selectable at 16- or 24-MHz operation; and 230.392 kbps or 115.196 kbps selectable at 20-MHz operation Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors * SCI channel selectable (SCI_0 and SCI_2): When SSE0I = 1, TxD0 = high-impedance state and SCK0 = fixed to high input; when SSE2I = 1, TxD2 = high-impedance state and SCK2 = fixed to high input Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on detection of a error signal during transmission * Both direct convention and inverse convention are supported Figure 16.1 shows a block diagram of SCI_1, and figure 16.2 shows a block diagram of SCI_0 and SCI_2. Rev. 3.00 Jan 25, 2006 page 388 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Internal data bus Bus interface Module data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI RxD1 RSR TSR SMR Transmission/ reception control TxD1 Parity check SCK1 Parity generation Legend: RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR SSR SCMR BRR : Serial control register : Serial status register : Smart card mode register : Bit rate register Figure 16.1 Block Diagram of SCI_1 Rev. 3.00 Jan 25, 2006 page 389 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Internal data bus Bus interface Module data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 RxD0/ RxD2 TxD0/ TxD2 RSR TSR SMR SEMR SCIDTER Transmission/ reception control Parity generation SSE0I/ SSE2I Parity check Clock TEI TXI RXI ERI RFU activation request Average transfer rate generator Extenal clock SCK0/ SCK2 At 10.667-MHz operation * 115.152 kbps * 460.606 kbps At 16-MHz operation * 115.196 kbps * 230.392 kbps * 460.784 kbps * 720kbps At 20-MHz operation * 115.196 kbps * 230.392 kbps At 24-MHz operation * 115.196 kbps * 230.392 kbps * 460.784 kbps * 720 kbps Legend: RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register C/A CKE1 SSE SCR SSR SCMR BRR SEMR SCIDTER : Serial control register : Serial status register : Smart card mode register : Bit rate register : Serial enhanced mode register : Serial RFU enable register Figure 16.2 Block Diagram of SCI_0 and SCI_2 Rev. 3.00 Jan 25, 2006 page 390 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.2 Input/Output Pins Table 16.1 shows the input/output pins for each SCI channel. Table 16.1 Pin Configuration Channel 0 Symbol* SCK0 RxD0 TxD0 SSE0I 1 SCK1 RxD1/IrRxD TxD1/IrTxD 2 SCK2 RxD2 TxD2 SSE2I Note: * Input/Output Input/Output Input Output Input Input/Output Input Output Input/Output Input Output Input Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 0 stop input Channel 1 clock input/output Channel 1 receive data input (normal/IrDA) Channel 1 transmit data output (normal/IrDA) Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Channel 2 stop input Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 16.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes--normal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. * Receive shift register (RSR) * Receive data register (RDR) * Transmit data register (TDR) * Transmit shift register (TSR) * Serial mode register (SMR) * Serial control register (SCR) * Serial status register (SSR) * Smart card mode register (SCMR) * Bit rate register (BRR) Rev. 3.00 Jan 25, 2006 page 391 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) * Serial interface control register (SCICR)*1 * Serial enhanced mode register (SEMR)*2 * Serial RFU enable register (SCIDTER)*2 Notes: 1. SCICR is not available in SCI_0 or SCI_2. 2. SEMR and SCIDTER are not available in SCI_1. 16.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 16.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. 16.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 16.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 3.00 Jan 25, 2006 page 392 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0) Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. Rev. 3.00 Jan 25, 2006 page 393 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1,0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 16.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 16.3.9, Bit Rate Register (BRR)). Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1) Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GS Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see section 16.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 16.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 5 PE 0 R/W Rev. 3.00 Jan 25, 2006 page 394 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 4 Bit Name O/E Initial Value 0 R/W R/W Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 16.7.2, Data Format (Except in Block Transfer Mode). 3 2 BCP1 BCP0 0 0 R/W R/W Basic Clock Pulse 1,0 These bits select the number of basic clock cycles in a 1-bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 16.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 16.3.9, Bit Rate Register (BRR). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1,0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 16.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 16.3.9, Bit Rate Register (BRR)). Rev. 3.00 Jan 25, 2006 page 395 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 16.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 16.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. Rev. 3.00 Jan 25, 2006 page 396 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1,0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 397 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Clock Enable 1,0 Controls the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 16.7.8, Clock Output Control. When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1X: Reserved When GM in SMR = 1 00: Output fixed to low 01: Clock output 10: Output fixed to high 11: Clock output 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Legend: X: Don't care 16.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. Rev. 3.00 Jan 25, 2006 page 398 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0) Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE =1 When a TXI interrupt request is issued allowing DTC to write data to TDR When RFU is activated by TDRE = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) [Clearing conditions] * * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR When RFU is activated by RDRE = 1 allowing data to be read from RDR (only for SCI_0 and SCI_2) [Clearing conditions] * * * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Rev. 3.00 Jan 25, 2006 page 399 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 5 Bit Name ORER Initial Value 0 R/W R/(W)* Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] * 4 FER 0 R/(W)* Framing Error [Setting condition] * * When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition] In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition] * 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE =1 When a TXI interrupt request is issued allowing DTC to write data to TDR When RFU is activated by TDRE = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) [Clearing conditions] * * * Rev. 3.00 Jan 25, 2006 page 400 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 1 Bit Name MPB Initial Value 0 R/W R Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1) Bit 7 Bit Name TDRE Initial Value 1 R/W Description Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and TDR can be written to. When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write data to TDR When BLK in SMR is 0, and RFU is activated by TEND = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) When BLK in SMR is 1 and RFU is activated by TDRE = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) R/(W)* Transmit Data Register Empty [Clearing conditions] * * * * Rev. 3.00 Jan 25, 2006 page 401 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 6 Bit Name RDRF Initial Value 0 R/W Description Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR When RFU is activated by RDRF = 1 allowing data to be read from RDR (only for SCI_0 and SCI_2) R/(W)* Receive Data Register Full [Clearing conditions] * * * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] * 4 ERS 0 R/(W)* Error Signal Status [Setting condition] * * When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing condition] 3 PER 0 R/(W)* Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition] Rev. 3.00 Jan 25, 2006 page 402 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both TE and EPS in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after the start of 1-byte data transfer. The set timing depends on the register setting as follows. When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] * * * When 0 is written to TEND after reading TEND = 1 When a TXI interrupt request is issued allowing DTC to write the next data to TDR When BLK in SMR is 0 and RFU is activated by TEND = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) When BLK in SMR is 1 and RFU is activated by TDRE = 1 allowing data to be written to TDR (only for SCI_0 and SCI_2) * 1 0 Note: MPB MPBT * 0 0 R R/W Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Only 0 can be written, to clear the flag. Rev. 3.00 Jan 25, 2006 page 403 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit 7 to 4 3 Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Stores receive data as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Stores receive data as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 -- 1 R Reserved This bit is always read as 1 and cannot be modified. 0 SMIF 0 R/W Smart Card Interface Mode Select: When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode Rev. 3.00 Jan 25, 2006 page 404 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 16.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 16.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode Clocked synchronous mode Smart card interface mode Bit Rate B= Error x 106 x (N + 1) Error (%) = -- 64 x 22n-1 { B x 64 x2x 10x (N + 1) - 1} x 100 6 2n-1 B= x 106 8 x 22n-1 x (N + 1) x 106 S x 22n+1 x (N + 1) B= Error (%) = { BxSx2 x 106 2n+1 x (N + 1) - 1 x 100 } Notes: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 0 0 1 1 SMR Setting BCP1 BCP0 0 1 0 1 S 32 64 372 256 Table 16.3 shows sample N settings in BRR in normal asynchronous mode. Table 16.4 shows the maximum bit rate settable for each frequency. Table 16.6 shows sample N settings in BRR in clocked synchronous mode, and table 16.8 shows sample N settings in BRR in smart card interface mode. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 16.7.4, Receive Data Sampling Timing and Reception Margin. Tables 16.5 and 16.7 show the maximum bit rates with external clock input. Rev. 3.00 Jan 25, 2006 page 405 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- Operating Frequency (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Jan 25, 2006 page 406 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Jan 25, 2006 page 407 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 16 16 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 166 233 166 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 25 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 Legend: --: Can be set, but there will be a degree of error. Note: Make the settings so that the error does not exceed 1%. Rev. 3.00 Jan 25, 2006 page 408 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 Maximum Bit Rate (bit/s) 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 781250 (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 (MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 Table 16.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 15.000 1.5360 1.8432 2.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 (MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 External Input Clock (MHz) 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.2500 Maximum Bit Rate (bit/s) 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 390625 Rev. 3.00 Jan 25, 2006 page 409 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. Operating Frequency (MHz) 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1* 0 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* 3 2 2 1 0 0 0 0 -- -- -- -- 97 155 77 155 249 124 62 24 -- -- -- -- n 8 N n 10 N n 16 N n 20 N n 25 N Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 2 4 6 8 10 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 (MHz) 12 14 16 18 20 25 External Input Clock (MHz) 2.0000 2.3333 2.6667 3.0000 3.3333 4.1667 Maximum Bit Rate (bit/s) 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 4166666.7 Rev. 3.00 Jan 25, 2006 page 410 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) Operating Frequency (MHz) 7.1424 Bit Rate (bit/s) 9600 n 0 N 0 Error (%) 0.00 n 0 10.0000 N 1 Error (%) 30 n 0 10.7136 N 1 Error (%) 25 n 0 13.0000 N 1 Error (%) 8.99 Operating Frequency (MHz) 14.2848 Bit Rate (bit/s) 9600 nN 0 1 Error (%) 0.00 16.0000 nN 0 1 Error (%) 12.01 18.0000 nN 0 2 Error (%) 15.99 n 0 20.0000 Error N (%) 2 6.60 25.0000 nN 0 3 Error (%) 12.49 Table 16.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) Maximum Bit Rate (bit/s) 9600 13441 14400 17473 Maximum Bit Rate (bit/s) 19200 21505 24194 26882 33602 (MHz) 7.1424 10.0000 10.7136 13.0000 n 0 0 0 0 N 0 0 0 0 (MHz) 14.2848 16.0000 18.0000 20.0000 25.0000 n 0 0 0 0 0 N 0 0 0 0 0 Rev. 3.00 Jan 25, 2006 page 411 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.10 Serial Interface Control Register (SCICR) SCICR controls IrDA operation of SCI_1. Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies SCI_1 I/O pins for either normal SCI or IrDA. 0: TxD1/IrTxD and RxD1/IrRxD pins function as TxD1 and RxD1 pins, respectively 1: TxD1/IrTxD and RxD1/IrRxD pins function as IrTxD and IrRxD pins, respectively 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 Specifies the high-level width of the clock pulse during IrTxD output pulse encoding when the IrDA function is enabled. 000: B x 3/16 (three sixteenths of the bit rate) 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 3, 2 1, 0 -- -- All 0 All 0 R/W R Reserved The initial value should not be changed. Reserved These bits are always read as 0 and cannot be modified. 16.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) SEMR_0 and SEMR_2 select the SCI_0 and SCI_2 functions, respectively, and the clock source in asynchronous mode. The basic clock is automatically specified when the average transfer rate operation is selected. Rev. 3.00 Jan 25, 2006 page 412 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 7 Bit Name SSE Initial Value 0 R/W R/W Description SCI Select Enable Enables/disables the external pins to select the SCI functions when the external clock is supplied in clocked synchronous mode. 0: Disables the external pins to select the SCI functions (normal) 1: Enables the external pins to select the SCI functions * SCI_0 SSE0I pin input = 0 (selected state): SCI_0 operates normally SSE0I pin input = 1 (non-selected state): SCI_0 halts operation (TxD0 = high-impedance state, SCK0 = fixed to high) * SCI_2 SSE2I pin input = 0 (selected state): SCI_2 operates normally SSE2I pin input = 1 (non-selected state): SCI_2 halts operation (TxD2 = high-impedance state, SCK2 = fixed to high) 6, 5 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 4 ABCS 0 R/W Asynchronous Mode Basic Clock Select Specifies the basic clock for a 1-bit cycle in asynchronous mode. This bit is valid only in asynchronous mode (C/A bit in SMR is 0). 0: The basic clock has a frequency 16 times the transfer clock frequency (normal operation) 1: The basic clock has a frequency 8 times the transfer clock frequency (double-speed operation) Rev. 3.00 Jan 25, 2006 page 413 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 3 2 1 0 Bit Name ACS4 ACS2 ACS1 ACS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Asynchronous Mode Clock Source Select These bits specify the clock source and the average transfer rate in asynchronous mode. These bits are valid only when external clock is supplied in asynchronous mode. 0000: Normal operation with external clock input and average transfer rate operation not used (operated using the basic clock with a frequency 16 or 8 times the transfer clock frequency) 0001: Average transfer rate operation at 115.152 kbps when the system clock frequency is 10.667 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 0010: Average transfer rate operation at 460.606 kbps when the system clock frequency is 10.667 MHz (operated using the basic clock with a frequency 8 times the transfer clock frequency) 0011: Reserved 0100: Reserved 0101: Average transfer rate operation at 115.196 kbps when the system clock frequency is 16 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 0110: Average transfer rate operation at 460.784 kbps when the system clock frequency is 16 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 0111: Average transfer rate operation at 720 kbps when the system clock frequency is 16 MHz (operated using the basic clock with a frequency 8 times the transfer clock frequency) Rev. 3.00 Jan 25, 2006 page 414 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Bit 3 2 1 0 Bit Name ACS4 ACS2 ACS1 ACS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description 1000: Average transfer rate operation at 115.196 kbps when the system clock frequency is 16 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1001: Average transfer rate operation at 230.392 kbps when the system clock frequency is 16 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1011: Average transfer rate operation at 115.196 kbps when the system clock frequency is 20 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1011: Average transfer rate operation at 230.392 kbps when the system clock frequency is 20 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1100: Average transfer rate operation at 115.196 kbps when the system clock frequency is 24 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1101: Average transfer rate operation at 230.392 kbps when the system clock frequency is 24 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1110: Average transfer rate operation at 460.784 kbps when the system clock frequency is 24 MHz (operated using the basic clock with a frequency 16 times the transfer clock frequency) 1111: Average transfer rate operation at 720 kbps when the system clock frequency is 24 MHz (operated using the basic clock with a frequency 8 times the transfer clock frequency) Rev. 3.00 Jan 25, 2006 page 415 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2) SCIDTER_0 and SCIDTER_2 enable or disable the RFU activation requests by SCI_0 and SCI_2, respectively. Bit 7 Bit Name TDRE_DTE Initial Value 0 R/W R/W Description TERE Data Transfer Enable Enables/disables the RFU to be activated by TDRE = 1. * SMIF = 0 in SCMR, or SMIF = 1 and BLK = 1 in SMR 0: Disables activation of the RFU by TDRE = 1 in SSR, and does not mask the TXI interrupt request 1: Enables activation of the RFU by TDRE = 1 in SSR, and masks the TXI interrupt request [Clearing condition] When data transfer has been completed by activation of the RFU by TDRE = 1 (FIFO EMPTY) * SMIF = 1 in SCMR and BLK = 1 in SMR 0: Disables activation of the RFU by TEND = 1 in SSR, and does not mask the TXI interrupt request 1: Enables activation of the RFU by TEND = 1 in SSR, and masks the TXI interrupt request [Clearing condition] When data transfer has been completed by the RFU activation by TEND = 1 in SSR 6 RDRF_DTE 0 R/W RDRF Data Transfer Enable Enables/disables activation of the RFU by RDRF = 1 in SSR. 0: Disables activation of the RFU, and does not mask the RXI interrupt request 1: Enables activation of the RFU, and masks the RXI interrupt request [Clearing condition] When data transfer has been completed by the RFU activated by RDRF = 1 in SSR (FIFO FULL) 5 to 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 416 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4 Operation in Asynchronous Mode Figure 16.3 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 16.3 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 3.00 Jan 25, 2006 page 417 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.1 Data Transfer Format Table 16.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 16.5, Multiprocessor Communication Function. Table 16.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transfmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP Legend: : Start bit S STOP : Stop bit : Parity bit P MPB : Multiprocessor bit : Don't care -- Rev. 3.00 Jan 25, 2006 page 418 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 16.4. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = (0.5 - { D - 0.5 1 )- - (L - 0.5) F N 2N } x 100 [%] ..... Formula (1) M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = {0.5 - 1/(2 x 16) } x 100[%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 16.4 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00 Jan 25, 2006 page 419 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 16.5. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 16.5 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 3.00 Jan 25, 2006 page 420 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.4 Serial Enhanced Mode Clock SCI_0 and SCI_2 can be operated not only based on the clocks described in section 16.4.3, Clock, but based on the following clocks, which are specified by the serial enhanced mode registers, SEMR_0 and SEMR_2. Double-Speed Operation: Operations that are usually achieved using the clock with frequency 16 times the normal bit rate can be achieved using the clock with frequency 8 times the bit rate in this mode. That is, double transfer rate can be achieved using a single basic clock. Double-speed operation can be specified by the ABCS bit in SEMR and is available for both clock sources of an internal clock generated by the on-chip baud rate generator and an external clock input at the SCK pin. However, double-speed operation cannot be specified when the average transfer rate operation is selected. Average Transfer Rate Operation: The SCI can be operated based on the clock with an average transfer rate generated from the system clock instead of the external clock input at the SCK pin. In this case, the SCK pin is fixed to input. Average transfer rate operation can be specified by the ACS4 and ACS2 to ACS0 bits in SEMR. Double-speed operation may be selected by clearing the ACS4 and ACS2 to ACS0 bits to 0. Figures 16.6 and 16.7 show some examples of internal basic clock operations when average transfer rate operation is selected. Rev. 3.00 Jan 25, 2006 page 421 of 872 REJ09B0286-0300 When = 10.667 MHz Average transfer rate at basic clock = 115.152 kbps 3 2.667 MHz 3 7 8 9 10 11 12 13 14 15 16 1 bit = Basic clock x 16* Average tranfer rate = 1.8424 MHz/16 = 115.152 kbps Average error rate = -0.043% 1.8424 MHz 45 6 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 34 1 2 Basic clock 10.6677 MHz/4 = 2.667 MHz 2.667 MHz x (38/55) = Rev. 3.00 Jan 25, 2006 page 422 of 872 REJ09B0286-0300 3 5.333 MHz 3 1 bit = Basic clock x 8* Average tranfer rate = 3.6848 MHz/8= 460.606 kbps Average error rate = -0.043% 3.6848 MHz 45 6 7 8 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 34 1.8424 MHz (average) 1 2 Average transfer rate at basic clock = 460.606 kbps 1 2 Basic clock 10.667 MHz/2 = 5.333 MHz 5.333 MHz x (38/55) = Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 3.6848 MHz (average) 1 2 Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1) Note: * 1-bit length depends on the changes in basic clock synchronization. When = 16 MHz Average transfer rate at basic clock = 115.196 kbps 1 2 MHz 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 34 5 6 78 Basic clock 16 MHz/8 = 2 MHz 4 1 bit = Basic clock x 16* Average tranfer rate = 1.8431 MHz/16 = 115.196 kbps Average error rate = -0.004% 2 MHz x (47/51) = 1.8431 MHz 5678 9 10 11 12 13 14 15 16 1.8431 MHz (average) 1 2 3 Average transfer rate at basic clock = 460.784 kbps 1 8 MHz 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Basic clock 16 MHz/2 = 8 MHz 4 1 bit = Basic clock x 16* Average tranfer rate = 7.3725 MHz/16 = 460.784 kbps Average error rate = -0.004% 8 MHz x (47/51) = 7.3725 MHz 5678 9 10 11 12 13 14 15 16 7.3725 MHz (average) 1 2 3 Average transfer rate at basic clock = 720 kbps 1 8 MHz 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Basic clock 16 MHz/2 = 8 MHz 5.76 MHz 45 6 7 8 8 MHz x (18/25) = 5.76 MHz (average) 1 2 3 1 bit = Basic clock x 8* Average tranfer rate = 5.76 MHz/8 = 720 kbps Average error rate = -0% Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2) Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Rev. 3.00 Jan 25, 2006 page 423 of 872 REJ09B0286-0300 Note: * 1-bit length depends on the changes in basic clock synchronization. Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.5 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 16.8. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 16.8 Sample SCI Initialization Flowchart Rev. 3.00 Jan 25, 2006 page 424 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.6 Serial Data Transmission (Asynchronous Mode) Figure 16.9 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 16.10 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine TEI interrupt request generated 1 frame Figure 16.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Jan 25, 2006 page 425 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. [4] Clear TE bit in SCR to 0 Figure 16.10 Sample Serial Transmission Flowchart Rev. 3.00 Jan 25, 2006 page 426 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.4.7 Serial Data Reception (Asynchronous Mode) Figure 16.11 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Jan 25, 2006 page 427 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.12 shows a sample flow chart for serial data reception. Table 16.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Rev. 3.00 Jan 25, 2006 page 428 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DTC is initiated by an RXI interrupt and reads data from RDR. Legend: : Logical add (OR) No All data received? Yes Clear RE bit in SCR to 0 [5] Figure 16.12 Sample Serial Reception Flowchart (1) Rev. 3.00 Jan 25, 2006 page 429 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 16.12 Sample Serial Reception Flowchart (2) Rev. 3.00 Jan 25, 2006 page 430 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 16.13 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 3.00 Jan 25, 2006 page 431 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 16.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 16.5.1 Multiprocessor Serial Data Transmission Figure 16.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 3.00 Jan 25, 2006 page 432 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart 16.5.2 Multiprocessor Serial Data Reception Figure 16.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data Rev. 3.00 Jan 25, 2006 page 433 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 16.15 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 16.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.00 Jan 25, 2006 page 434 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value. Legend: : Logical add (OR) Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR [2] FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes [3] FER ORER = 1 No Read RDRF flag in SSR Yes No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 (Continued on next page) [5] Error processing Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.00 Jan 25, 2006 page 435 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Jan 25, 2006 page 436 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6 Operation in Clocked Synchronous Mode Figure 16.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 16.17 Data Format in Synchronous Communication (LSB-First) 16.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 16.6.2 SCI Initialization (Synchronous) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 16.18. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is Rev. 3.00 Jan 25, 2006 page 437 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. [2] Set the data transfer format in SMR and SCMR. [1] Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 16.18 Sample SCI Initialization Flowchart 16.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 16.19 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. Rev. 3.00 Jan 25, 2006 page 438 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 16.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 3.00 Jan 25, 2006 page 439 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 16.20 Sample Serial Transmission Flowchart Rev. 3.00 Jan 25, 2006 page 440 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 16.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 16.21 Example of SCI Receive Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.22 shows a sample flowchart for serial data reception. Rev. 3.00 Jan 25, 2006 page 441 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Read ORER flag in SSR [2] Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 16.22 Sample Serial Reception Flowchart Rev. 3.00 Jan 25, 2006 page 442 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 16.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set the TE and RE bits to 1 with a single instruction. 16.6.6 SCI Selection in Serial Enhanced Mode SCI_0 and SCI_2 provides the following capability according to the serial enhanced mode registers (SEMR_0 and SEMR_2) settings. If the SCI is used in clocked synchronous mode with clock input, the SCI channel can be enabled/disabled using the input at the external pins. The external pins include PA0/SSE0I (SCI_0) and PA1/SSE2I (SCI_2); therefore, this capability is not available in modes where the PA0 and PA1 pins are automatically set for address output. When the SCI operation is disabled (not selected) by input at the external pins, TxD output is fixed to the high-impedance state and SCK input is internally fixed to high. One-to-multipoint communication is possible if the master device, which outputs SCK, controls these external pins for chip selection. SCI selection capability is selected using the SSE bits in SEMR. Rev. 3.00 Jan 25, 2006 page 443 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] [3] Read ORER flag in SSR Yes [3] Error processing ORER = 1 No [4] Read RDRF flag in SSR No RDRF = 1 Yes [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, No before the MSB (bit 7) of the current All data received? [5] frame is transmitted, read 1 from the TDRE flag to confirm that writing is Yes possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked Clear TE and RE bits in SCR to 0 and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DTC is initiated by a receive Note: When switching from transmit or receive operation to simultaneous data full interrupt (RXI) and reads transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. data from RDR. Figure 16.23 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 3.00 Jan 25, 2006 page 444 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 16.7.1 Sample Connection Figure 16.24 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card Figure 16.24 Pin Connection for Smart Card Interface Rev. 3.00 Jan 25, 2006 page 445 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.2 Data Format (Except in Block Transfer Mode) Figure 16.25 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after two or more etu. In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from the transmitting station Output from the receiving station : Start bit : Data bits : Parity bit : Error signal Legend: Ds D0 to D7 Dp DE Figure 16.25 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state Figure 16.26 Direct Convention (SDIR = SINV = O/E = 0) E Rev. 3.00 Jan 25, 2006 page 446 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 16.26. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state Figure 16.27 Inverse Convention (SDIR = SINV = O/E = 1) E For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 16.27. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 16.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. * If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. 16.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the internal basic clock in order to perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th Rev. 3.00 Jan 25, 2006 page 447 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 16.28. The reception margin here is determined by the following formula. M = (0.5 - 1 D - 0.5 ) - (L - 0.5) F - (1 + F) x 100 [%] 2N N ..... Formula (1) M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 32, 64, 372, 256) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock rate deviation Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is determined by the formula below. M = (0.5 - 1/2 x 372) x 100[%] = 49.866% 372 clock cycles 186 clock cycles 0 Internal basic clock 185 371 0 185 371 0 Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 16.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency Is 372 Times the Bit Rate) Rev. 3.00 Jan 25, 2006 page 448 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ORER, ERS, and PER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval. Do not set the TE and RE bits to 1 simultaneously except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, and initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from transmission to reception, first verify that transmission has completed, and initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. Rev. 3.00 Jan 25, 2006 page 449 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.6 Serial Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted. Figure 16.29 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 16.31 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. The above procedure also applies to the case in which RFU is activated by TEND in SCI_0 and SCI_2. When transmitting/receiving data using the DTC or RFU, be sure to set and enable them prior to making SCI settings. For DTC and RFU settings, see section 7, Data Transfer Controller (DTC) and section 8, RAM-FIFO Unit (RFU). Rev. 3.00 Jan 25, 2006 page 450 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Re-transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) (n + 1) th transfer frame Ds D0 D1 D2 D3 D4 TDRE Transfer frorm TDR to TSR TEND [2] Transfer from TDR to TSR Transfer from TDR to TSR [4] FER/ERS [1] [3] Figure 16.29 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 16.30. I/O data TXI (TEND interrupt) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu GM = 0 11.0 etu GM = 1 Legend: Ds : Stat bit D0 to D7 : Data bits Dp : Parity bit DE : Error signal Figure 16.30 TEND Flag Set Timings during Transmission Rev. 3.00 Jan 25, 2006 page 451 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 16.31 Sample Transmission Flowchart Rev. 3.00 Jan 25, 2006 page 452 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 16.32 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set. Figure 16.33 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. The above flow also applies to the case in which RFU is activated by RDRF in SCI_0 and SCI_2. Note: For operations in block transfer mode, see section 16.4, Operation in Asynchronous Mode. (n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Re-transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 16.32 Data Re-transfer Operation in SCI Reception Mode Rev. 3.00 Jan 25, 2006 page 453 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Start Initialization Start reception ORER = 0 and PER = 0? No Yes Error processing No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 End Figure 16.33 Sample Reception Flowchart 16.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 16.34 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 1. Rev. 3.00 Jan 25, 2006 page 454 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) CKE0 SCK Specified pulse width Specified pulse width Figure 16.34 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. 4. Set the CKE0 bit in SCR to 1 to start clock output. At Transition from Smart Card Interface Mode to Software Standby Mode: 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty ratio retained. 5. Make the transition to software standby mode. At Transition from Software Standby Mode to Smart Card Interface Mode: 1. Cancel software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty ratio is then generated. Rev. 3.00 Jan 25, 2006 page 455 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Normal operation Software standby Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 16.35 Clock Stop and Restart Procedure 16.8 IrDA Operation IrDA operation can be used with SCI_1. Figure 16.36 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 pins in SCI_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming. IrDA TxD1 TxD1/IrTxD RxD1/IrRxD Pulse encoder Pulse decoder RxD1 SCI_1 SCICR Figure 16.36 IrDA Block Diagram Transmission: During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 16.37). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in SCICR. Rev. 3.00 Jan 25, 2006 page 456 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of at least 1.4 s to 1.6 s can be specified. For serial data of level 1, no pulses are output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmission Reception IR frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Bit cycle Pulse width is 1.6 s to 3/16 bit cycle Figure 16.37 IrDA Transmission and Reception Reception: During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_1. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0. High-Level Pulse Width Selection: Table 16.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Rev. 3.00 Jan 25, 2006 page 457 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.12 IrCKS2 to IrCKS0 Bit Settings Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 25 Bit Rate (bps) (Upper Row)/Bit Interval x 3/16 (s) (Lower Row) 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 57600 3.26 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 115200 1.63 -- -- -- -- 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 Legend: --: An SCI bit rate setting cannot be made. Rev. 3.00 Jan 25, 2006 page 458 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.9 16.9.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 16.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. When the DTE bit in TDRE in SCIDTER_0 and SCIDTER_2 is 1, TXI0 and TXI2 interrupts are masked, and when the DTE bit in RDRF is 1, RXI0 and RXI2 interrupts are masked. Rev. 3.00 Jan 25, 2006 page 459 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Table 16.13 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High 16.9.2 Interrupts in Smart Card Interface Mode Table 16.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 16.14 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 1 ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 Interrupt Source Receive error, error signal detection Receive data full Transmit data empty Receive error, error signal detection Receive data full Transmit data empty Receive error, error signal detection Receive data full Transmit data empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Low Priority High Rev. 3.00 Jan 25, 2006 page 460 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Data transmission/reception using the DTC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. When the DTE bit in TDRE in SCIDTER_0 and SCIDTER_2 is 1, TXI_0 and TXI_2 interrupt requests are masked, and when the DTE bit in RDRF is 1, RXI0 and RXI2 interrupt requests are masked. 16.10 Usage Notes 16.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 27, Power-Down Modes. 16.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Rev. 3.00 Jan 25, 2006 page 461 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.10.3 Mark State and Break Detection When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 16.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 16.10.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. 16.10.6 Restrictions on Using DTC or RFU When the external clock source is used as a synchronization clock, update TDR by the DTC or RFU and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 16.38). When using the DTC or RFU to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC or RFU activation source. Rev. 3.00 Jan 25, 2006 page 462 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 16.38 Sample Transmission using DTC in Clocked Synchronous Mode 16.10.7 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 16.39 shows a sample flowchart for mode transition during transmission. Figures 16.40 and 16.41 show the pin states during transmission. Before making the transition from the transmission mode using DTC transfer to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC. Reception: Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 16.42 shows a sample flowchart for mode transition during reception. Rev. 3.00 Jan 25, 2006 page 463 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 0. [2] Also clear TIE and TEIE to 0 when they are 1. Make transition to software standby mode etc. Cancel software standby mode etc. [3] [3] Module stop, watch, sub-active, and sub-sleep modes are included. Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 16.39 Sample Flowchart for Mode Transition during Transmission Transition to Software standby Transmission end software standby mode cancelled mode Transmission start TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 16.40 Pin States during Transmission in Asynchronous Mode (Internal Clock) Rev. 3.00 Jan 25, 2006 page 464 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) Transmission start Transmission end Transition to Software standby software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 16.41 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop, watch, sub-active, and subsleep modes are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 16.42 Sample Flowchart for Mode Transition during Reception Rev. 3.00 Jan 25, 2006 page 465 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.10.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 16.43. Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output Figure 16.43 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. End serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 (switch to port output) 5. CKE1 bit = 0 High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 16.44 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 3.00 Jan 25, 2006 page 466 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11 CRC Operation Circuit The cyclic redundancy check (CRC) operation circuit detects errors in data blocks. 16.11.1 Features The features of the CRC operation circuit are listed below. * CRC code generated for any desired data length in an 8-bit unit * CRC operation executed on eight bits in parallel * One of three generating polynomials selectable * CRC code generation for LSB-first or MSB-first communication selectable Figure 16.45 shows a block diagram of the CRC operation circuit. CRCCR Internal bus Control signal CRCDIR CRC code generation circuit CRCDOR Legend Legend: CRCCR : CRC control register CRCDIR : CRC data input register CRCDOR : CRC data output register Figure 16.45 Block Diagram of CRC Operation Circuit 16.11.2 Register Descriptions The CRC operation circuit has the following registers. * CRC control register (CRCCR) * CRC data input register (CRCDIR) * CRC data output register (CRCDOR) Rev. 3.00 Jan 25, 2006 page 467 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial. Bit 7 6 to 3 2 Bit Name DORCLR -- LMS Initial Value 0 All 0 0 R/W W R R/W Description CRCDOR Clear Setting this bit to 1 clears CRCDOR to H'0000. Reserved The initial value should not be changed. CRC Operation Switch Selects CRC code generation for LSB-first or MSB-first communication. 0: Performs CRC operation for LSB-first communication. The lower byte (bits 7 to 0) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1: Performs CRC operation for MSB-first communication. The upper byte (bits 15 to 8) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1 0 G1 G0 0 0 R/W R/W CRC Generating Polynomial Select: Selects the polynomial. 00: Reserved 01: X + X + X + 1 10: X 11: X 16 16 8 2 +X +X 15 12 +X +1 +X +1 5 2 CRC Data Input Register (CRCDIR): CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written. The result is obtained in CRCDOR. CRC Data Output Register (CRCDOR): CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to which CRC operation is to be performed, the CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1, respectively, the lower byte of this register contains the result. Rev. 3.00 Jan 25, 2006 page 468 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11.3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An example in which a CRC code for hexadecimal data H'F0 is generated using the X16 + X12 + X5 + 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below. 1. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 0 11 CRCDIR 2. Write H'F0 to CRCDIR 7 1 1 1 1 0 0 0 00 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0 CRC code generation 0 0 1 1 1 11 11 3. Read from CRCDOR CRC code = H'F78F 4. Serial transmission (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Output Figure 16.46 LSB-First Data Transmission 1. Write H'87 to CRCCR 7 CRCCR 1 0 0 0 0 1 0 11 CRCDIR 2. Write H'F0 to CRCDIR 7 1 1 1 1 0 0 0 0 0 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 CRCDOR clearing 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1 CRC code generation 0 1 1 1 1 1 1 1 1 3. Read from CRCDOR CRC code = H'EF1F 4. Serial transmission (MSB first) Data 7 Output 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1 Figure 16.47 MSB-First Data Transmission Rev. 3.00 Jan 25, 2006 page 469 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 1. Serial reception (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Input 2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 1 0 1 3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0 CRC code generation 0 0 1 1 1 1 1 1 1 4. Write H'8F to CRCDIR 7 CRCDIR 1 0 0 0 1 1 1 0 1 5. Write H'F7 to CRCDIR 7 CRCDIR 1 1 1 1 0 1 1 0 1 CRC code generation 7 CRCDORH CRCDORL 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0 CRC code generation 0 0 0 0 0 0 0 0 0 6. Read from CRCDOR CRC code = H'0000 No error Figure 16.48 LSB-First Data Reception Rev. 3.00 Jan 25, 2006 page 470 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 1. Serial reception (MSB first) Data 7 Input 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1 2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 1 1 0 1 3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0 CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1 CRC code generation 0 1 1 1 1 1 1 1 1 4. Write H'EF to CRCDIR 7 CRCDIR 1 1 1 0 1 1 1 0 1 5. Write H'1F to CRCDIR 7 CRCDIR 0 0 0 1 1 1 1 0 1 CRC code generation 7 CRCDORH CRCDORL 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0 CRC code generation 0 0 0 0 0 0 0 0 0 6. Read from CRCDOR CRC code = H'0000 No error Figure 16.49 MSB-First Data Reception Rev. 3.00 Jan 25, 2006 page 471 of 872 REJ09B0286-0300 Section 16 Serial Communication Interface (SCI, IrDA, and CRC) 16.11.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission. 1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) (2) (3) (4). 7 0 CRCDIR (1) (2) (3) (4) CRC code generation 0 (5) (6) 7 CRCDORH CRCDORL 2. Transmission data (i) LSB-first transmission CRC code 7 (5) (ii) MSB-first transmission 07 (6) 07 (4) 07 (3) 07 (2) 07 (1) 0 Output CRC code 7 Output (1) 07 (2) 07 (3) 07 (4) 07 (5) 07 (6) 0 Figure 16.50 LSB-First and MSB-First Transmit Data Rev. 3.00 Jan 25, 2006 page 472 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Section 17 I2C Bus Interface (IIC) This LSI has an I2C bus interface (IIC) of two channels. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. Note however that the register configuration that controls the I2C bus differs partly from the Philips configuration. 17.1 Features * Selection of I2C bus format or clocked synchronous serial format I2C bus format: Addressing format with acknowledge bit, for master/slave operation Clocked synchronous serial format: Non-addressing format without acknowledge bit, for master operation only * For I2C bus format, two ways of setting slave address * For I2C bus format, start and stop conditions generated automatically in master mode * For I2C bus format, selection of acknowledge output levels when receiving * For I2C bus format, automatic loading of acknowledge bit when transmitting * For I2C bus format, wait bit function in master mode A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * For I2C bus format, wait function is available A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I2C bus format occurs, when ICDR data is transferred, or during a wait state) Address match: When any slave address matches or the general call address is received in slave receive mode with I2C bus format (including address reception after loss of master arbitration) Arbitration loss Start condition detection (in master mode) Stop condition detection (in slave mode) * Selection of 16 internal clocks (in master mode) IFIIC50A_000020020300 Rev. 3.00 Jan 25, 2006 page 473 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 * Direct bus drive Two pins, SCL and SDA, function as NMOS open-drain outputs when the bus drive function is selected. * Operation using the operation reservation adapter Figure 17.1 shows a block diagram of the I2C bus interface. Figure 17.2 shows an example of I/O pin connections to external circuits. I/O pins are NMOS open drain, and 5.8 V or less should be applied as the power supply voltage. Rev. 3.00 Jan 25, 2006 page 474 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Timeout decision circuit Adapter ICCNT ICCRX Command control ICCMD ICSRA ICSRB ICSRC SCL Noise canceler Clock control ICMR Bus state decision circuit Arbitration decision circuit ICSR ICDRX(W)*1 ICDRT ICDRS ICDRX(R)*2 SDA Output data conrol circuit ICDRR Noise canceler Address comparator SAR, SARX Notes: 1. ICDRX write = ICDRT write 2. ICDRX read = ICDRR read Legend: ICCR : ICMR : ICSR : ICDR : SAR : SARX : ICCNT : ICCRX : ICCMD : I2C bus control register I2C bus mode register I2C bus status register I2C bus data register Slave address register Second slave address register IIC operation reservation adapter count register IIC operation reservation adapter control register IIC operation reservation adapter command register Interrupt generator ICSRA : ICSRB : ICSRC : ICDRX : ICDRT : ICDRS : ICDRR : PS : IIC operation reservation adapter status register A IIC operation reservation adapter status register B IIC operation reservation adapter status register C IIC operation reservation adapter data register IIC data transmit buffer IIC data shift register IIC data receive buffer Prescaler Figure 17.1 Block Diagram of I2C Bus Interface Rev. 3.00 Jan 25, 2006 page 475 of 872 REJ09B0286-0300 Internal data bus Interrupt request PS ICCR Section 17 I C Bus Interface (IIC) 2 VCC VDD VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) This LSI SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 17.2 I2C Bus Interface Connections (Example: This LSI as Master) 17.2 Input/Output Pins Table 17.1 summarizes the input/output pins used by the I2C bus interface. Table 17.1 Pin Configuration Channel 0 1 Symbol SCL0 SDA0 SCL1 SDA1 Input/Output Input/Output Input/Output Input/Output Input/Output Function Clock input/output pin of channel 0 Data input/output pin of channel 0 Clock input/output pin of channel 1 Data input/output pin of channel 1 17.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Rev. 3.00 Jan 25, 2006 page 476 of 872 REJ09B0286-0300 SCL SDA Section 17 I C Bus Interface (IIC) 2 * I2C bus data register (ICDR) * Slave address register (SAR) * Second slave address register (SARX) * I2C bus mode register (ICMR) * I2C bus control register (ICCR) * I2C bus status register (ICSR) * IIC operation reservation adapter control register (ICCRX) * IIC operation reservation adapter status register A (ICSRA) * IIC operation reservation adapter status register B (ICSRB) * IIC operation reservation adapter status register C (ICSRC) * IIC operation reservation adapter data register (ICDRX) * IIC data shift register (ICDRS) * IIC operation reservation adapter count register (ICCNT) * IIC operation reservation adapter command register (ICCMD) 17.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. When ICDRE is 1 and the transmit buffer is empty, ICDRE shows that the next transmit data can be written from the CPU. When ICDRF is 1, it shows that valid receive data is stored in the receive buffer. If I2C is in transmit mode and the next transmit data is in the transmit buffer (the ICDRE flag is 0) after successful transmission/reception of one frame of data using the shift register, data is transferred automatically from the transmit buffer to the shift register. If I2C is in receive mode and no previous data remains in the receive buffer (the ICDRF flag is 0), data is transferred automatically from the shift register to the receive buffer. Note however that no data is transferred from the transmit buffer to the shift register in receive mode, and from the shift register to the receive buffer in transmit mode. If ICDR is read from in transmit mode, data in the receive buffer can be read but data in the shift register cannot. Always set I2C to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. Rev. 3.00 Jan 25, 2006 page 477 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. The ICDRE and ICDRF flags are set and cleared under the conditions shown below. Setting the ICDRE and ICDRF flags affects the status of the interrupt flags. Bit -- Bit Name ICDRE Initial Value R/W -- -- Description Transmit Data Register Empty [Setting conditions] * When satisfaction of a start condition is detected in 2 the bus line state with the I C bus format or serial format selected When data is transferred from the transmit buffer to the shift register (Data transfer from the transmit buffer to the shift register if the shift register is empty when ICDRE = 0 in transmit mode) (Do not write to ICDR in receive mode because the ICDRE flag value is invalid) [Clearing conditions] * * When transmit data is written in ICDR (transmit buffer) in transmit mode When satisfaction of a stop condition is detected in 2 the bus line state with the I C bus format or serial format selected If transmit data is written to ICDR (transmit buffer) in transmit mode when ICDR does not contain data to be transmitted, ICDRE is cleared to 0. However, since data is transferred from the transmit buffer to the shift register immediately, ICDRE is set to 1 again. * Internal state initialization (Writing 0 to the TRS bit in ICCR during transfer is valid after reception of a frame containing an acknowledge bit) * Rev. 3.00 Jan 25, 2006 page 478 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit -- Bit Name ICDRF Initial Value R/W -- -- Description Receive Data Register Full [Setting condition] * When data is transferred from the shift register to the receive buffer (Data transfer from the shift register to the receive buffer if there is receive data in the shift register when ICDRF = 0 in receive mode) (Data is not transferred from the shift register to the receive buffer in transmit mode. To read data in the shift register, read ICDR in receive mode.) [Clearing conditions] * When receive data in ICDR (receive buffer) is read in receive mode If receive data is read from ICDR (receive buffer) in receive mode when the shift register contains the next receive data, ICDRF is cleared to 0. However, since data is transferred from the shift register to the receive buffer immediately, ICDRF is set to 1 again. * Internal state initialization 2 Rev. 3.00 Jan 25, 2006 page 479 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. When the LSI is in slave mode with the addressing format selected, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Format Select Selects the communication format together with the FSX bit in SARX. For details, see table 17.2. This bit should be cleared to 0 when general call address recognition is performed. Description Slave Address 6 to 0 Set a slave address. Rev. 3.00 Jan 25, 2006 page 480 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the second slave address. When the LSI is in slave mode with the I2C bus format selected, if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value R/W 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR. For details, see table 17.2. Description Second Slave Address 6 to 0 Set the second slave address. Table 17.2 Communication Format SAR FS 0 0 1 1 SARX FSX 0 1 0 1 Communication Format SAR and SARX are used as the slave addresses with the I C bus format. Only SAR is used as the slave address with the I C bus format. Only SARX is used as the slave address with the I C bus format. Clocked synchronous serial format (SAR and SARX are invalid) 2 2 2 Rev. 3.00 Jan 25, 2006 page 481 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value R/W 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, see section 17.5.6, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Serial Clock Select 2 to 0 These bits are valid only in master mode. These bits select the required transfer rate, together with bit IICX1 (channel 1) or IICX0 (channel 0) in STCR. See table 17.3. 2 2 Rev. 3.00 Jan 25, 2006 page 482 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred 2 next. With the I C bus format, the data is transferred with one additional acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than B'000, the setting should be made while the SCL line is low. The value returns to B'000 when a start condition is detected or when data transfer including the acknowledge bit ends. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 3.00 Jan 25, 2006 page 483 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.3 I2C Transfer Rate STCR Bit 6/5 IICX1/ IICX0 0 Bit 5 CKS2 0 ICMR Bit 4 CKS1 0 Bit 3 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 =5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz =8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 12 MHz 429 kHz* 300 kHz 250 kHz 188 kHz 150 kHz 120 kHz 107 kHz 93.8 kHz 212 kHz 150 kHz 125 kHz 93.8 kHz 75.0 kHz 60.0 kHz 53.5 kHz 46.9 kHz = 16 MHz 517 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz = 24 MHz 857 kHz* 600 kHz* 500 kHz* 375 kHz 300 kHz 240 kHz 214 kHz 188 kHz 429 kHz 300 kHz 250 kHz 188 kHz 150 kHz 120 kHz 107 kHz 93.8 kHz Note: * Outside the I C bus interface specifications (standard mode: max. 100 kHz; high-speed mode: max. 400 kHz) 2 Rev. 3.00 Jan 25, 2006 page 484 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.5 I2C Bus Control Register (ICCR) ICCR consists of the control bits and interrupt request flags of the I2C bus interface. Bit 7 Bit Name ICE Initial Value R/W 0 R/W Description I C Bus Interface Enable 0: This module is stopped and disconnected from the SCL and SDA pins. SAR and SARX can be accessed. 1: This module can perform transfer and reception, they 2 are connected to the SCL and SDA pins, and the I C bus can be driven. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I C Bus Interface Interrupt Enable When this bit is set to 1, IRIC interrupts are enabled. 2 2 Rev. 3.00 Jan 25, 2006 page 485 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 5 4 Bit Name MST TRS Initial Value R/W 0 0 R/W R/W Description Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus conflict in master mode of the I C bus format. In slave receive mode, the R/W bit in the first frame immediately after the start condition automatically sets these bits in receive mode or transmit mode by hardware. The settings can be made again for the bits that were set/cleared by hardware, by reading these bits. When the TRS bit is intended to change during a transfer, the bit will not be switched until data transfer ends. [MST clearing conditions] 1. When 0 is written by software 2 2. When lost in bus conflict in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 2 3. When lost in bus conflict in I C bus format master mode [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing condition 3) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing condition 3) 3. When 1 is received for the R/W bit value of the first 2 frame in I C bus format slave mode 2 Rev. 3.00 Jan 25, 2006 page 486 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 3 Bit Name ACKE Initial Value R/W 0 R/W Description Acknowledge Bit Decision Selection 0: The value of the received acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. 2 0 BBSY SCP 0 1 R/W W Bus Busy Start Condition/Stop Condition Prohibit In master mode: Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: Writing to the BBSY flag is disabled. [BBSY setting condition] * When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. When the SDA level changes from low to high under the condition of SCL = high, assuming that the start condition has been issued. 2 2 [BBSY clearing condition] * To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored. 2 Rev. 3.00 Jan 25, 2006 page 487 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 1 Bit Name IRIC Initial Value R/W 0 Description Indicates that the IIC module has issued an interrupt request to the CPU. This flag is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. For details, see section 17.5.6, IRIC Setting Timing and SCL Control. The conditions under which this flag is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode: * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) * When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) * At the end of data transfer (rise of the 9th transmit/receive clock without no waits) * When a slave address is received after bus arbitration is lost (first frame after start condition) * If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 * When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 I C bus format slave mode: * When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) * When the general call address is detected (when 0 is received as the R/W bit and the ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) * If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 * When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) when the STOPIM bit is 0 2 2 2 2 R/(W)* I C Bus Interface Interrupt Request Flag Rev. 3.00 Jan 25, 2006 page 488 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description Clocked synchronous serial format mode: * At the end of data transfer (rise of the 8th transmit/receive clock with serial format selected) * When a start condition is detected with serial format selected When the ICDRE or ICDRF flag is set to 1 in any operating mode: * When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) * When data is transferred among the ICDR register and buffer (when data is transferred from the transmit buffer to the shift register in transmit mode and the ICDRE flag is set to 1, or when data is transferred from the shift register to the receive buffer in receive mode and the ICDRF flag is set to 1) [Clearing conditions] * * When 0 is written in IRIC after reading IRIC = 1 When ICDR is read from or written to by the DTC (This may not function as a clearing condition depending on the situation. For details, see the description of the DTC operation given below.) 2 Note: * Only 0 can be written, to clear the flag. When the DTC is used, the IRIC flag is cleared automatically and transfer can be performed continuously without CPU intervention. When, with the I2C bus format selected, the IRIC flag is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set the IRIC flag to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 17.4 shows the relationship between the flags and the transfer states. Rev. 3.00 Jan 25, 2006 page 489 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.4 Flags and Transfer States Operating Mode MST Master mode 1 1 1 1 1 1 1 1 1 TRS 1 1 1 1 1 1 1 1 BBSY ESTP STOP IRTR 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 AASX AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAS 0 0 0 0 0 0 0 0 0 ADZ 0 0 0 0 0 0 0 0 0 ACKB ICDRE ICDRF 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 State Idle state (flag clearing required) Start condition detected Wait state Transmission end (when ACKB = 1 received) Transmission end (when previous state is ICDRE = 0) Write to ICDR in above state Transmission end (when previous state is ICDRE = 1) Write to ICDR in above state or after start condition is detected Data transfer from transmit buffer to shift register (automatic) in above state Reception end (when previous state is ICDRF = 0) Write to ICDR in above state Reception end (when previous state is ICDRF = 1) Write to ICDR in above state Data transfer from shift register to receive buffer (automatic) in above state Arbitration lost Stop condition detected Idle state (flag clearing required) Start condition detected SAR match by first frame (SARX SAR) General call address match by first frame (SARX H'00) SARX match by first frame (SAR SARX) 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Slave mode 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1/0*1 1 0 1 1/0*1 1 Rev. 3.00 Jan 25, 2006 page 490 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Operating Mode MST Slave mode 0 2 TRS 1 BBSY ESTP STOP IRTR 1 0 0 AASX AL 0 0 AAS 0 0 ADZ 0 ACKB ICDRE ICDRF 1 1 State Transmission end (when ACKB = 1 received) Transmission end (when previous state is ICDRE = 0) Write to ICDR in above state Transmission end (when previous state is ICDRE = 1) Write to ICDR in above state or after start condition is detected Data transfer from transmit buffer to shift register (automatic) in above state Reception end (when previous state is ICDRF = 0) Write to ICDR in above state Reception end (when previous state is ICDRF = 1) Write to ICDR in above state Data transfer from shift register to receive buffer (automatic) in above state Stop condition detected 0 1 1 0 0 1/0*2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1/0*2 0 0 0 0 1 0 0 1 0 0 1/0*2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1/0*2 0 0 1/0* 3 0/1*3 0 Legend: 0: Retains 0 1: Retains 1 : Retains the previous state 0: Cleared to 0 1: Set to 1 Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP = 1, STOP is 0, or when STOP = 1, ESTP is 0. Rev. 3.00 Jan 25, 2006 page 491 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see table 17.4. Bit 7 Bit Name ESTP Initial Value 0 R/W Description This bit is valid in I C bus format slave mode. [Setting condition] * * 6 STOP 0 When a stop condition is detected during frame transfer. When 0 is written in ESTP after reading ESTP = 1 [Clearing conditions] * When the IRIC flag in ICCR is cleared to 0 * Normal Stop Condition Detection Flag R/(W) This bit is valid in I C bus format slave mode. [Setting condition] * * * 5 IRTR 0 When a stop condition is detected during frame transfer. When 0 is written in STOP after reading STOP = 1 [Clearing conditions] When the IRIC flag in ICCR is cleared to 0 * I2C Bus Interface Continuous Transfer Interrupt Request Flag R/(W) Indicates that the IIC module has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting condition in I C bus format slave mode] * When the ICDRE or ICDRF flag in ICXR is set to 1 when AASX = 1 2 2 2 2 R/(W)* Error Stop Condition Detection Flag [Setting condition in I C bus format modes other than slave mode] * * * When the ICDRE or ICDRF flag in ICXR is set to 1 When 0 is written in IRTR after reading IRTR = 1 When the IRIC flag in ICCR is cleared to 0 (while ICE = 1 or ICXE = 1) [Clearing conditions] Rev. 3.00 Jan 25, 2006 page 492 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit Name AASX Initial Value 0 2 Bit 4 R/W Description In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] * When the second slave address is detected in slave receive mode and FSX = 0 in SARX When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode 2 R/(W)* Second Slave Address Recognition Flag [Clearing conditions] * * * 3 AL 0 R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL = 0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1 2 When ALSL = 1 * * [Clearing conditions] * * Rev. 3.00 Jan 25, 2006 page 493 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit Name AAS Initial Value 0 2 Bit 2 R/W Description In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] * When the slave address or general call address is detected in slave receive mode and FS = 0 in SAR When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode 2 2 R/(W)* Slave Address Recognition Flag [Clearing conditions] * * * 1 ADZ 0 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] * When the general call address is detected in slave receive mode and FS = 0 in SAR or FSX = 0 in SARX When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode [Clearing conditions] * * * If a general call address is detected while FS = 1 and FSX = 0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1). Rev. 3.00 Jan 25, 2006 page 494 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit Name ACKB Initial Value 0 2 Bit 0 R/W R/W Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] * When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode When 0 is received as the acknowledge bit when ACKE = 1 in transmit mode When 0 is written to the ACKE bit [Clearing conditions] * * Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If a flag in ICSR is written using bit manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write 0 in the ACKE bit to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Jan 25, 2006 page 495 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.7 IIC Operation Reservation Adapter Control Register (ICCRX) ICCRX controls the operation of the IIC operation reservation adapter. Bit 7 Bit Name ICXE Initial Value 0 R/W R/W Description IIC Operation Reservation Adapter Enable Selects whether to control the conventional IIC module or enable and control the IIC operation reservation adapter. 0: Directly controls the conventional IIC module; disables the IIC operation reservation adapter 1: Enables the IIC operation reservation adapter; restricts direct control of the conventional IIC module When this bit is set to 1, the SCL and SDA pins can 2 drive the I C bus, similar to when the ICE bit in ICCR is set to 1. 6 CRIC 0 R/W Command Request Interrupt Enable Enables or disables the IIC operation reservation command execution end/next command write request interrupt. 0: Disables the command write request interrupt 1: Enables the command write request interrupt 5 MRIC 0 R/W Master Mode Transmission/Reception Interrupt Enable 0: Disables the master mode transmission/reception interrupt (MRREQ, MTREQ) 1: Enables the master mode transmission/reception interrupt (MRREQ, MTREQ) 4 SRIC 0 R/W Slave Mode Transmission/Reception Interrupt Enable 0: Disables the slave mode transmission/reception interrupt (SRREQ, STREQ) 1: Enables the slave mode transmission/reception interrupt (SRREQ, STREQ) 3 BBSYX 0 R Bus Busy X 0: Bus is released 1: Bus is occupied 2 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 496 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 1 Bit Name AASHIT Initial Value 0 R/W R Description Slave Address Match 0: In master mode or slave address does not match 1: Slave address matches 0 ACKBX 0 R Acknowledge Bit Transmission Reserve 0: Reserves transmission of acknowledge bit 0 1: Reserves transmission of acknowledge bit 1 3 2 1 0 CLR3 CLR2 CLR1 CLR0 -- -- -- -- W W W W Clear 3 to 0 Writing B'0101 to these bits with an MOV instruction initializes the internal latch circuit and state machine of the conventional IIC module and the IIC operation reservation adapter. The appropriate control bits of the conventional IIC module and the IIC operation reservation adapter must be initialized so as to deactivate the IIC module. When bits 7 to 4 in this register are set/cleared using a bit manipulation instruction, the contents in BBSYX and AASHIT are written to the CLR3 to CLR0 bits by read/modify/write operation. However, since bit 2 is always read as 0, clearing operation cannot be executed. 2 17.3.8 IIC Operation Reservation Adapter Status Register A (ICSRA) ICSRA monitors the operating status of the IIC module. Bit 7 6 5 4 Bit Name SDAO SCLO SDAI SCLI Initial Value 1 1 -- -- R/W R R R R Description SDA Output Value Monitors the output value from the SDA pin. SCL Output Value Monitors the output value from the SCL pin. SDA Input Level Monitors the input level to the SDA pin. SCL Input Level Monitors the input level to the SCL pin. Rev. 3.00 Jan 25, 2006 page 497 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 3 2 Bit Name MSTX TRSX Initial Value 0 0 R/W R R Description Master/Slave State X Transmit/Receive State X 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode These bits are automatically set by an operation reservation command. 1 WAITX 0 R Wait Insertion Bit X This bit is valid only in master mode with the I C bus format. This bit is automatically set by an operation reservation command. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit, a wait state begins (with SCL at the low level). 0 ACKXE 0 R Acknowledge Bit Decision Selection X 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKBX bit in ICCRX, which is always 0. 1: If the acknowledge bit is 1, continuous transfer is halted. This bit is automatically set by an operation reservation command. 2 2 Rev. 3.00 Jan 25, 2006 page 498 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.9 IIC Operation Reservation Adapter Status Register B (ICSRB) ICSRB monitors operating state transitions and error status of the IIC operation reservation adapter. Bit 7 Bit Name CREQ Initial Value 0 R/W Description R/(W)* Operation Reservation Command Write Request Interrupt Flag 0: No command write request is generated 1: Command write request is generated [Clearing conditions] * * When ICCMD is read from or written to When 0 is written to CREQ after reading CREQ = 1 Generation Timing Rise of 9th clock Rise of 9th clock [Setting condition] CREQ Generation Source Automatic command transition after slave address match ACKB = 1 received (NACK = 1) when the acknowledge bit is enabled in transmit mode Stop condition detected (STOPIMX = 0 while STOP = 1 or ABRT = 1) Arbitration lost (ALST = 1) Timeover generated (TOVR = 1) Undefined command is written Stop condition detected Always Always Always 6 CERR 0 R/(W)* Operation Reservation Command Error Flag 0: No command error is generated 1: Command error is generated [Clearing conditions] * * * * * * When ICCMD is written to When 0 is written to CERR after reading CERR = 1 When arbitration loss is generated When a timeover is generated When a start/stop condition is detected during transfer When NAK is received [Setting conditions] Rev. 3.00 Jan 25, 2006 page 499 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 5 Bit Name STOP Initial Value 0 R/W Description 0: No stop condition is detected 1: Stop condition is detected [Clearing conditions] * * * 4 ABRT 0 R When ICCMD is written to When 0 is written to STOP after reading STOP = 1 When a stop condition is detected 2 R/(W)* Stop Condition Detection [Setting condition] Abort 0: Normal end 1: Abort [Clearing conditions] * * * 3 ALST 0 When ICCMD is written to When 0 is written to ABRT after reading ABRT = 1 When a start/stop condition is detected during data transfer [Setting condition] R/(W)* Arbitration Lost 0: Normal operation 1: Arbitration loss is generated [Clearing conditions] * * * When ICCMD is written to When 0 is written to ALST after reading ALST = 1 When arbitration loss is generated in master mode (1) Internal SDA disagrees with the SDA pin level at rise of SCL (2) Internal SDA is high when the start condition is detected [Setting condition] Rev. 3.00 Jan 25, 2006 page 500 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 2 Bit Name DERR Initial Value 0 R/W Description 0: Normal operation 1: Transmit data disagree [Clearing conditions] * * * When ICCMD is written to When 0 is written to DERR after reading DERR = 1 The DERR bit is set to 1 when a stop condition is detected in slave transmit mode. When the STOP and DERR bits are set to 1 simultaneously, the DERR value is ignored because this is normal operation and not an error. When internal transmit data disagrees with the SDA pin level during transmission 2 R/(W)* Transmit Data Disagree Error [Setting condition] * 1 TOVR 0 R/(W)* Timeover 0: Normal operation 1: A timeover is generated [Clearing conditions] * * When ICCMD is written to When 0 is written to TOVR after reading TOVR = 1 [Setting condition] 0 NACK 0 * When a timeover is generated * NACK Receive R/(W) 0: Normal operation 1: NACK is received [Clearing conditions] * * * Note: * When ICCMD is written to When 0 is written to NACK after reading NACK = 1 When NACK is received after data transmission is completed (ACKBX = 1 received) [Setting condition] Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 501 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.10 IIC Operation Reservation Adapter Status Register C (ICSRC) ICSRC monitors the transmission/reception status of the IIC operation reservation adapter. See figure 17.3 for details on the TDRE, SDRF, and RDRF bits. Bit 7 Bit Name MTREQ Initial Value 0 R/W Description 0: No transmit data write request is generated in master mode 1: A transmit data write request is generated and an interrupt is requested in master mode [Clearing conditions] * * * When ICDRX is written to When ICCMD is written to When 0 is written to MTREQ after reading MTREQ = 1 When data transmission is completed in master mode 1 R/(W)* Master Mode Transmit Data Write Request Interrupt Flag [Setting condition] * 6 MRREQ 0 1 R/(W)* Master Mode Receive Data Read Request Interrupt Flag 0: No receive data read request is generated in master mode 1: A receive data read request is generated and an interrupt is requested in master mode [Clearing conditions] * * * When ICDRX is written to When ICCMD is written to When 0 is written to MRREQ after reading MRREQ = 1 When data reception is completed in master mode [Setting condition] * Rev. 3.00 Jan 25, 2006 page 502 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 5 Bit Name STREQ Initial Value 0 R/W Description 0: No transmit data write request is generated in slave mode 1: A transmit data write request is generated and an interrupt is requested in slave mode [Clearing conditions] * * * When ICDRX is written to When ICCMD is written to When 0 is written to STREQ after reading STREQ = 1 2 1 R/(W)* Slave Mode Transmit Data Write Request Interrupt Flag: [Setting condition] 4 SRREQ 0 * When data transmission is completed in slave mode *1 Slave Mode Receive Data Read Request Interrupt Flag R/(W) 0: No receive data read request is generated in slave mode 1: A receive data read request is generated and an interrupt is requested in slave mode [Clearing conditions] * * * When ICDRX is written to When ICCMD is written to When 0 is written to SRREQ after reading SRREQ = 1 When data reception is completed in slave mode [Setting condition] * 3 MASX 0 R Master Mode Address Select X 0: DTC cannot be activated Address disagrees in slave mode or AAS and ADZ addresses agree 1: DTC can be activated In master mode, or AASX address agrees in slave mode Rev. 3.00 Jan 25, 2006 page 503 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 2 Bit Name TDRE Initial Value 0 R/W R Description Transmit Data Register Empty 0: Transmit buffer (ICDRT) contains transmit data 1: Transmit buffer (ICDRT) contains no transmit data; write to ICDRT is possible [Setting conditions] * * * When start condition is detected (when ICDRX is not 2 written to before the start condition is detected)* When transfer of first frame (address + R/W) ends 2 (rise of 9th clock)* When transmission of second or subsequent frames starts (fall of 1st clock) (except for when transferring 2 the last byte in DTC transfer)* When ICDRX is written to* 2 2 [Clearing conditions] * * * When ACKB = 1 is received When stop condition is detected This bit is enabled during transmission by the IIC operation reservation adapter. For transmission/reception with the conventional method, see the description of the ICDRE and ICDRF flags in ICDR. Rev. 3.00 Jan 25, 2006 page 504 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 1 Bit Name SDRF Initial Value 0 R/W R Description Shift Data Register Full 0: Shift register (ICDRS) contains no receive data remaining to be read or data remaining to be transmitted 1: Shift register (ICDRS) contains receive data remaining to be read or data remaining to be transmitted [Setting condition in transmit mode] * When ICDRX is written to, or when data transmission ends (rise of 9th clock) with the next transmit data set 2 in ICDRT (TDRE = 0)* When data transmission ends (rise of 9th clock) with 2 the next transmit data not set in ICDRT (TDRE = 1)* When stop condition is detected When receive mode is entered Arbitration lost When data reception ends (fall of 8th clock) with 3 RDRF = 1* When ICDRX is read from When start condition is detected When transmit mode is entered 2 [Clearing conditions in transmit mode] * * * * * [Setting condition in receive mode] [Clearing conditions in receive mode] * * * This bit is enabled during transmission or reception by the IIC operation reservation adapter. Rev. 3.00 Jan 25, 2006 page 505 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 0 Bit Name RDRF Initial Value 0 R/W R Description Receive Data Register Full 0: Receive buffer (ICDRR) contains no receive data 1: Receive buffer (ICDRR) contains receive data; read from ICDRR is possible [Setting conditions] * * * When transmission of first frame (address + R/W = 1) in master mode ends (rise of 9th clock) When reception of second or subsequent frames 3 ends (fall of 8th clock)* When ICDRX is read from with receive data in the shift register (SDRF = 1) in receive mode When ICDRX is read from with no receive data in the shift register (SDRF = 0) in receive mode When start condition is detected 2 [Clearing conditions] * * This bit is enabled during reception by the IIC operation reservation adapter. Notes: 1. Only 0 can be written to clear the flag. 2. Address disagree in master mode or slave mode transmission. 3. Address (including general call address) match in master mode or slave mode reception. Rev. 3.00 Jan 25, 2006 page 506 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 TDRE = 0 SDRF = 0 Start condition detected Stop condition detected Rise of 9th clock TDRE = 1 SDRF = 0 Rise of 9th clock in first frame Write to ICDRX TDRE = 1 SDRF = 1 Fall of 1st clock TDRE = 0 SDRF = 1 Write to ICDRX Fall of 1st clock TDRE = 0 SDRF = 1 (a) Transmit mode Rise of 9th clock Start condition detected SDRE = 0 RDRF = 0 Stop condition detected Fall of 8th clock (Rise of 9th clock in first frame in master mode) Read from ICDRX SDRE = 0 RDRF = 1 Fall of 8th clock Stop condition detected Read from ICDRX SDRE = 1 RDRF = 1 (b) Receive mode Figure 17.3 State Transitions of TDRE, SDRF, and RDRF Bits 17.3.11 IIC Operation Reservation Adapter Data Register (ICDRX) ICDRX is an 8-bit register identical to ICDR. When this register is accessed for read, the contents in the receive buffer (ICDRR) are read out; and when this register is accessed for write, the write data is written to the transmit buffer (ICDRT). However, the IIC module operates in the way defined by the operation reservation adapter when this register is read from or written to. When the ICXE bit in ICCRX is set to 1, accesses to ICDR are invalid. The initial value of ICDRX is undefined. Rev. 3.00 Jan 25, 2006 page 507 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.12 IIC Data Shift Register (ICDRS) ICDRS is an 8-bit read-only register, which is ICDR's readable shift register (ICDRS). During transfer operation, the ICDRS values change in accordance with the frame bit count. The ICDRS values can be associated with the BBC3 to BBC0 bits in ICCNT by simultaneously reading from ICDRS and ICCNT in words. The ICDRS values read when the BBC3 to BBC0 bits are set to B'1111 match the receive data. When receive data is to be read with the SCL clock stopped while the ACK/NACK bit is to be selected after reading receive data, read from ICDRS using the above method. 17.3.13 IIC Operation Reservation Adapter Count Register (ICCNT) ICCNT controls monitoring of timeout-related operations of the IIC operation reservation adapter. Timeout Occurrence Condition: In transmission/reception operation using the IIC operation reservation adapter, a timeout occurs when the interrupt flag is not set and the SCL pin has not changed for a period exceeding the time specified by the CNTS1 and CNTS0 bits. When a timeout occurs, the TOVR and CERR flags in ICSRB are set to 1 and a command request interrupt (CREQ) request occurs. Timeout Counter Clear Conditions: * At a reset * When ICXE = 0 in ICCRX (IIC operation reservation adapter disabled) * When CNTE = 0 (timeout counter stopped) * When BBSYX = 0 in ICCRX (bus released state) * When a bit among CREQ in ICSRB, and MTREQ, MRREQ, STREQ, and SRREQ in ICSRC is set to 1 (interrupt is requested) * When a rising edge or falling edge is input to the SCL pin Rev. 3.00 Jan 25, 2006 page 508 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Bit 7 Bit Name CNTE Initial Value 0 R/W R/W Description Timeout Counter Enable Starts or stops the timeout counter. 0: Stops the timeout counter and clears the internal counter 1: Operates the timeout counter 6 STOPIMX 0 R/W Stop Condition Interrupt Source Mask X Selects whether to enable CREQ interrupt requests by stop conditions. 0: CREQ interrupt requests by stop conditions are enabled 1: CREQ interrupt requests by stop conditions are disabled 5 4 CNTS1 CNTS0 0 0 R/W R/W Counter Select These bits specify the number of clock cycles for the timeout counter. The clock is selected by the IICX1 and IICX0 bits in STCR and the CKS2 to CKS0 bits in ICMR. 00: 32 clock cycles 01: 34 clock cycles 10: 128 clock cycles 11: 256 clock cycles 3 2 1 0 BBC3 BBC2 BBC1 BBC0 1 1 1 1 R R R R Frame Bit Count These bits count the frame bit at each rising edge of SCL. These bits are cleared to B'0000 at the first rising edge, and are incremented by 1 at each rising edge. After being incremented to B'0111 at the eighth rising edge, these bits are initialized to B'1111 at the next rising edge (for acknowledge). 2 Rev. 3.00 Jan 25, 2006 page 509 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.3.14 IIC Operation Reservation Adapter Command Register (ICCMD) ICCMD is an 8-bit readable/writable register that specifies an IIC operation reservation adapter command. When the reserved operation is completed, ICCMD may be automatically modified to contain the next related command. For details on commands and operations, see section 17.4, IIC Operation Reservation Adapter. When the ICXE bit in ICCRX is set to 1, ICCMD is automatically set to H'A0. When the ICXE bit in ICCRX is cleared to 0, ICCMD is cleared to H'00. If a value not defined as an operation reservation command is written to ICCMD when the ICXE bit is set to 1, the CERR bit in ICSRB is set to 1 and a CREQ interrupt request is generated. In this case, ICCMD is reset to H'A0. When the ICXE bit is cleared to 0, no value can be written to ICCMD. 17.4 17.4.1 IIC Operation Reservation Adapter Restrictions on Accessing IIC Registers There are restrictions when accessing registers other than those related to the IIC operation reservation adapter when the IIC operation reservation adapter is enabled (ICXE = 1 in ICCRX), as shown in table 17.5. Rev. 3.00 Jan 25, 2006 page 510 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.5 Restrictions on Accessing IIC Registers Register ICDR Bit 7 to 0 Bit Name -- R/W R/W Description Writing is disabled. Reading/writing to this register does not initiate any data transfer. Writing has no affect on the bits. Write the slave address. Select the I C bus format. Write the second slave address as required. Select the I C bus format. Select MSB-first. The value written to this bit is ignored because the function of this bit is replaced by ICCMD. The function of this bit can be monitored by the WAITX bit in ICSRA. Select the transfer rate. Set to B'000 (9 bits). -- Even when set to 1, the conventional interrupt is ignored. The values written to these bits are ignored because the functions of these bits are replaced by ICCMD. The functions of these bits can be monitored by the MSTX, TRSX, and ACKXE bits in ICSRA. Writing B'10 or B'00 is ignored. -- Writing B'10 or B'00 is ignored. -- 2 2 SAR SARX ICMR 7 to 1 0 7 to 1 0 7 6 SVA6 to SVA0 FS SVAX6 to SVAX0 FSX MLS WAIT R/W R/W R/W R/W R/W R/W 5 to 3 2 to 0 ICCR 7 6 5 4 3 2 1 0 ICSR 7 6 5 4 3 2 1 0 CKS2 to CKS0 BC2 to BC0 ICE IEIC MST TRS ACKE BBSY IRIC SCP ESTP STOP IRTR AASX AL AAS ADZ ACKB R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/W The value written to this bit is ignored because the function of this bit when written to is replaced by the ACKXB bit in ICCRX. Rev. 3.00 Jan 25, 2006 page 511 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.4.2 Operation Reservation Commands Table 17.6 lists the operation reservation commands that can be set in ICCMD. If values other than H'A0 to H'AF, and H'C0 to H'CF are set, H'A0 is automatically set as the command. The operation reservation commands reserve various operations such as start condition issuance, stop condition issuance, data transmission (including acknowledge (ACK)/non-acknowledge (NAK) judgment), and data reception (including ACK/NAK transmission and stop condition issuance). Since 16 bits can be simultaneously written to ICCMD and ICDRX, a series of required operations can be written as the transfer data (data + command) for data transmission. Table 17.7 shows the changes in interrupt flag status and automatic command transition when the operation reservation command is completed. Each IIC data set consists of the first frame (address + read/write) and the subsequent frames (data). Each frame consists of 8-bit data and ACK/NAK; transmission of ACK or NAK and enabling or disabling NAK judgment must be specified using the command. The corresponding commands are updated by a command request interrupt (CREQ) issued after the operation reservation command is completed or automatically updated by the automatic command transition function. The commands corresponding to the first frame allow automatic transition. The commands corresponding to the subsequent frames are divided into two types; some are used for continuous data, which do not allow automatic transition, and others are used for the last data or a stop condition, which allow automatic transition. A command also allows automatic transition when arbitration loss occurs. The commands for continuous data generate a data transfer request interrupt (MRREQ, MTREQ, SRREQ, or STREQ) after the operation specified by the command is completed (one byte is processed). To process the last data, update the command at interrupt generation. Rev. 3.00 Jan 25, 2006 page 512 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.6 Operation Reservation Commands Mode Command Description IIC operation reservation adapter disabled Waits for address reception (ACK transmission/NACK enabled, reception using single buffer) Waits for address reception (NAK transmission/NACK disabled, reception using single buffer) Waits for address reception (ACK transmission/NACK enabled, reception using double buffer) Waits for address reception (NAK transmission/NACK disabled, reception using double buffer) Waits for slave reception, reserves ACK transmission, receives using single buffer Waits for slave reception, reserves NAK transmission, receives using single buffer Waits for slave reception, reserves ACK transmission, receives using double buffer Waits for slave reception, reserves NAK transmission, receives using double buffer Reserves slave transmission, automatically stops at NAK reception Reserves slave transmission, disables NAK Reserved (setting prohibited) Reserved (setting prohibited) Reserves master reception, reserves ACK transmission, receives using single buffer Reserves master reception, reserves NAK transmission, receives using single buffer Reserves master reception, reserves ACK transmission, receives using double buffer Reserves master reception, reserves NAK transmission, receives using double buffer Issues a start condition, reserves master transmission, enables NAK Issues a start condition, reserves master transmission, disables NAK Issues a start condition, reserves master transmission, issues a stop condition at NAK reception Issues a start condition, reserves master transmission, issues a stop condition at NAK reception Issues a retransmission start condition Transmits ACK, reserves stop condition issuance Transmits NAK, reserves stop condition issuance Reserves stop condition issuance Initial value 00 Slave A0 A1 A2 A3 A4 A5 A6 A7 A8, AA A9, AB AC to AF C0 to C3 Master C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF Rev. 3.00 Jan 25, 2006 page 513 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.7 Operation When the Operation Reservation Command Is Completed Trigger of Starting Operation Address reception Address reception Address reception Address reception A4 ICDRX read ICDRX read A5 ICDRX read ICDRX read A6 ICDRX read ICDRX read A7 ICDRX read ICDRX read A8, AA ICDRX write ICDRX write ICDRX write A9, AB ICDRX write ICDRX write Automatic Transition Conditions AAS or ADZ = 1, R/W = 0 AAS or ADZ = 1, R/W = 1 AASX = 1, R/W = 0 AASX = 1, R/W = 1 -- -- -- -- -- -- -- -- ACK received NAK received -- -- -- Transition Destination Commands A4 to A7 A8 to AB A4 to A7 A8 to AB -- A0 -- A0 -- A0 -- A0 -- -- A0 -- A0 Interrupt Flags CREQ, SRREQ CREQ, STREQ SRREQ STREQ SRREQ CREQ SRREQ CREQ SRREQ CREQ SRREQ CREQ STREQ CREQ CREQ STREQ CREQ Command A0 to A3 Operation Completion Address reception completed Address reception completed Address reception completed Address reception completed (ACK transmitted), reception completed ACK transmitted, stop condition detected (NAK transmitted), reception completed NAK transmitted, stop condition detected Reception completed, ACK transmitted Stop condition detected Reception completed, NAK transmitted Stop condition detected Transmission completed Transmission completed Stop condition detected Transmission completed Stop condition detected Rev. 3.00 Jan 25, 2006 page 514 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) Trigger of Starting Operation ICCMD write ICDRX write Simultaneous write to ICCMD and ICDRX ICDRX write Simultaneous write to ICCMD and ICDRX ICDRX write C8 ICDRX write -- C9 CA, CB ICDRX write ICDRX write ICDRX write C4 C5 C6 C7 CC CD CE CF ICDRX read ICDRX read ICDRX read ICDRX read ICCMD write ICCMD write ICCMD write ICCMD write Automatic Transition Conditions -- R/W = 1 R/W = 1 Transition Destination Commands -- -- -- 2 Command C8 to CB Operation Completion Start condition detected Address transmission completed Start condition issued, address transmission completed Address transmission completed Start condition issued, address transmission completed Arbitration lost Data transmission started -- Transmission completed Transmission completed Transmission completed stop condition issued (ACK transmitted), reception completed (NAK transmitted), reception completed Reception completed, ACK transmitted Reception completed, NAK transmitted Retransmission start condition issued ACK transmitted, stop condition issued ACK transmitted, stop condition issued Stop condition issued Interrupt Flags MTREQ MTREQ MTREQ R/W = 0 R/W = 0 C4 to C7 C4 to C7 MRREQ MRREQ -- -- NAK received* -- ACK received NAK received -- -- -- -- -- -- -- -- A0 -- -- -- -- A0 -- -- -- -- -- A0 A0 A0 CREQ MTREQ CREQ MTREQ MTREQ CREQ MRREQ MRREQ MRREQ MRREQ CREQ CREQ CREQ CREQ Note: * Data in the buffer is ignored. Rev. 3.00 Jan 25, 2006 page 515 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.5 Operation The I2C bus interface has an I2C bus format and a serial format. 17.5.1 I2C Bus Data Format The I2C bus formats are addressing formats and an acknowledge bit is inserted. The first frame following a start condition always consists of 9 bits. The I2C bus format is shown in figure 17.4. The serial formats are non-addressing formats with no acknowledge bit inserted. The serial format is shown in figure 17.5. The I2C bus timing is shown in figure 17.6. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 17.4 I2C Bus Data Formats (I2C Bus Formats) FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 17.5 I2C Bus Formats (Serial Formats) Rev. 3.00 Jan 25, 2006 page 516 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 17.6 I2C Bus Timing Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: From the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge signal. The receiving device drives SDA to low. DATA: Transmit/Receive data P: Stop condition. The master device drives SDA from low to high while SCL is high. 17.5.2 Master Transmit Operation When data is set to ICDR during the period between the execution of an instruction to issue a start condition and the creation of the start condition, the data may not be output normally, because there will be a conflict between generation of a start condition and output of data. Although data H'FF is to be sent to ICDR by a dummy write operation before an issue of a stop condition, the H'FF data may be output by the dummy write operation if the execution of the instruction to issue a stop condition is delayed. To prevent these problems, follow the flowchart shown below during the master transmit operation. In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations for sequential data transmission in synchronization with the ICDR writing are described below. 1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bits IICX1 and IICX0 in STCR, according to the operating mode. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. Rev. 3.00 Jan 25, 2006 page 517 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmit clock and the data written to ICDR using the timing shown in figure 17.7. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. 12. Clear the IRIC flag to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 3.00 Jan 25, 2006 page 518 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Start condition generation SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W [7] A Bit 7 Bit 6 Data 1 Slave address [5] IRIC IRTR ICDR * Incorrect operation Address + R/W Data 1 [9] IRIC clear Normal operation [6] ICDR write [6] IRIC clear [9] ICDR write User processing [4] BBSY set to 1 SCP cleared to 0 (start condition issuance) Note: * Data write timing in ICDR Figure 17.7 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0) 17.5.3 Master Receive Operation The data buffer of the IIC module can receive data consecutively since it consists of ICDRR and ICDRS. However, if the completion of receiving the last data is delayed, there will be a conflict between the instruction to issue a stop condition and the SCl clock output to receive the next data. This may generate unnecessary clocks or fix the output level of the SDA line as low. The switch timing of the ACKB bit in ICSR should be controlled because the acknowledge bit does not return an acknowledge signal after receiving the last data in master mode. These problems can be avoided by using the WAIT function. Follow the procedure shown below. In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The reception procedure and operations for sequential data reception with the wait function in synchronization with the ICDR read operation are shown below. Rev. 3.00 Jan 25, 2006 page 519 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Set the WAIT bit in ICMR to 1. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). 2. When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to detect wait operation, clear the IRIC flag in ICCR to 0. After reading ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for reception of one frame of data has passed before the IRIC clearing, the end of reception cannot be determined. 3. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last receive data, execute step [10] to halt reception. 4. Clear the IRIC flag to clear the wait state. The master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. 5. When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR are set to 1 at the rise of the 9th receive clock pulse. The master device outputs the receive clock to receive the next data. 6. Read ICDR receive data. 7. Clear the IRIC flag to 0 to detect the next wait operation. Data reception process from steps [5] to [7] should be executed during one byte reception period after IRIC flag clearing in step [4] or [9] to release the wait state. 8. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. If this frame is the last receive data, execute step [10] to halt reception. 9. Clear the IRIC flag in ICCR to cancel wait state. The master device outputs the 9th clock and drives SDA 1ow at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [5] to [9]. 10. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. 11. Clear the IRIC flag to 0 to release the wait state. 12. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th receive clock pulse. Rev. 3.00 Jan 25, 2006 page 520 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 13. Clear the WAIT bit in ICMR to 0 to clear wait mode. Read ICDR receive data and clear the IRIC flag to 0. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition cannot be issued because the output level of SDA is fixed as low.) 14. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master tansmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SDA (slave output) SDA (master output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A [5] Bit 7 Bit 6 Bit 5 Data 2 Bit 4 Bit 3 IRIC IRTR ICDR Data 1 User processing [1] TRS cleared to 0 [2] ICDR read [2] IRIC clear (dummy read) WAIT set to 1 ACKB cleared to 0 [4] IRIC clear [6] ICDR read [7] IRIC clear (Data 1) Figure 17.8 Master Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, WAIT = 1) Rev. 3.00 Jan 25, 2006 page 521 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 SCL (master output) 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA Bit 0 (slave output) Data 2 SDA (master output) Bit 7 [8] A [5] Bit 6 Bit 5 Bit 4 Data 3 Bit 3 Bit 2 Bit 1 Bit 0 [8] A [5] Bit 7 Bit 6 Data 4 IRIC IRTR ICDR Data 1 Data 2 Data 3 User processing [9] IRIC clear [6] ICDR read (Data 2) [7] IRIC clear [9] IRIC clear [6] ICDR read (Data 3) [7] IRIC clear Figure 17.9 Master Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, WAIT = 1) 17.5.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. 3. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. 4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. 5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Rev. 3.00 Jan 25, 2006 page 522 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is changed from low to high when SCL is high and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Start condition issuance SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 1 2 3 4 5 6 7 8 9 1 2 Slave address R/W [4] A Data 1 RDRF IRIC Interrupt request generation Address + R/W ICDRS ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clear Figure 17.10 Slave Receive Mode Operation Timing Example (1) (MLS = ACKB = 0) Rev. 3.00 Jan 25, 2006 page 523 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 SCL (master output) SCL (slave output) SDA (master output) 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 SDA (slave output) [4] Data 2 [4] A A RDRF IRIC Interrupt request generation Data 1 Data 2 Interrupt request generation ICDRS ICDRR Data 1 Data 2 User processing [5] ICDR read [5] IRIC clear Figure 17.11 Slave Receive Mode Operation Timing Example (2) (MLS = ACKB = 0) Rev. 3.00 Jan 25, 2006 page 524 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.5.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. 3. After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 17.12. 4. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS and the TDRE internal flag and IRIC and IRTR flags are set to 1 again. 5. To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE internal flag is cleared to 0. Transmit operations can be performed continuously by repeating steps [4] and [5]. To end transmission, write H'FF to ICDR. When SDA is changed from low to high when SCL is high and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 3.00 Jan 25, 2006 page 525 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Slave receive mode SCL (master output) SCL (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) SDA (master output) R/W A [2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 1 A Data 2 TDRE [3] IRIC Interrupt request generation Interrupt request generation Interrupt request generation ICDRT Data 1 Data 2 ICDRS Data 1 Data 2 User processing [3] IRIC clear [3] ICDR write [3] ICDR write [5] IRIC clear [5] ICDR write Figure 17.12 Slave Transmit Mode Operation Timing Example (MLS = 0) Rev. 3.00 Jan 25, 2006 page 526 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.5.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figures 17.13 to 17.15 show the IRIC flag timings and SCL control, and figure 17.16 shows an example of the interrupt flag timing of the operation reservation adapter. When WAIT = 0 while FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 2 3 SDA IRIC 7 8 A 1 2 3 User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception SCL 7 8 9 1 SDA IRIC 7 8 A 1 User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 for transmission or ICDRF = 1 for reception Figure 17.13 IRIC Flag Timing and SCL Control (1) Rev. 3.00 Jan 25, 2006 page 527 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 When WAIT = 1 while FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 2 3 SDA IRIC 8 A 1 2 3 User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception SCL 8 9 1 SDA IRIC 8 A 1 User processing Clear IRIC Write to ICDR (transmit) Clear or read from ICDR (receive) IRIC (b) Data transfer ends with ICDRE = 1 for transmission or ICDRF = 1 for reception Figure 17.14 IRIC Flag Timing and SCL Control (2) Rev. 3.00 Jan 25, 2006 page 528 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 When FS = 1 while FSX = 1 (synchronous serial format) SCL 7 8 1 2 3 4 SDA IRIC 7 8 1 2 3 4 User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception SCL 7 8 1 SDA IRIC 7 8 1 User processing Clear IRIC Write to ICDR (transmit) Clear IRIC or read from ICDR (receive) (b) Data transfer ends with ICDRE = 1 for transmission or ICDRF = 1 for reception Figure 17.15 IRIC Flag Timing and SCL Control (3) Rev. 3.00 Jan 25, 2006 page 529 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 First frame SCL 7 8 9 Second and subsequent frames 1 2 8 9 IRIC Read from or write to ICCMD Read from or write to ICCMD (a) Interrupt flag timing for request to write operation reservation commands SCL 7 8 9 1 2 8 9 MRREQ* SRREQ* Read from ICDRX Read from ICDRX (b) Interrupt flag timing for request to read receive data in master or slave mode SCL 7 8 9 1 2 8 9 MTREQ* STREQ* Write to ICDRX Write to ICDRX (c) Interrupt flag timing for request to write transmit data in master or slave mode Note: * Flags MRREQ, SRREQ, MTREQ, and STREQ may not change depending on the conditions. Figure 17.16 Example of Interrupt Flag Timing of Operation Reservation Adapter Rev. 3.00 Jan 25, 2006 page 530 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.5.7 Operation Using DTC This LSI provides the DTC to allow continuous data transfer. The DTC is activated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data transmission is completed with the acknowledge bit value of 0, and when the ACKE bit is 1, only the IRIC flag is set if data transmission is completed with the acknowledge bit value of 1. When initiated, the DTC transfers specified number of bytes, and then clears the ICDRE, IRIC, and IRTR flags to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, the DTC is not activated, thus allowing an interrupt to be generated if enabled. The acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1, indicating no specific events. The I2C bus format provides selection of the slave device and transfer direction by means of the slave address and the R/W bit, and confirmation of reception and display of the last frame with the acknowledge bit. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. For transfer operations by the operation reservation adapter, a stop condition is automatically issued when transfer of the number of transfer data bytes set by the DTC ends in master mode. Table 17.8 shows some examples of processing using the DTC. Table 17.9 shows some examples of operation reservation adapter processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Rev. 3.00 Jan 25, 2006 page 531 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.8 Examples of Operation Using DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: End condition issuance by CPU Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Transmission: Actual data count + 1 (+1 equivalent to dummy data (H'FF)) Reception: Actual data count Setting of number of DTC transfer data frames Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) Rev. 3.00 Jan 25, 2006 page 532 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.9 Examples of Operation Reservation Adapter Operation Using DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDRX + ICCMD write) Processing by CPU (ICDRX read) Reception by DTC (ICDRX read) -- Not necessary Slave Transmit Mode Not necessary Slave Receive Mode Not necessary Slave address + Transmission by R/W bit CPU (ICDRX + transmission/ ICCMD write) reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames -- -- -- Transmission by DTC (ICDRX write) -- Not necessary MTREQ: Clearing by CPU CREQ: Clearing by CPU Transmission: Actual data count Transmission by DTC (ICDRX write) Not necessary Not necessary Reception by DTC (ICDRX read) -- Not necessary SRREQ: Clearing by CPU CREQ: Clearing by CPU Reception: Actual data count MRREQ: Clearing STREQ: Clearing by CPU by CPU CREQ: Clearing by CPU Reception: Actual data count CREQ: Clearing by CPU Transmission: Actual data 17.5.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 17.17 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Rev. 3.00 Jan 25, 2006 page 533 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 17.17 Block Diagram of Noise Canceler 17.5.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in ICCRX or clearing the ICE bit. For details on the setting of bits CLR3 to CLR0, see section 17.3.7, IIC Operation Reservation Adapter Control Register (ICCRX). Scope of Initialization: The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (other than ICDRE and ICDRF flags), ICCRX, ICSRA, ICSRB, ICSRC, ICRRX, ICDRS, ICCNT, ICCMD) * Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, ICSR, ICSRB, and ICSRC * The value of the ICMR register bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Rev. 3.00 Jan 25, 2006 page 534 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is executed by ICCRX, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. * Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. 17.5.10 Sample Flowcharts Figures 17.18 to 17.21 show sample flowcharts for using the I2C bus interface in each mode. Rev. 3.00 Jan 25, 2006 page 535 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Start Initialize [1] Initialization Read BBSY in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC in ICCR [5] Wait for a start condition No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC in ICCR [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC continuously.) [7] Wait for 1 byte to be transmitted. [3] Select master transmit mode. [4] Start condition issuance Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No No [8] Test the acknowledge bit transferred from the slave device. Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC immediately.) [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB in ICSR [11] Test for end of tranfer No End of transmission? or ACKB = 1? Yes Clear IRIC in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 17.18 Sample Flowchart for Master Transmit Mode Rev. 3.00 Jan 25, 2006 page 536 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Master receive operation Set TRS = 0 in ICCR Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No [3] Wait for 1 byte to be received. IRIC = 1? Yes Last receive? No Clear IRIC in ICCR [4] Clear IRIC. (to end the wait insertion) Yes [2] Start receiving. The first read is a dummy read. (After reading from ICDR, clear IRIC continuously.) [1] Select receive mode. Read IRIC in ICCR [5] Wait for 1 byte to be received. No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Last receive? No Clear IRIC in ICCR Yes [8] Wait for the data for the second and subsequent bytes to be received. [6] Read the receive data. [7] Clear IRIC. [9] Clear IRIC. (to end the wait insertion) Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC = 1 in ICCR Read IRIC in ICCR [10] Set acknowledge data for the last reception. [11] Clear IRIC. (to end the wait insertion) [12] Wait for 1 byte to be received. No IRIC = 1? Yes Set WAIT = 0 in ICMR Read ICDR Clear IRIC in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [13] Clear wait mode. Read receive data. Clear IRIC. ( IRIC should be cleared to 0 after setting WAIT = 0.) [14] Stop condition issuance. Figure 17.19 Sample Flowchart for Master Receive Mode Rev. 3.00 Jan 25, 2006 page 537 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes [1] Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? Yes Read TRS in ICCR TRS = 0? Yes Last reception? No Read ICDR Clear IRIC in ICCR Yes No Slave transmit mode No General call address processing * Description omitted [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). [3] Start receiving. The first read is a dummy read. [4] Read IRIC in ICCR No IRIC = 1? Yes [4] Wait for the reception to end. [5] Set acknowledge data for the last reception. [6] Start the last reception. [7] Wait for the reception to end. Set ACKB = 1 in ICSR Read ICDR Clear IRIC in ICCR [5] [6] [8] Read the last receive data. Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR End [7] [8] Figure 17.20 Sample Flowchart for Slave Receive Mode Rev. 3.00 Jan 25, 2006 page 538 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [1] [2] Wait for 1 byte to be transmitted. [3] Test for end of transfer. Clear IRIC in ICCR [4] Set slave receive mode. [5] Dummy read (to release the SCL line). Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC in ICCR [4] [3] Write transmit data in ICDR No [5] End Figure 17.21 Sample Flowchart for Slave Transmit Mode 17.6 Interrupt Sources The I2C bus interface has four interrupt sources: IICC, IICM, IICR, and IICT. Table 17.10 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in ICCR, ICCRX, or ICCNT. Independent signals are sent to the interrupt controller for each interrupt. The IICM, IICR, and IICT interrupts can be used as DTC activation interrupt sources. Rev. 3.00 Jan 25, 2006 page 539 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Table 17.10 IIC Interrupt Sources Channel 0 Name IICC0 Enable Bit CRIC Interrupt Source Operation reservation command write request interrupt Master mode receive data read request interrupt Master mode transmit data write request interrupt IICR0 IEIC SRIC IICT0 1 IICC1 CRIC I C bus interface interrupt request Slave mode receive data read request interrupt Slave mode transmit data write request interrupt Operation reservation command write request interrupt Master mode receive data read request interrupt Master mode transmit data write request interrupt IICR1 IEIC SRIC IICT1 Note: * I C bus interface interrupt request Slave mode receive data read request interrupt Slave mode transmit data write request interrupt 2 2 Interrupt Flag CREQ DTC Activation Not possible Priority High IICM0 MRIC MRREQ MTREQ IRIC* SRREQ STREQ CREQ Possible Possible Possible Not possible IICM1 MRIC MRREQ MTREQ IRIC* SRREQ STREQ Possible Possible Possible Low Shares the interrupt source with SRREQ in the operation reservation adapter. Rev. 3.00 Jan 25, 2006 page 540 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 17.7 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from transmit buffer to shift register) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from shift register to receive buffer) 3. Table 17.11 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 17.11 I2C Bus Timing (SCL and SDA Outputs) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO 6 tcyc when IICX is 0, 12 tcyc when 1. Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28 tcyc to 256 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO - 1 tcyc 0.5 tSCLO - 1 tcyc 1 tSCLO 0.5 tSCLO + 2 tcyc 1 tSCLLO - 3 tcyc 1 tSCLL - (6 tcyc or 12 tcyc*) 3 tcyc ns Unit ns ns ns ns ns ns ns ns Notes 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 29.10. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. Rev. 3.00 Jan 25, 2006 page 541 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 17.12. Table 17.12 Permissible SCL Rise Time (tsr) Values Time Indication[ns] IICX1, tcyc IICX0 Indication 0 7.5 tcyc Standard mode I C Bus Specification = = = = = = (Max.) 5 MHz 8 MHz 10 MHz 16 MHz 20 MHz 25 MHz 1000 1000 300 1000 300 937 300 1000 300 750 300 1000 300 468 300 1000 300 375 300 875 300 300 300 700 300 2 High-speed mode 300 1 17.5 tcyc Standard mode 1000 High-speed mode 300 6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in table 17.11. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 17.13 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. The values in the above table will vary depending on the settings of the IICX1, IICX0, and CKS2 to CKS0 bits. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I2C bus interface specifications are met must be determined in accordance with the actual setting conditions. tBUFO fails to meet the I2C bus interface specifications at any frequency. The following solutions should be investigated. * * Provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition. Select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. The following solutions should be investigated. * * Adjusting the rise and fall times by means of a pull-up resistor and capacitive load. Reducing the transfer rate to meet the specifications. Rev. 3.00 Jan 25, 2006 page 542 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 * Selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Table 17.13 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I2C Bus tSr/tSf tcyc Item tSCLHO Indication 0.5 tSCLO (-tSr) Standard mode High-speed mode tSCLLO 0.5 tSCLO (-tSf) Standard mode High-speed mode tBUFO 0.5 tSCLO - 1 tcyc Standard mode ( -tSr) tSTAHO High-speed mode (Max.) -1000 -300 -250 -250 -1000 -300 -250 -250 -1000 -300 -1000 -300 -1000 -300 -1000 -300 0 0 Specifi= 5 MHz 4000 950 4750 = 8 MHz 4000 950 4750 = 10 MHz 4000 950 4750 = 16 MHz 4000 950 4750 1000*1 3938 *1 = 20 MHz 4000 950 4750 1000*1 3950 *1 = 25 MHz 4000 950 4750 1000*1 3960*1 910 *1 4710 960 9000 2200 4080 1030 3580 880 3220 520 120 120 (Min.) 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 0 0 Influence cation 1 1 1 1000* 1000* 1000* 3800 750 * *1 3875 *1 3900 *1 1 825 *1 4625 875 9000 2200 4250 1200 3325 625 2200 *1 -500 375 375 *1 850 *1 4650 900 9000 2200 4200 1150 3400 700 2500 -200 300 300 *1 888 *1 4688 938 9000 2200 4125 1075 3513 813 2950 250 188 188 900 *1 4700 950 9000 2200 4100 1050 3550 850 3100 400 150 150 0.5 tSCLO - 1 tcyc Standard mode (-tSf) High-speed mode Standard mode High-speed mode 4550 800 9000 2200 4400 1350 3100 400 1300 -1400 600 600 tSTASO 1 tSCLO (-tSr) tSTOSO 0.5 tSCLO + 2 tcyc Standard mode (-tSr) High-speed mode Standard mode High-speed mode Standard mode High-speed mode Standard mode High-speed mode tSDASO 3 1 tSCLLO* - 3 (master) tcyc (-tSr) tSDASO (slave) 1 tSCLL*3 - 2 3 tcyc* (-tSr) tSDAHO 3 tcyc Notes: 1. Does not meet the I C bus interface specifications. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS2 to CKS0. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I2C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6 tcyc). 3. Calculated using the I2C bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.). 2 Rev. 3.00 Jan 25, 2006 page 543 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 7. Notes on ICDR read at end of master reception To halt reception after completion of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high when the SCL pin is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer, the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing 0 to the BBSY bit in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Rewriting of IIC control bits for changing the operating mode and settings for transmission/reception, such as clearing the MST bit after master transmit/receive operation has ended, must be done during interval (a) in figure 17.22. Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9 Start condition Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confimation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 17.22 Notes on Reading Master Receive Data 8. Notes on start condition issuance for retransmission Depending on the timing combination with the start condition issuance and the subsequently writing data to ICDR, it may not be possible to issue the retransmission condition and the data transmission after retransmission condition issuance. Rev. 3.00 Jan 25, 2006 page 544 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Therefore, after start condition issuance is done and the start condition is generated, write the transmit data to ICDR. Figure 17.23 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. [1] Wait for end of 1-byte transfer IRIC = 1? Yes Clear IRIC in ICSR [3] Issue start condition instruction for retransmission Start condition issuance? Yes Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICSR) [3] No [2] [5] Set transmit data (slave address + R/W) No Other processing [4] Determine whether start condition is generated or not No [1] [2] Determine whether SCL is low IRIC = 1? Yes Write transmit data to ICDR No [4] Note: Program so that processing from [3] to [5] is executed continuously. [5] Start condition generation (retransmission) SCL 9 SDA ACK Bit 7 IRIC [5] ICDR write (transmit data) [4] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low [1] IRIC determination Figure 17.23 Flowchart and Timing of Start Condition Issuance for Retransmission Rev. 3.00 Jan 25, 2006 page 545 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 9. Note on when I2C bus interface stop condition instruction is issued In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low, as shown in figure 17.24. 9th clock V IH Secures a high period SCL SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low judgement [2] Stop condition instruction issuance Figure 17.24 Stop Condition Issuance Timing 10. Note on IRIC flag clearing when wait function is used When the wait function is used in I2C bus interface master mode and in a situation where the rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining that the SCL pin is low. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously. 9th clock VIH Secures a high period SCL SCL = low detected SDA IRIC [1] SCL = low determination [2] IRIC clear Figure 17.25 IRIC Flag Clearing Timing When WAIT = 1 Rev. 3.00 Jan 25, 2006 page 546 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 11. Note on ICDR read and ICCR access in slave transmit mode In I2C bus interface slave transmit mode, do not read from ICDR or do not read from or write to ICCR during the time shaded in figure 17.26. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions. Read ICDR data that has been received so far or read from or write to ICCR before starting the receive operation of the next slave address. Monitor the BC2 to BC0 counter in ICMR; when the count is 000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read from ICDR or read from or write to ICCR during the time other than the shaded time. Waveform at problem occurrence SDA R/W A Bit 7 SCL 8 9 TRS bit Address reception Data transmission ICDR read and ICCR read/write are disabled (Period of 6 system clocks) ICDR write The rise of the 9th clock is detected Figure 17.26 ICDR Read and ICCR Access Timing in Slave Transmit Mode 12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 17.27), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 17.27), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. Rev. 3.00 Jan 25, 2006 page 547 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 17.27. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR. Restart condition (a) SDA (b) A SCL 8 9 1 2 3 4 5 6 7 8 9 TRS Data transmission Address reception TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected The rise of the 9th clock is detected Figure 17.27 TRS Bit Set Timing in Slave Mode 13. Note on ICDR read in transmit mode and ICDR write in receive mode When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive mode or write to the ICDR after setting transmit mode. 14. Note on ACKE and TRS bits in slave mode In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1) and 1 is received as the acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source even when the address does not match. To use the I2C bus interface module in slave mode, be sure to follow the procedures below. Rev. 3.00 Jan 25, 2006 page 548 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 1. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR to 0 once to initialize the ACKB bit to 0. 2. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 17.21, in order to switch from slave transmit mode to slave receive mode. 15. Notes on WAIT function (a) Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall. (1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode (2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. (b) Error phenomenon Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the 7th clock fall and the 8th clock fall, the IRIC flag-clear data will be retained internally. Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall. (c) Restrictions Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2 through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th clock. If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC counter is turned to 1 or 0, please confirm the SCL pins are in L' state after the counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 17.28.) Rev. 3.00 Jan 25, 2006 page 549 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 SDA SCL BC2 to BC0 IRIC (operation example) A 9 0 1 7 2 6 Transmit/receive data A 7 2 1 8 SCL = `L' confirm 0 IRIC clear 9 Transmit/receive data 1 7 2 6 3 5 When BC2-0 2 IRIC clear 3 5 4 4 5 3 6 IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 17.28 IRIC Flag Clear Timing on WAIT Operation 16. Notes on Arbitration Lost The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 17.29.) In multi-master mode, a bus conflict could happen. When The I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. Rev. 3.00 Jan 25, 2006 page 550 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match DATA2 A DATA3 A Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device Figure 17.29 Diagram of Erroneous Operation when Arbitration Is Lost Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Note: Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register. Rev. 3.00 Jan 25, 2006 page 551 of 872 REJ09B0286-0300 Section 17 I C Bus Interface (IIC) 2 Rev. 3.00 Jan 25, 2006 page 552 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Section 18 Universal Serial Bus Interface (USB) This LSI incorporates a universal serial bus (conforms to USB standard Rev. 1.1) function module. A USB is an interface for connecting personal computer peripheral devices. There are various types of peripheral devices on the market. To support this wide range of devices, the USB in this LSI provides several device classes such as MassStorage class and HID (Human Interface Device) class for end points that support control transfer, interrupt transfer, and bulk transfer. 18.1 Features * USB standard Rev. 1.1 compliant * USB function core executed by standard commands Executed by interpreting device class commands by the CPU (Firmware must be created.) * Compound function consisting of HID device class and MassStorage device class * EP0: USB control endpoint (for control transfer) EP0S, EP0I, and EP0O can use their specific FIFOs. * EP1, EP2: HID control endpoint (for interrupt transfer) EP1 and EP2 use specific FIFOs. * EP3: MassStorage control endpoint (for interrupt transfer) EP3 uses a specific FIFO. * EP4, EP5: MassStorage data endpoint (for bulk transfer) EP4 and EP5 use a maximum of 2048-byte RFU-FIFOs. * Full speed (12 Mbps) support * System clock and external clock division/multiplication circuit * Bus driver/receiver incorporated Driven by DrVCC/DrVSS power supply Figure 18.1 shows the block diagram of the USB. IFUSB10A_000020020300 Rev. 3.00 Jan 25, 2006 page 553 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Internal FIFO controller EP0S FIFO EP0I FIFO EP0O FIFO Module data bus 1 Module data bus 2 Bus interface Internal data bus EP1 FIFO USDP USB function core USDM DrVCC DrVSS Bus driver/ receiver EP2 FIFO EP3 FIFO Control registers EP4 transmit buffer EP5 receive buffer Supplied to each block USEXCL 24 RFU request RFU communication Clock selection Internal interrupt Interrupt interface PLL Legend: USDP USDM USEXCL 24 DrVcc DrVss EP0S FIFO EP0I FIFO EP0O FIFO EP1 FIFO EP2 FIFO EP3 FIFO EP4 transmit buffer EP5 receive buffer Internal FIFO Controller Registers : Up-stream data + pin : Up-stream data - pin : USB external clock input pin : System clock : Clock multiplied to be 24 MHz : Bus driver power supply pin : Bus driver ground pin : FIFO in USB for endpoint 0S : FIFO in USB for endpoint 0I : FIFO in USB for endpoint 0O : FIFO in USB for endpoint 1 : FIFO in USB for endpoint 2 : FIFO in USB for endpoint 3 : Endpoint 4 transmit buffer : Endpoint 5 receive buffer EPDR0S EPDR0O EPDR0I EPDR1 EPDR2 EPDR3 FVSR0S FVSR0O FVSR0I FVSR1 FVSR2 FVSR3 EPSZR1 UDTRFR EP4PKTSZR : Endpoint data register 0S : Endpoint data register 0O : Endpoint data register 0I : Endpoint data register 1 : Endpoint data register 2 : Endpoint data register 3 : FIFO valid size register 0S : FIFO valid size register 01 : FIFO valid size register 0I : FIFO valid size register 1 : FIFO valid size register 2 : FIFO valid size register 3 : Endpoint size register 1 : RFU/FIFO read request flag register : Endpoint 4 packet size register Control Registers PTTER0 : Packet transfer enable register 0 USBIER0 : USB interrupt enable register 0 USBIFR0 : USB interrupt flag register 0 : Transfer normal completion interrupt flag register 0 TSFR0 : Transfer abnormal completion interrupt flag register 0 TFFR0 USBCSR0 : USB control/status register 0 USBIER1 : USB interrupt enable register 1 USBIFR1 : USB interrupt flag register 1 EPSTLR0 : Endpoint stall register 0 : Endpoint direction register 0 EPDIR0 EPRSTR0 : Endpoint reset register 0 DEVRSMR : Device resume register INTSELR0 : Interrupt source select register 0 USBCR1 : USB control register 1 USBMDCR : USB mode control register USBCR0 : USB control register 1 UPLLCR : USBPLL control register UPRTCR : USB port control register UTESTR0 : USB test register 0 UTESTR1 : USB test register 1 : Configuration value register CONFV Figure 18.1 Block Diagram of USB Rev. 3.00 Jan 25, 2006 page 554 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.2 Input/Output Pins Table 18.1 shows the USB pin configuration. Table 18.1 Pin Configuration Name Symbol Input/Output Function Input Input/Output Input/Output Input Input USB external clock input pin I/O pin for USB serial data I/O pin for USB serial data On-chip bus driver/receiver power supply pin On-chip bus driver/receiver ground pin External clock input USEXCL pin Up-stream data + pin Up-stream data + pin Bus driver power supply pin USDP USDM DrVCC Bus driver ground DrVSS pin 18.3 Register Descriptions In the USB protocol, the host sends a token to initiate a unit of data transmission (transaction). A transaction consists of a token packet, data packet, and handshake packet. A token packet contains information relating to the device addresses and endpoints, and transfer type. A data packet contains data. A handshake packet includes information relating to the transmission success or failure. To transfer data from the host to the slave, the host first sends an OUT or SETUP token and then sends data to the slave (OUT transaction or SETUP transaction). To transfer data from the slave to the host, the host first sends an IN token to the slave and then waits for data sent from the slave (IN transaction). In the following descriptions, IN and OUT operations based on the host may be described as input and output. In addition, host input transfer may be referred to as IN (IN transaction, IN-FIFO, or EP0in). Host output transfer may be referred to as OUT (OUT transaction, OUT-FIFO, or EP0out). On the other hand, transmission (send) and reception (receive) mean transmission and reception based on the USB module or slave CPU unless it is noted as transmission by the host or reception by the host. Rev. 3.00 Jan 25, 2006 page 555 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) The USB has the following registers. * Endpoint size register 1 (EPSZR1) * Endpoint data register 0S (EPDR0S) * Endpoint data register 0O (EPDR0O) * Endpoint data register 0I (EPDR0I) * Endpoint data register 1 (EPDR1) * Endpoint data register 2 (EPDR2) * Endpoint data register 3 (EPDR3) * FIFO valid size register 0S (FVSR0S) * FIFO valid size register 0O (FVSR0O) * FIFO valid size register 0I (FVSR0I) * FIFO valid size register 1 (FVSR1) * FIFO valid size register 2 (FVSR2) * FIFO valid size register 3 (FVSR3) * Endpoint direction register 0 (EPDIR0) * Packet transfer enable register 0 (PTTER0) * USB interrupt enable register 0 (USBIER0) * USB interrupt enable register 1 (USBIER1) * USB interrupt flag register 0 (USBIFR0) * USB interrupt flag register 1 (USBIRF1) * Transfer normal completion interrupt flag register 0 (TSFR0) * Transfer abnormal completion interrupt flag register 0 (TFFR0) * USB control/status register 0 (USBCSR0) * Endpoint stall register 0 (EPSTLR0) * Endpoint reset register 0 (EPRSTR0) * Device resume register (DEVRSMR) * Interrupt source select register 0 (INTSELR0) * USB control register 0 (USBCR0) * USB control register 1 (USBCR1) * USBPLL control register (UPLLCR) * Configuration value register (CONFV) * Endpoint 4 packet size register (EP4PKTSZR) * RFU/FIFO read request flag register (UDTRFR) * USB mode control register (USBMDCR) Rev. 3.00 Jan 25, 2006 page 556 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) * USB port control register (UPRTCR) * USB test register 0 (UTESTR0) * USB test register 1 (UTESTR1) 18.3.1 USB Data FIFO FIFOs combined with EPDRs intervene in data transfer between this LSI (slave CPU) and the USB function core. The USB function core performs data transmission to or from the USB host (host). This LSI incorporates 80 bytes of specific FIFOs, and a RAM-FIFO unit (RFU) that can be used as a maximum of 4096 bytes of FIFOs by using on-chip RAM. As shown in table 18.2, specific FIFOs can be used in two ways based on whether EP2 is used or not. In EP0I, EP0O, EP1, and EP2, the maximum packed size of the data packet is specified as half of the FIFO size (bytes). In EP0S and EP3, the maximum packet size of the data packet is equal to the FIFO size (bytes). EP0S is a specific FIFO for setup command reception, which is enabled or disabled by the SETICNT bit in USBMDCR. For details on RAM-FIFOs that form EP4 and EP5, refer to section 8, RAM-FIFO Unit (RFU). In the host input transfer, all data items sent from the slave are written to a specific FIFO before the slave transmission is initiated. In the host output transfer, the host transfer is completed before the slave reads all data items from the specific FIFO. Table 18.2 FIFO Configuration Endpoint Endpoint 0 EP0S EP0O EP0I Endpoint 1 Endpoint 2 Endpoint 3 Endpoint 4 Endpoint 5 EP1 EP2 EP3 EP4 EP5 Transfer Direction OUT (SETUP) OUT IN IN IN/OUT IN IN OUT FIFO Size 8 bytes 16 bytes 16 bytes 16 bytes 32 bytes 16 bytes 0 bytes 8 bytes Max. 2048 bytes Max. 2048 bytes Configuration 8 bytes x 1 8 bytes x 2 8 bytes x 2 8 bytes x 2 16 bytes x 2 8 bytes x 2 Not used 8 bytes x 1 Max. 64 bytes x 32 Max. 64 bytes x 32 RAM-FIFO (RFU) Description Specific FIFO Rev. 3.00 Jan 25, 2006 page 557 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.2 Endpoint Size Register 1 (EPSZR1) EPSZR1 specifies the sizes of the FIFO (number of bytes) used in USB function core endpoints 1 and 2. To use both endpoints 1 and 2 in this LSI, the size of FIFOs used for endpoints 1 and 2 must be specified as 16 bytes. To use only endpoint 1 in this LSI, the size of FIFO used for endpoint 1 must be specified as 16 bytes or 32 bytes. If the size of FIFO used for endpoint 1 is specified as 32 bytes, the FIFO for endpoint 2 must be specified as 0 bytes. EPSZR1 is initialized to H'44 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 6 5 4 Bit Name EP1SZ3 EP1SZ2 EP1SZ1 EP1SZ0 Initial Value R/W 0 1 0 0 R/W R/W R/W R/W Description EP1 FIFO Size 0000 : Setting prohibited 0001 : Setting prohibited 0010 : Setting prohibited 0011 : Setting prohibited 0100 : FIFO size, 16 bytes 0101 : FIFO size, 32 bytes 0110 : Setting prohibited 0111 : Setting prohibited 1XXX: Setting prohibited 3 2 1 0 EP2SZ3 EP2SZ2 EP2SZ1 EP2SZ0 0 1 0 0 R/W R/W R/W R/W EP2 FIFO Size 0000 : FIFO size, 0 byte 0001 : Setting prohibited 0010 : Setting prohibited 0011 : Setting prohibited 0100 : FIFO size, 16 bytes 0101 : Setting prohibited 0110 : Setting prohibited 0111 : Setting prohibited 1XXX: Setting prohibited Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 558 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3 (EPDR0S, EPDR0O, EPDR0I, EPDR1, EPDR2, and EPDR3) EPDRs intervene in the data transfer between the CPU and FIFOs in each host input transfer or host output transfer for the USB function core endpoints 1 and 2. EPDR0I, EPDR1, and EPDR3 are write-only registers used for host input transfer. EPDR0S and EPDR0O are read-only registers used for host output transfer. EPDR2 is specified depending on the transfer direction specified in EPDIR0. If EPDIR0 is specified as a host input transfer, EPDR2 is specified as a read-only register; if EPDIR0 is specified as a host output transfer, EPDR2 is specified as a write-only register. Data written in EPDR0I, EPDR1, EPDR2 (write-only register), and EPDR3 is stored in the FIFOs and is enabled by setting the EPTE bit in PTTER0. This enabled data is transferred to the USB function core according to the USB function core's request and then sent to the host. Data sent to the host is stored in the FIFO by the USB function core and is enabled by returning an ACK handshake after all bytes of data packet has been received. When reading EPDR0S, EPDR0O, or EPDR2 (read-only register), data is stored in the FIFO and then enabled data is read out in order of transfer. EPDR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Note that EPDR for endpoints 4 and 5 is not supported. Data is handled by reading on-chip RAM directly. EPDR0S Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W All 0 R Description Endpoint 0 is used for input or output transfer and EPDR0S is specified as a read-only register. EPDR0S is a specific FIFO for setup command reception and is enabled when the SETICNT bit in USBMDCR is set to 1. EPDR0S access is disabled when the SETICNT bit is cleared to 0. EPDR0O Bit 7 to 0 Bit Name D7 to D0 Initial Value R/W All 0 R Description Endpoint 0 is used for input or output transfer and EPDR0O is specified as a read-only register. Rev. 3.00 Jan 25, 2006 page 559 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) EPDR0I Bit Bit Name Initial Value R/W All 0 W Description Endpoint 0 is used for input or output transfer and EPDR0I is specified as a write-only register. 7 to 0 D7 to D0 EPDR1 Bit Bit Name Initial Value R/W All 0 W Description Endpoint 1 is used for input transfer and EPDR1 is specified as a write-only register. 7 to 0 D7 to D0 EPDR2 Bit Bit Name Initial Value R/W All 0 Description 7 to 0 D7 to D0 R or W EPDR2 is specified as a write-only or read-only register depending on the transfer direction specified by EPDIR0. EPDR3 Bit Bit Name Initial Value R/W All 0 W Description Endpoint 3 is used for input transfer and EPDR3 is specified as a write-only register. 7 to 0 D7 to D0 18.3.4 Endpoint Valid Size Registers 0S, 0O, 0I, 1, 2, and 3 (FVSR0S, FVSR0O, FVSR0I, FVSR1, FVSR 2, and FVSR3) FVSRs indicate the number of valid data items stored in FIFOs in each endpoint of the USB function core. Since endpoints 4 and 5 do not use FIFOs in the USB interface, they perform data transfer by using the RFU which has the function corresponding to FVSRs. In host input transfer, FVSR indicates the number of bytes that the slave CPU can write to the FIFO (FIFO size -- number of bytes that are written to the FIFO by the slave CPU but which are not read (transmitted) by the USB function core). In host output transfer, FVSRs indicate the number of bytes that are written to the FIFO by the USB function core but which are not read by the slave CPU. Rev. 3.00 Jan 25, 2006 page 560 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) In host input transfer, FVSR is decremented by the number of bytes to be written if the slave CPU writes to EPDR and sets the EPTE bit in PTTER0; FVSR is incremented by the number of bytes to be read if the USB function core reads the FIFO and an ACK handshake is received from the host. In host output transfer, the FVSR is incremented by the number of bytes to be written if the USB function core writes to the FIFO and sends an ACK handshake; FVSR is decremented by 1 if the slave CPU reads the EPDR. In certain situations, data must be re-transferred if a transfer error occurs. In this case, the FVSR is not modified and the FIFO of the channel to be re-transferred will be re-wound. In the USB protocol, the DATA0 and DATA1 packets are transmitted or received alternatively during data transfer for each endpoint. Accordingly, the success of the data transfer can be checked by the DATA0 and DATA1 packet toggles. If the DATA0 or DATA1 packet toggle is not performed correctly, the USB function core stops the transaction processing and the FVSR value does not change. FVSR is a 2-byte register but can indicate the FIFO status only by using the lower byte, since the FIFOs used in this LSI are 8 bytes, 16 bytes or 32 bytes. Therefore, only the lower byte of FSVR must be read. The upper byte of FSVR cannot be accessed directly. The upper byte of FSVR is sent to the temporary register when the lower byte of FSVR is read and the contents of the temporary register can be read when the upper byte of FSVR is read. If FSVR is read by word access, the contents of the upper byte indicates the value when the lower byte has been read out. FVSR0S, FVSR0O, and FVSR0I are automatically specified as H'0000, H'0000, and H'0010, respectively when a SETUP token has been received. FVSR is initialized by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)) according to the transfer direction and the FIFO size specified by EPDIR0 and EPSZR1. Rev. 3.00 Jan 25, 2006 page 561 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) FVSR0SH, FVSR0OH, FVSR0IH, FVSR1H, FVSR2H, FVSR3H Bit 7 6 5 4 3 2 1 0 Bit Name -- -- -- -- -- -- N9 N8 Initial Value R/W 0 0 0 0 0 0 0 0 R R R R R R R R Description Initial Values FVSR0SH: H'00 FVSR0OH: H'00 FVSR0IH: H'00 FVSR1H: H'00 FVSR2H: H'00 FVSR3H: H'00 FVSR0SL, FVSR0OL, FVSR0IL, FVSR1L, FVSR2L, FVSR3L Bit 7 6 5 4 3 2 1 0 Bit Name N7 N6 N5 N4 N3 N2 N1 N0 Initial Value R/W 0 0 0 0/1* 2 0/1* 1 Description Initial Values FVSR0SL: H'00 FVSR0OL: H'00 FVSR0IL: H'10 FVSR1L: H'10 FVSR2L: H'10 FVSR3L: H'08 R R R R R R R R 0 0 0 Notes: 1. Initial value of the N4 bit is 0 in FVSR0S, FVSR0O, and FVSR3 and 1 in other FVSRs. 2. Initial value of the N3 bit is 1 in FVSR3 and 0 in other FVSRs. Rev. 3.00 Jan 25, 2006 page 562 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.5 Endpoint Direction Register 0 (EPDIR0) EPDIR0 controls the direction of data transfer for endpoints other than endpoint 0 of the USB function core. In this LSI, EP1, EP3 and EP4 must be specified as host input transfers, EP5 as a host output transfer, and EP2 as either a host input transfer or host output transfer. EPDIR0 is initialized to H'3C by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 6 Bit Name -- EP5DIR Initial Value R/W 0 0 R R/W Description Reserved This bit is always read as 0 and cannot be modified. Endpoint 5 Data Direction Control Flag Controls the data transfer direction of endpoint 5. 0: Endpoint 5 is specified as host output transfer 1: Setting prohibited 5 EP4DIR 1 R/W Endpoint 4 Data Direction Control Flag Controls the data transfer direction of endpoint 4. 0: Setting prohibited 1: Endpoint 4 is specified as host input transfer 4 EP3DIR 1 R/W Endpoint 3 Data Direction Control Flag Controls the data transfer direction of endpoint 3. 0: Setting prohibited 1: Endpoint 3 is specified as host input transfer 3 EP2DIR 1 R/W Endpoint 2 Data Direction Control Flag Controls the data transfer direction of endpoint 2. 0: Endpoint 2 is specified as host output transfer 1: Endpoint 2 is specified as host input transfer 2 EP1DIR 1 R/W Endpoint 1 Data Direction Control Flag Controls the data transfer direction of endpoint 1. 0: Setting prohibited 1: Endpoint 1 is specified as host input transfer 1, 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 563 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.6 Packet Transfer Enable Register 0 (PTTER0) PTTER0 controls the FIFO valid size register used in the host input transfer of the USB function core. In the USB protocol, communication is performed using packets. The minimum unit of data transfer is a transaction. A transaction is comprised of a token packet, a data packet, and a handshake packet. In host input transfer, the USB function core receives an IN token (packet). On receiving the IN token, the USB core must send a data packet when it is not stalled or a NAK handshake if no data exists. If an EPTE bit is set to 1 after the slave CPU has written the data that is to be transferred to the host in the FIFO, the contents of FVSR is modified. This enables the transmission of data written in FIFO. By controlling the data transmission using an EPTE bit, erroneous data transmission during data write from slave CPU to FIFO can be prevented effectively. The FIFO used for endpoint 4 is assigned to the on-chip RAM area controlled by the RFU. If the EP4TE bit is set to 1, data transmission is initiated by an IN token and then data in the FIFO is sent to a buffer in the USB interface (pre-read). To transfer a data packet of 0 bytes to the host, set the corresponding EPTE bit to 1 in the RAMFIFO empty state. Rev. 3.00 Jan 25, 2006 page 564 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 7, 6 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0 and cannot be modified. 5 EP4TE 0 R/(W)* Endpoint 4 Packet Transmission Enable Prepares the transmission of RAM-FIFO data for endpoint 4 0: Normal read value. 1: Prepares the transmission of RAM-FIFO data for endpoint 4. The EP4TE bit must be set 1 for each IN transfer in one transaction. 4 EP3TE 0 R/(W)* Endpoint 3 Packet Transmission Enable Updates FVSR3 for endpoint 3 0: Normal read value. 1: Updates FVSR3 in endpoint 3-specific FIFO. 3 EP2TE 0 R/(W)* Endpoint 2 Packet Transmission Enable Modifies FVSR2 for endpoint 2 if the EP2DIR bit is set to 1. 0: Normal read value. 1: Updates FVSR2 in endpoint 2-specific FIFO. 2 EP1TE 0 R/(W)* Endpoint 1 Packet Transmission Enable Updates FVSR2 for endpoint 1. 0: Normal read value. 1: Updates FVSR1 in endpoint 1-specific FIFO. 1 EP0ITE 0 R/(W)* Endpoint 1 Packet Transmission Enable Updates FVSR0I for endpoint 0. 0: Normal read value. 1: Updates FVSR0I in endpoint 0-specific FIFO. 0 Note: -- * 0 Only 1 can be written. R Reserved This bit is always read as 0 and cannot be modified. 18.3.7 USB Interrupt Enable Registers 0 and 1 (USBIER0, USBIER1) USBIER0 and USBIER1 provide interrupt enable bits that allow interrupt requests from the USB function core to the slave CPU. Rev. 3.00 Jan 25, 2006 page 565 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USBIER0 and USBIER1 are initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). USBIER0 Bit 7 6 Bit Name Initial Value R/W -- UDTRE 0 0 R R/W Description Reserved This bit is always read as 0 and cannot be modified. RFU/FIFO Read Request Interrupt Enable 0: Disables EP5 RFU/FIFO read request interrupt 1: Enables EP5 RFU/FIFO read request interrupt 5 BRSTE 0 R/W Bus Reset Interrupt Enable 0: Disables bus reset interrupt of USB function core 1: Enables bus reset interrupt of USB function core 4 SOFE 0 R/W SOF Interrupt Enable 0: Disables USB function core SOF (start of frame) interrupt 1: Enables USB function core SOF (start of frame) interrupt 3 SPNDE 0 R/W Suspend Interrupt Enable 0: Disables USB function core suspend OUT and IN interrupts 1: Enables USB function core suspend OUT and IN interrupts 2 TFE 0 R/W Transfer Abnormal Completion Interrupt Enable 0: Disables transfer abnormal completion interrupt of the USB function core 1: Enables transfer abnormal completion interrupt of the USB function core 1 TSE 0 R/W Transfer Normal Completion Interrupt Enable 0: Disables transfer normal completion interrupt of the USB function core 1: Enables transfer normal completion interrupt of the USB function core 0 SETUPE 0 R/W Setup Interrupt Enable 0: Disables USB function core setup interrupt 1: Enables USB function core setup interrupt Rev. 3.00 Jan 25, 2006 page 566 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USBIER1 Bit 7 to 2 1 SETCE 0 R/W Bit Name Initial Value R/W -- All 0 R Description Reserved These bits are always read as 0 and cannot be modified. SetConfiguration Command Detection Interrupt Enable 0: Disables SetConfiguration command detection interrupt 1: Enables SetConfiguration command detection interrupt 0 SETIE 0 R/W SetInterface Command Detection Interrupt Enable 0: Disables SetInterface command detection interrupt 1: Enables SetInterface command detection interrupt 18.3.8 USB Interrupt Flag Registers 0 and 1 (USBIFR0, USBIFR1) USBIFR0 and USBIFR1 have interrupt flags which generate interrupts from the USB module to the slave CPU. The USB module supports four interrupt sources: USBIA, USBIB, USBIC, and USBID. USBIA is specific to a setup interrupt. USBIB and USBIC can be used for either transfer normal completion interrupts or transfer abnormal completion interrupts. USBID can be used for other interrupts such as transfer normal completion interrupts, transfer abnormal completion interrupts, RFU/FIFO read request interrupts, bus reset interrupts, SOF interrupts, suspend OUT interrupts, suspend IN interrupts, SetConfiguration command detection interrupts, and SetInterface command detection interrupts. USBIFR0 and USBIFR1 are initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Rev. 3.00 Jan 25, 2006 page 567 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USBIFR0 Bit 7 Bit Name Initial Value R/W TS 0 R Description Transfer Normal Completion Interrupt Status Indicates that data transfer for an USB core endpoint has been completed normally. If the TSE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. In this case, if an interrupt source whose TS bit is set to 1 is specified to request an USBIB or USBIC interrupt, the USBIB or USBIC interrupt is processed prior to the USBID interrupt according to the interrupt priority specified in the slave CPU interrupt controller. 0: All bits in TSFR0 are cleared to 0. 1: At least one bit in TSFR0 is set to 1. 6 TF 0 R Transfer Abnormal Completion Interrupt Status Indicates that data transfer for an USB core endpoint has been completed abnormally. If the TFE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. In this case, if an interrupt source whose TF bit is set to 1 is specified to request an USBIB or USBIC interrupt, the USBIB or USBIC interrupt is processed prior to the USBID interrupt according to the interrupt priority specified in the slave CPU interrupt controller. 0: All bits in TFFR0 are cleared to 0. 1: At least one bit in TFFR0 is set to 1. 5 UDTRF 0 R RFU/FIFO Read Request Interrupt Status Indicates that the host output transfer (out transaction) has been completed normally and that the RAM-FIFO is full and the receive buffer contains data. If the UDTRE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. 0: All bits in UDTRFR are cleared to 0. 1: At least one bit in UDTRFR is set to 1. Rev. 3.00 Jan 25, 2006 page 568 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 4 Bit Name Initial Value R/W BRSTF 0 Description Indicates that the USB function core detects a bus reset by an up-stream. If the BRSTE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 3 SOFF 0 0 is written to after BRSTF = 1 has been read. The USB function core detects a bus reset by an upstream. [Setting condition] R/(W)* Bus Reset Interrupt Status R/(W)* SOF Interrupt Status Indicates that the USB function core detects an SOF (Start of Frame) by an up-stream. If the SOFE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 0 is written to after SOFF = 1 has been read. The USB function core detects an SOF (Start of Frame). [Setting condition] 2 SPNDOF 0 R/(W)* Suspend OUT Interrupt Status Indicates that the USB function core detects a bus state transition from suspend state to normal state. If the SPNDE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 0 is written to after SPNDOF = 1 has been read. The USB function core detects a bus state transition from suspend state to normal state. [Setting condition] Rev. 3.00 Jan 25, 2006 page 569 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 1 Bit Name Initial Value R/W SPNDIF 0 Description Indicates that the USB function core detects an idle state for a specific period or more, and detects a bus state transition from normal state to suspend state. If the SPNDE bit in USBIER0 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 0 SETUPF 0 0 is written to after SPNDIF = 1 has been read. The USB function core detects s bus state transition from normal state to suspend state. [Setting condition] R/(W)* Suspend IN Interrupt Status R/(W)* Setup Interrupt Status The meaning of this bit differs depending on the SETICNT bit in USBMDCR. When SETICNT = 0, Indicates that endpoint 0 of the USB function core receives a SETUP token. When SETICNT = 1, Indicates that endpoint 0 of the USB function core receives a setup command that must be decoded by the slave CPU. If the SETUPE bit in USBIER0 is set to 1, an USBIA interrupt is requested to the slave CPU. [Clearing condition] * * * 0 is written to after SETUPF = 1 has been read. Endpoint 0 of the USB function core receives a SETUP token (when SETICNT = 0). Endpoint 0 of the USB function core receives a setup command to be decoded by the slave CPU (when SETICNT = 1). [Setting conditions] Note: * Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 570 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USBIFR1 Bit 7 to 2 1 SETC 0 Bit Name Initial Value R/W -- All 0 R Description Reserved These bits are always read as 0 and cannot be modified. * SetConfiguration Command Detection Interrupt Status R/(W) Indicates that the USB function core detects a SetConfiguration command. If the SETCE bit in USBIER1 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 0 is written to after SETC = 1 has been read. The USB function core detects a SetConfiguration command. [Setting condition] 0 SETI 0 R/(W)* SetInterface Command Detection Interrupt Status Indicates that the USB function core detects a SetInterface command. If the SETIE bit in USBIER1 is set to 1, an USBID interrupt is requested to the slave CPU. [Clearing condition] * * 0 is written to after SETI = 1 has been read. The USB function core detects a SetConfiguration command. [Setting condition] Note: * Only 0 can be written to clear the flag. 18.3.9 Transfer Normal Completion Interrupt Flag Register 0 (TSFR0) TSFR0 provides status flags indicating that the host input or host output transaction of each USB function core endpoint has been completed normally. The normal completion of a transaction can be detected by an ACK handshake reception in host input transfer or by an ACK handshake transmission in host output transfer. TSFR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Rev. 3.00 Jan 25, 2006 page 571 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 7 6 Bit Name Initial Value R/W -- EP5TS 0 0 R Description Reserved This bit is always read as 0 and cannot be modified. R/(W)* Endpoint 5 Transfer Success Flag Indicates that the endpoint 5 host output transfer has been completed normally. When host output transfer is completed normally while the RAM-FIFO is full and data still remains in the receive buffer, this bit is not set to 1 and the EP5UDTR bit in UDTRFR is set to 1. For details, see section 18.3.20, RFU/FIFO Read Request Flag Register (UDTRFR). 0: Indicates that the endpoint 5 is in a transfer wait state. [Clearing condition] * 0 is written to EP5TS after EP5TS = 1 has been read. 1: Indicates that the endpoint 5 host output transfer (OUT transaction) has been completed normally. [Setting condition] * An ACK handshake has been achieved (ACK transmission) after OUT token reception and data transfer, and FIFO operation by the RFU has been completed normally. 5 EP4TS 0 R/(W)* Endpoint 4 Transfer Success Flag Indicates that the endpoint 4 host input transfer has been completed normally. 0: Indicates that the endpoint 4 is in a transfer wait state. [Clearing condition] * 0 is written to EP4TS after EP4TS = 1 has been read. 1: Indicates that the endpoint 4 host input transfer (IN transaction) has been completed normally. [Setting condition] * An ACK handshake has been achieved (ACK transmission) after IN token reception and data transfer, and FIFO operation by the RFU has been completed normally. Rev. 3.00 Jan 25, 2006 page 572 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 4 Bit Name Initial Value R/W EP3TS 0 Description Indicates that the endpoint 3 host input transfer has been completed normally. 0: Indicates that the endpoint 3 is in a transfer wait state. [Clearing condition] * 0 is written to EP3TS after EP3TS = 1 has been read. R/(W)* Endpoint 3 Transfer Success Flag 1: Indicates that the endpoint 3 host input transfer (IN transaction) has been completed normally. [Setting condition] * 3 EP2TS 0 An ACK handshake has been achieved (ACK reception) after IN token reception and data transfer. R/(W)* Endpoint 2 Transfer Success Flag Indicates that the endpoint 2 host input/output transfer has been completed normally. 0: Indicates that the endpoint 2 is in a transfer wait state. [Clearing condition] * 0 is written to EP2TS after EP2TS = 1 has been read. 1: Indicates that the endpoint 2 host input transfer (IN transaction) or host output transfer (out transaction) has been completed normally. [Setting conditions] * An ACK handshake has been achieved (ACK transmission) after IN token reception and data transfer. An ACK handshake has been achieved (ACK transmission) after OUT token reception data transfer. * Rev. 3.00 Jan 25, 2006 page 573 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 Bit Name Initial Value R/W EP1TS 0 Description Indicates that the endpoint 1 host input transfer has been completed normally. 0: Indicates that the endpoint 1 is in a transfer wait state. [Clearing condition] * 0 is written to EP1TS after EP1TS = 1 has been read. 1: Indicates that the endpoint 1 host input transfer (IN transaction) has been completed normally. [Setting condition] * 1 EP0ITS 0 An ACK handshake has been achieved (ACK reception) after IN token reception and data transfer. R/(W)* Endpoint 1 Transfer Success Flag R/(W)* Endpoint 0 Transfer Success Flag Indicates that the endpoint 0 host input transfer has been completed normally. 0: Indicates that the endpoint 0 is in a transfer wait state. [Clearing conditions] * * 0 is written to EP0ITS after EP0ITS = 1 has been read. The endpoint 0 has received a SETUP token 1: Indicates that the endpoint 1 host input transfer (IN transaction) has been completed normally. [Setting condition] * An ACK handshake has been achieved (ACK reception) after IN token reception and data transfer. Rev. 3.00 Jan 25, 2006 page 574 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 0 Bit Name Initial Value R/W EP0OTS 0 Description Indicates that the endpoint 0 host output transfer has been completed normally. Endpoint 0 host output transfer has two transactions: OUT transaction and SETUP transaction. Data transmission in these transactions are the same, but flag handling in these transactions differ. Since most of the commands sent by a SETUP transaction are processed in the USB function core, the EP0OTS flag is not set and the EP0OTF flag in TFFR0 is set to 1. For a command that cannot be processed in the USB core, the EP0OTS flag is set to 1. Note that neither the EP0OTS nor the EP0OTF flag is set to 1 if the SEICNT bit in USBMDCR is set to 1 regardless of whether the command can be processed in the USB core or not. 0: Indicates that the end point 0 is in a host output transfer wait state. [Clearing conditions] * * 0 is written to EP0OTS after EP0OTS = 1 has been read. Endpoint 0 has received a SETUP token. R/(W)* Endpoint 0 Host Output Transfer Success Flag 1: Indicates that the endpoint 0 host output transfer (OUT transaction or SETUP transaction) has been completed normally. [Setting conditions] * An ACK handshake has been achieved (ACK transmission) after OUT token reception and data transfer. A received command needs to be processed in the slave CPU after a SETUP token has been received (only when the SETICNT bit is cleared to 0). * Note: * Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 575 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.10 Transfer Abnormal Completion Interrupt Flag Register 0 (TFFR0) TFFR0 provides status flags (EPTF) indicating that the host input or host output transaction of each USB function core endpoint has been completed abnormally. The abnormal completion of a transaction will be detected if a NAK handshake has been received or a NAK handshake has been sent because no transfer data has been received (FVSR = FIFO size: FIFO empty) in host input transfer, if a NAK handshake has been sent because the FIFO is full during data transfer in host output transfer, or if other transfer errors (DATA0/DATA1 toggle error, bit staffing error, bit count error, CRC error, and a transfer whose byte size exceeds Max Packet Size, etc.) occur. TFFR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Rev. 3.00 Jan 25, 2006 page 576 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 7 6 Bit Name Initial Value R/W -- EP5TF 0 0 R Description Reserved This bit is always read as 0 and cannot be modified. R/(W)* Endpoint 5 Transfer Failure Flag Indicates that the endpoint 5 host output transfer has been completed abnormally. 0: Indicates that the endpoint 5 is in a transfer wait state. [Clearing condition] * 0 is written to EP5TF after EP5TF = 1 has been read. 1: Indicates that the endpoint 5 host output transfer (OUT transaction) has been completed abnormally. [Setting conditions] * Data cannot be received because both receive buffers for RFU and FIFO become full after an OUT token has been received (NAK transmission). A communication error occurs after an OUT token has been received. * 5 EP4TF 0 R/(W)* Endpoint 4 Transfer Failure Flag Indicates that the endpoint 4 host input transfer has been completed abnormally. 0: Indicates that the endpoint 4 is in a transfer wait state. [Clearing condition] * 0 is written to EP4TF after EP4TF = 1 has been read. 1: Indicates that the endpoint 4 host input transfer (IN transaction) has been completed abnormally. [Setting conditions] * An ACK handshake cannot be achieved after an IN token has been received and data has been transferred. Data cannot be sent because both receive buffers for RFU and FIFO are empty after an IN token has been received (NAK transmission). * Rev. 3.00 Jan 25, 2006 page 577 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 4 Bit Name Initial Value R/W EP3TF 0 Description Indicates that the endpoint 3 host input transfer has been completed abnormally. 0: Indicates that the endpoint 3 is in a transfer wait state. [Clearing condition] * 0 is written to EP3TF after EP3TF = 1 has been read. 1: Indicates that the endpoint 3 host input transfer (IN transaction) has been completed abnormally. [Setting conditions] * An ACK handshake cannot be achieved after IN token has been received and data has been transferred. Data cannot be sent because the FIFO is empty after an IN token has been received (NAK transmission). R/(W)* Endpoint 3 Transfer Failure Flag * 3 EP2TF 0 R/(W)* Endpoint 2 Transfer Failure Flag Indicates that the endpoint 2 host input or output transfer has been completed abnormally. 0: Indicates that the endpoint 2 is in a transfer wait state. [Clearing condition] * 0 is written to EP2TF after EP2TF = 1 has been read. 1: Indicates that the endpoint 2 host input transfer (IN transaction) or output transfer (OUT transaction) has been completed abnormally. [Setting conditions] * An ACK handshake cannot be achieved after IN token has been received and data has been transferred. Data cannot be sent because the FIFO is empty after an IN token has been received (NAK transmission). Data cannot be received because the FIFO is full after an OUT token has been received (NAK transmission). A communication error occurs after the OUT token has been received. * * * Rev. 3.00 Jan 25, 2006 page 578 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 Bit Name Initial Value R/W EP1TF 0 Description Indicates that the endpoint 1 host input transfer has been completed abnormally. 0: Indicates that the endpoint 1 is in a transfer wait state. [Clearing condition] * 0 is written to EP1TF after EP1TF = 1 has been read. 1: Indicates that the endpoint 1 host input transfer (IN transaction) has been completed abnormally. [Setting conditions] * An ACK handshake cannot be achieved after an IN token has been received and data has been transferred. Data cannot be sent because the FIFO is empty after an IN token has been received (NAK transmission). R/(W)* Endpoint 1 Transfer Failure Flag * 1 EP0ITF 0 R/(W)* Endpoint 0 Transfer Failure Flag Indicates that the endpoint 0 host input transfer has been completed abnormally. 0: Indicates that the endpoint 0 is in a transfer wait state. [Clearing conditions] * * 0 is written to EP0ITF after EP0ITF = 1 has been read. Endpoint 0 has received a SETUP token. 1: Indicates that the endpoint 0 host input transfer (IN transaction) has been completed abnormally. [Setting conditions] * An ACK handshake cannot be achieved after an IN token has been received and data has been transferred. Data cannot be sent because the FIFO is empty after an IN token has been received (NAK transmission). * Rev. 3.00 Jan 25, 2006 page 579 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 0 Bit Name Initial Value R/W EP0OTF 0 Description Indicates that the endpoint 0 host output transfer has been completed abnormally. Endpoint 0 host output transfer has two transactions: OUT transaction and SETUP transaction. Data transmission in these transactions are the same, but flag handling in these transactions differ. Since most of the commands sent by a SETUP transaction are processed in the USB function core, the EP0OTS flag in TSFR0 is not set and the EP0OTF flag is set to 1. For a command that cannot be processed in the USB core, the EP0OTS flag is set to 1. Note that neither the EP0OTS nor the EP0OTF flag is set to 1 if the SEICNT bit in USBMDCR is set to 1 regardless of whether the command can be processed in the USB core or not. 0: Indicates that the endpoint 0 is in a transfer wait state. [Clearing conditions] * * 0 is written to EP0OTF after EP0OTF = 1 has been read. Endpoint 0 has received a SETUP token. R/(W)* Endpoint 0 Host Output Transfer Failure Flag 1: Indicates that the endpoint 0 host output transfer (OUT transaction or SETUP transaction) has been completed abnormally. [Setting conditions] * * * * Data cannot be sent because the FIFO is full after an OUT token has been received. Data cannot be sent because EP0OTC = 0 after an OUT token has been received (NAK transmission). A communication error occurs after the OUT token has been received. A received command can be processed in the USB function core (only when the SETICNT bit is cleared to 0) after a SETUP token has been received. Note: * Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 580 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.11 USB Control /Status Register 0 (USBCSR0) USBCSR0 controls the operation of the USB function core. USBCSR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit Bit Name Initial Value R/W All 0 R R/W Description Reserved These bits are always read as 0 and cannot be modified. 3 EP0STOP 0 Endpoint 0 Stop Used to protect the contents of endpoint 0 FIFO in the USB function core. Setting this bit to 1 protects the data that is sent to the EP0 OUT-FIFO by a SETUP transaction. 0: Indicates that the EP0 OUT-FIFO and specific FIFO is in an operating state. [Clearing conditions] * * System reset Function software reset 7 to 4 -- 1: Indicates that the EP0 OUT-FIFO is in a read stop state. [Setting conditions] * FVSR0O contents are not changed by reading EPDR0O. Indicates that the EP0 specific FIFO is in a write or transfer stop state. * * FIFO contents are not changed by writing to EPDR0I. FVSR0I contents are not changed by setting EP0ITE. Rev. 3.00 Jan 25, 2006 page 581 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 Bit Name Initial Value R/W EPIVLD 0 Description Enables USB function core operation. To enable the USB function core operation, endpoint information must be specified. After a system reset or function software reset, the USB function core has no endpoint information. Endpoint information of the USB function core in this LSI can be set by writing to EPDR0I sequentially (for details, see section 18.4.7, USB Module Startup Sequence). By setting this bit to 1 after writing all data in EPDR0I, endpoint information written to the USB function core becomes valid. 0: Indicates that endpoint information (EPINFO) is not specified. [Clearing conditions] * * System reset Function software reset R/(W)* Endpoint Information Valid 1: Indicates that endpoint information (EPINFO) is specified. Rev. 3.00 Jan 25, 2006 page 582 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 1 Bit Name Initial Value R/W EP0OTC 0 R/W Description Endpoint 0O Transfer Control Controls the USB function core endpoint 0 control transfer. Clearing this bit to 0 disables the write to the EP0 OUT-FIFO. This generates a transfer abnormal completion interrupt. A change in the direction of data transfer in the control transfer can be detected by this interrupt. In control transfer, a command is first received in a SETUP transaction (setup stage), data is then transferred in an OUT transaction or IN transaction (data stage), and a handshake is finally transferred in an IN transaction or OUT transaction (status stage). This bit is set to 1 when a SETUP token is received and command data reception is then enabled after FVSR initialization. This bit is cleared to 0 after a command data has been received to protect the EP0 OUT-FIFO contents. If the received command cannot be processed in the USB function core, the EP0OTS flag in TSFR0 is set to 1 and the slave CPU must analyze the command. After command analysis, if an OUT transaction is performed at the data stage, the slave CPU must set this bit to 1 to prepare the OUT transaction; if an IN transaction is performed at the data stage, the slave CPU leaves this bit cleared to 0. If the host CPU initiates an OUT transaction at the status stage, the EP0OTF flag in TFFR0 is set to 1 to generate a transfer abnormal completion interrupt. Therefore, the slave CPU can acknowledge the completion of the data stage. By the interrupt, the slave CPU sets this bit to 1 to receive status stage data that is retransferred. 0: Indicates that EP0 OUT-FIFO is in a write stop state. (The following write to the EP0 OUT-FIFO is disabled.) [Clearing conditions] * System reset * Function software reset * Command data reception in SETUP transaction (EP0OTS flag is set) 1: Indicates that EP0 OUT-FIFO is in an operating state [Setting conditions] * A SETUP token has been received. * 0 is written to EP0OTC after EP0OTC = 1 has been read. Rev. 3.00 Jan 25, 2006 page 583 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 0 Note: Bit Name Initial Value R/W -- * 0 R/(W) Description Reserved The initial value should not be changed. Writing of 0 is disabled. 18.3.12 Endpoint Stall Register 0 (EPSTLR0) EPSTLR0 stalls the USB function core endpoints. Endpoints whose EPSTL bits are set to 1 respond by a STALL handshake when a transaction has been initiated by receiving a token from the host. A stall state (STALL handshake is used to respond) can be set from both the USB function core and the host. A stall state can be cancelled only from the host. The stall state is specified in the USB function core internal bit. This internal bit can be set or cleared by the SetFeature/Clear Feature command of the host. If STALL handshaking is performed because the EPSTL bit is set to 1, the internal bit of the USB function core is also set to a stall state. Even if the host clears the USB function core internal bit, this internal bit remains to be set to a stall state until the corresponding EPSTL bit is set to 1. EPSTLR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). EPSTLR0 Bit 7 6 Bit Name Initial Value R/W -- EP5STL 0 0 R R/W Description Reserved This bit is always read as 0 and cannot be modified. Endpoint 5 Stall Sets endpoint 5 in a stall state. 0: Endpoint 5 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) * STALL handshake response of endpoint 5 is performed. 1: Endpoint 5 is in a stall state. [Clearing condition] (SCME = 1) * 1 is written to EP5STL after EP5STL = 0 has been read. Rev. 3.00 Jan 25, 2006 page 584 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 5 Bit Name Initial Value R/W EP4STL 0 R/W Description Endpoint 5 Stall Sets endpoint 5 in a stall state. 0: Endpoint 5 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) * STALL handshake response of endpoint 5 is performed. 1: Endpoint 5 is in a stall state. [Clearing condition] (SCME = 1) * 4 EP3STL 0 R/W 1 is written to EP5STL after EP5STL = 0 has been read. Endpoint 4 Stall Sets endpoint 4 in a stall state. 0: Endpoint 4 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) * STALL handshake response of endpoint 4 is performed. 1: Endpoint 4 is in a stall state. [Clearing condition] (SCME = 1) * 3 EP2STL 0 R/W 1 is written to EP4STL after EP4STL = 0 has been read. Endpoint 3 Stall Sets endpoint 3 in a stall state. 0: Endpoint 3 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) * STALL handshake response of endpoint 3 is performed. 1: Endpoint 3 is in a stall state. [Clearing condition] (SCME = 1) * 1 is written to EP3STL after EP3STL = 0 has been read. Rev. 3.00 Jan 25, 2006 page 585 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 Bit Name Initial Value R/W EP1STL 0 R/W Description Endpoint 2 Stall Sets endpoint 2 in a stall state. 0: Endpoint 2 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] (SCME = 1) * STALL handshake response of endpoint 2 is performed. 1: Endpoint 2 is in a stall state. [Clearing condition] (SCME = 1) * 1 0 -- EP0STL 0 0 R 1 is written to EP2STL after EP2STL = 0 has been read. Reserved This bit is always read as 0 and cannot be modified. R/(W)* Endpoint 0 Stall Sets endpoint 0 in a stall state. 0: Endpoint 0 is in an operating state. (Stall state can be cancelled by the ClearFeature command) [Clearing condition] * Endpoint 0 receives a SETUP token. 1: Endpoint 0 is in a stall state. [Setting condition] * 1 is written to EP0STL after EP0STL = 0 has been read. Note: * Writing of 0 is disabled. Rev. 3.00 Jan 25, 2006 page 586 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.13 Endpoint Reset Register 0 (EPRSTR0) EPRSTR0 resets the FIFO pointers for each USB function core endpoint. Bit 7 6 Bit Name Initial Value R/W -- EP5RST 0 0 R Description Reserved This bit is always read as 0 and cannot be modified. * Endpoint 5 Reset R/(W) Initializes endpoint 5 FIFO. 0: Normal read value 1: A command to reset the endpoint 5 FIFO is issued to the RFU 5 EP4RST 0 R/(W)* Endpoint 4 Reset Initializes endpoint 4 FIFO. 0: Normal read value 1: A command to reset the endpoint 4 FIFO is issued to the RFU 4 EP3RST 0 R/(W)* Endpoint 3 Reset Initializes endpoint 3 FIFO. 0: Normal read value 1: FVSR3 is initialized to H'0008 3 EP2RST 0 R/(W)* Endpoint 2 Reset Initializes endpoint 2 FIFO. 0: Normal read value 1: FVSR2 is initialized to H'0000 (when EP2DIR = 0) FVSR2 is initialized to H'0010 (when EP2DIR = 1) Rev. 3.00 Jan 25, 2006 page 587 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 Bit Name Initial Value R/W EP1RST 0 Description Initializes endpoint 1 FIFO. 0: Normal read value 1: FVSR1 is initialized to H'0010 (EP1 FIFO size is 16 bytes) FVSR1 is initialized to H'0020 (EP1 FIFO size is 32 bytes) 1 EP0IRST 0 R/(W)* Endpoint 0I Reset Initializes endpoint 0I FIFO. 0: Normal read value 0 EP0ORST 0 1: FVSR0I is initialized to H'0010 * Endpoint 0O Reset R/(W) Initializes endpoint 0O FIFO. 0: Normal read value 1: FVSR0O is initialized to H'0000 Note: * Only 1 can be written. R/(W)* Endpoint 1 Reset Rev. 3.00 Jan 25, 2006 page 588 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.14 Device Resume Register (DEVRSMR) DEVRSMR has a flag that shows whether remote wakeup is enabled or disabled and a bit that controls remote wakeup of the USB function core suspend state. DEVRSMR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 to 2 1 Bit Name Initial Value R/W -- RMUPS All 0 0 R R Description Reserved These bits are always read as 0 and cannot be modified. Remote Wakeup Status Indicates whether USB function core remote wakeup is enabled or disabled. Remote wakeup can only be enabled or disabled by a command issued from the host. 0: Remote wakeup disabled 1: Remote wakeup enabled 0 DVR 0 R/(W)* Device Resume Cancels the suspend state. 0: Normal read value 1: Cancels the suspend state (remote wakeup) Note: * Only 1 can be written. Rev. 3.00 Jan 25, 2006 page 589 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.15 Interrupt Source Select Register 0 (INTSELR0) INTSELR0 selects USBIB interrupt and USBIC interrupt sources for the USB module. INTSELR0 is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 Bit Name Initial Value R/W TSELB 0 R/W Description Transfer Select B Combined with the EPIBS2 to EPIBS0 bits, selects a USBIB interrupt source. 0: Requests a USBIB interrupt by a TS flag interrupt in USBIFR0 and specifies a TS flag interrupt source endpoint by the EPIBS2 to EPIBS0 bits. 1: Requests a USBIB interrupt by a TF flag interrupt in USBIFR0 and specifies a TF flag interrupt source endpoint by the EPIBS2 to EPIBS0 bits. 6 5 4 EPIBS2 EPIBS1 EPIBS0 0 0 0 R/W R/W R/W Interrupt B Endpoint Select 2 to 0 Combined with the TSELB bit, selects a USBIB interrupt source. 000: Selects no endpoint 001: Selects endpoint 1 010: Selects endpoint 2 011: Selects endpoint 3 100: Selects endpoint 4 101: Selects endpoint 5 11X: Setting prohibited 3 TSELC 0 R/W Transfer Select C Combined with EPICS2 to EPICS0 bits, selects a USBIC interrupt source. 0: Requests a USBIC interrupt by a TS flag interrupt in USBIFR0 and specifies a TS flag interrupt source endpoint by the EPICS2 to EPICS0 bits. 1: Requests a USBIC interrupt by a TF flag interrupt in USBIFR0 and specifies a TF flag interrupt source endpoint by the EPICS2 to EPICS0 bits. Rev. 3.00 Jan 25, 2006 page 590 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 2 1 0 Bit Name Initial Value R/W EPICS2 EPICS1 EPICS0 0 0 0 R/W R/W R/W Description Interrupt C Endpoint Select 2 to 0 Combined with the TSELC bit, selects a USBIC interrupt source. 000: Selects no endpoint 001: Selects endpoint 1 010: Selects endpoint 2 011: Selects endpoint 3 100: Selects endpoint 4 101: Selects endpoint 5 11X: Setting prohibited Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 591 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.16 USB Control Registers 0 and 1 (USBCR0, USBCR1) USBCR0 selects the USB module data input/output method and controls the operation states and reset states of each unit. USBCR1 controls clock supply to the bus driver/receiver and USB function core. USBCR0 is initialized to H'7F by a system reset. USBCR1 is initialized to H'00 by a system reset. USBCR0 Bit 7 Bit Name Initial Value R/W FADSEL 0 R/W Description Function Input/Output Analog 1 Digital Selection Selects the USB module data input/output method. 0: Selects the USDP and USDM pins as USB module data input/output. 1: Multiplexes the control input/output of the driver/receiver that is compatible with PDIUSBP11A manufactured by Philips Electronics with port 6 pins and selects it as USB module data input/output (see table 18.3). 6, 5 4 -- UIFRST All 1 1 R R/W Reserved These bits are always read as 1 and cannot be modified. USB Interface Software Reset Resets EP4PKTSZR, EPSZR1, USBIER0, USBIER1, USBMDCR, EPDIR0, and INTSELR0. 0: Sets the above registers in operating state. 1: Sets the above registers in reset state. 3, 2 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 592 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 1 Bit Name Initial Value R/W FPLLRST 1 R/W Description Function PLL Software Reset Resets the USB bus clock circuit (DPLL) in the USB function core. Setting this bit to 1 resets the DPLL in the USB function core and stops bus clock synchronization. Clear this bit to 0 after the PLL operation is stabilized. 0: Sets DPLL in operating state. 1: Sets DPLL in reset state. 0 FSRST 1 R/W Function Core Internal State Software Reset Resets the internal state of the USB function core. Setting this bit 1 to 1 initializes all the internal states of the USB function core other than the bus clock circuit (DPLL). Clear this bit to 0 after the DPLL operation is stabilized. A function software reset is defined as the state where both the FSRST and UIFRST bits are set to 1. 0: Sets USB function core other than DPLL in operating state. 1: Sets USB function core other than DPLL in reset state. Rev. 3.00 Jan 25, 2006 page 593 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USBCR1 Bit 7 to 2 1 Bit Name Initial Value R/W -- VBUSS All 0 0 R R/W Description Reserved These bits are always read as 0 and cannot be modified. VBUS Status Prevents bus driver/receiver feedthrough current from generating by controlling the VBUS line (USB cable) connection state. The VBUS status monitor circuit must be designed by using the external interrupt and general ports. In addition, external pull-up resistors must be turned ON or OFF by using the general ports. 0: Prevents feedthrough current from generating by disconnecting VBUS. The USDP and USDM pins are placed in highimpedance state. 1: VBUS connection. The USDP and USDM pins are pulled up and pulled down, respectively. 0 CK48READY 0 R/W CK48READY Controls the bus clock (48 MHz) supply to the USB function core. To stop or start up the PLL operation correctly in suspend or resume state, the bus clock supply must be stopped before stopping the PLL circuit, and the bus clock supply must be restarted after the PLL operation is stabilized. 0: Disables the bus clock supply to the USB function core 1: Enables the bus clock supply to the USB function core Rev. 3.00 Jan 25, 2006 page 594 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Table 18.3 Port 6 Functions Port 6 P67 (DPLS) P66 (DMNS) P65 (XVERDATA) P64 (TXDPLS) P63 (TXDMNS) P62 (TXENL) P61 (SUSPEND) P60 (SPEED) Control I/O of Driver/Receiver Compatible with PDIUSBP11A by Philips Electronics Input Input Input Output Output Output Output Output VP VM RCV VPO VMO OE SUSPEND SPEED Differential input (+) Differential input (-) Data input Differential input (+) Differential input (-) Output enable Suspend specification Speed specification (Fixed to high for 12-Mbps specifications) 18.3.17 USB PLL Control Register (UPLLCR) UPLLCR controls the generation method of the USB function core operating clock. UPLLCR is initialized to H'01 by a system reset. Rev. 3.00 Jan 25, 2006 page 595 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Bit 7, 6 5 Bit Name Initial Value R/W -- PFSEL2 All 0 0 R R/W Description Reserved These bits are always read as 0 and cannot be modified. PLL Frequency Select 2 Combined with the PFSEL1 and PFSEL0 bits, this bit selects the frequency of the clock to be provided to the USB operating clock generation circuit (PLL). For details, refer to the description of the PFSEL1 and PFSEL0 bits. 4 3 2 CKSEL2 CKSEL1 CKSEL0 0 0 0 R/W R/W R/W Clock Source Select 2 to 0 These bits select the source of the clock to be provided to the USB operating clock generation circuit (PLL). 0XX: PLL stops operation and no clock is input to the PLL. 100: Setting prohibited 101: PLL stops operation and the USEXCL pin input (48 MHz) is directly used instead of PLL output. 110: PLL operates using the system clock generator (XTAL) as a clock source. 111: PLL operates using the USEXCL pin input as a clock source. 1 0 PFSEL1 PFSEL0 0 1 R/W R/W PLL Frequency Select 1 and 0 The PFSEL2 to PFSEL0 bits select the frequency of the clock to be provided to the USB operating clock generation circuit (PLL). The PLL circuit generates a 48-MHz USB operating clock based on the clock source whose frequency is specified by the PFSEL1 and PFSEL2 bits. 000: PLL input clock frequency is 8 MHz 001: PLL input clock frequency is 12 MHz 010: PLL input clock frequency is 16 MHz 011: PLL input clock frequency is 20 MHz 100: PLL input clock frequency is 24 MHz Other than above: Setting prohibited Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 596 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.18 Configuration Value Register (CONFV) CONFV stores the configuration, interface, and alternation values selected by the host by using the SetConfiguration and SetInterface command. CONFV is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). CONFV Bit 7, 6 5 4 3 2 1 0 Bit Name Initial Value R/W -- CONFV0 INTV1 INTV0 ALTV2 ALTV1 ALTV0 All 0 0 0 0 0 0 0 R R R R R R R Alternate Value Description Reserved These bits are always read as 0 and cannot be modified. Configuration Value Interface Value Rev. 3.00 Jan 25, 2006 page 597 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.19 Endpoint 4 Packet Size Register (EP4PKTSZR) EP4PKTSZR specifies the MaxPacketSize for endpoint 4. In this LSI, only 64 bytes can be specified as MaxPacketSize. Endpoint 4 receives transmit data from the RFU. The packet size of endpoint 4 is controlled by the USB module and transmit data is transferred from the RFU until the number of transmit data bytes reaches the value specified in EP4PKTSZR. EP4PKTSZR is initialized to H'40 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 0 1 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description EP4 Maximum Packet Size Only H'40 (64 bytes) can be specified; other settings are prohibited. Rev. 3.00 Jan 25, 2006 page 598 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.20 RFU/FIFO Read Request Flag Register (UDTRFR) UDTRFR provides a flag indicating that endpoint 5 is placed in data transfer completion state. Endpoint 5 has a 2-byte receive buffer in the USB module to temporarily store data received from the host into the receive buffer before transferring it to the RAM-FIFO by the RFU. The receive buffer holds the receive data until the RFU data transfer ends. If the RAM-FIFO is full, the transaction may be completed normally even while receive data of one or two bytes still remain in the receive buffer. At this time, the EP5TS bit in TSFR0 is not set to 1 and the EP5UDTR bit is set to 1. By clearing the EP5UDTR bit to 0 when there is a space of at least two bytes in the RAM-FIFO, data in the receive buffer is transferred to the RAM-FIFO, and the EP5TS bit is set to 1 after transfer completes. In the slave CPU, a space of at least two bytes must be secured in the RAM-FIFO and the EP5UDTR bit must be cleared to 0 by an UDTR interrupt. UDTRFR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit Bit Name Initial Value R/W All 0 R R/(W) Description Reserved These bits are always read as 0 and cannot be modified. 0 EP5UDTR 0 Endpoint 5 RFU/FIFO Read Request Flag 0: Indicates that endpoint 5 receive buffer is empty 1: Indicates that endpoint 5 holds [Clearing condition] * 0 is written to EP5UDTR after EP5UDTR = 1 has been read. USB transfer has been completed normally while the RAM-FIFO is full and the receive buffer holds data. 7 to 1 -- [Setting condition] * Rev. 3.00 Jan 25, 2006 page 599 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.21 USB Mode Control Register (USBMDCR) USBMDCR controls SETUP transaction operations and stall cancellation procedures. USBMDCR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB Control Registers 0 and 1 (USBCR0, USBCR1)). Bit 7 to 2 1 Bit Name Initial Value R/W -- SCME All 0 0 R R/W Description Reserved These bits are always read as 0 and cannot be modified. Stall Cancellation Mode Enable Specifies the auto-clear function of the EPSTL bit in EPSTLR0. 0: Does not specify the auto-clear function of the EPSTL bit 1: Specifies the auto-clear function of the EPSTL bit corresponding to the endpoint that responds to a STALL handshaking 0 SETICNT 0 R/W Setup Interrupt Control Specifies the FIFO handling methods in SETUP transaction and interrupt control. 0: FIFO is used for EP0O and EP0I, and a SETUP transaction uses EP0O. An USBIA interrupt is used and its priority is specified as the highest. 1: FIFO is used for EP0O, EP0I, and EP0S, and a SETUP transaction uses EP0S. An USBIA interrupt is used and its priority is specified as the lowest. Rev. 3.00 Jan 25, 2006 page 600 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.3.22 USB Port Control Register (UPRTCR), and USB Test Registers 0 and 1 (UTESTR0 and UTESTR1) UPRTCR, UTESTR0, and UTESTR1 are used for testing. Note that values other than initial values must not be set to UPRTCR, UTESTR0, and UTESTR1. UPRTCR, UTESTR0, and UTESTR1 are initialized to H'00 by a system reset. UPRTCR, UTESTR0, and UTESTR1 are not initialized in software standby mode. UPRTCR Bit Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0 and cannot be modified. 2 1 0 PCNMD2 PCNMD1 PCNMD0 0 0 0 R/(W) R/(W) R/(W) Test Mode Setting Initial values must not be modified. 7 to 3 -- UTESTR0 Bit 8 Bit Name TEST8 Initial Value R/W All 0 R/(W) Description Test Mode Setting Initial values must not be modified. 15 to TEST15 to UTESTR1 Bit 7 to 0 Bit Name TEST7 to TEST0 Initial Value R/W All 0 R/(W) Description Test Mode Setting Initial values must not be modified. Rev. 3.00 Jan 25, 2006 page 601 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.4 Operation The USB is an interface for personal computer peripheral devices and is defined by the USB standard Rev. 1.1. The USB module in this LSI operates based on the USB standard Rev. 1.1. 18.4.1 USB Function Core Functions The USB function core has five endpoints. The USB function core can select three alternate specifications from a combination of endpoint 2 enable/disable and IN/OUT, and the maximum packet size (MaxPacketSize) of endpoint 1. Configuration 1 Alternate Specification 0 1 2 Endpoint 0 IN/OUT IN/OUT FIFO 16 bytes for each Endpoint 1 IN/OUT IN FIFO 16 bytes Endpoint 2 IN/OUT IN OUT IN 32 bytes None FIFO 16 bytes 16 bytes None Interface 0 Configuration 1 Interface 1 Alternate Specification 0 Endpoint 3 IN/OUT IN FIFO 8 bytes Endpoint 4 IN/OUT IN FIFO 2048 bytes (Maximum) Endpoint 5 IN/OUT OUT FIFO 2048 bytes (Maximum) The USB function core supports a control transfer by endpoint 0, interrupt transfer by endpoints 1 to 3, and bulk transfer by endpoints 4 and 5. A control transfer is comprised of multiple transactions. In a SETUP transaction, a command sent from the host is first decoded in the USB function core. When a SETUP token has been received, FVS0O and FVSR0I are initialized, the EP0OTC bit is set to 1 and command reception is enabled. If a USB standard command other than GetDescriptor or SetDescriptor is received, the SETUPF and EP0OTF flags are set to 1 and the USB standard command reception is informed to the slave CPU (when SETICNT = 0). In this case, the remaining transactions of the control transfer are processed in the USB function core and the slave CPU performs no operations. On the other hand, if a GetDescriptor or SetDescriptor command or device class specific command is received, the SETUPF and EP0OTS flags are set to 1 (when SETICNT=0). The slave Rev. 3.00 Jan 25, 2006 page 602 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) CPU must read, interpret and execute a command from the FIFO. The slave CPU must process the remaining transactions of a control transfer using FIFOs. When the SETICNT bit is set to 1, the FIFO for EP0S is used and the SETUPF flag is set only when a GetDescriptor, SetDescriptor, or device class specific command is received. An interrupt transfer is comprised of a single IN or OUT transaction. The slave CPU must process an interrupt transfer using FIFOs. A bulk transfer is comprised of a single IN or OUT transaction. Transfer data is directly transferred between on-chip RAM and USB modules by the RFU. As described above, the USB module performs communication processing using both the USB function core and slave CPU as required. Table 18.4 shows the USB function core and slave CPU functions and the registers, flags, and bits used for interface. Table 18.4 USB Function Core and Slave CPU Functions No. Function 1 Analog digital conversion of the USDP/USDM signal Serial parallel conversion/ bit staffing, PID check/addition, CRC check/addition Token packet check/SETUP notification to the slave CPU Handshake packet check/generation DATA0/1 PID toggle, FIFO rewind, ACK/NAC detection/return ACK handshake detection, notification to the slave CPU/ACK handshake return Data error detection, notification to the slave CPU/NAK handshake return STALL handshake return 5 6 Data packet reception/generation/transfer between the USB function slave CPU core USB command interpretation and execution USB function core, slave CPU Operating Hardware Port unit USB function core USB function core USB function core USB function core -- SETUPF, TS, EPTS, TF, EPTF FVSR, EPTE, RFU Related Registers, Flags, and Bits -- 2 3 4 TS, EPTS TF, EPTF EPSTL FIFO, RFU FIFO, RFU Rev. 3.00 Jan 25, 2006 page 603 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) The bus driver/receiver on the port unit and the USB function core process the electrical signal and signal bit stream on the USB bus line. The token, acknowledge type, and data byte are extracted, and the acknowledge and data byte are converted to electrical signals of the bit stream (no. 1 and 2 in table 18.4). In a SETUP token reception, if a GetDescriptor or SetDescriptor command or a device class specific command is received, the SETUP and EP0OTS flags are set to 1 and SETUP token reception is informed to the slave CPU (no. 3 in table 18.4). The received command must be transferred using the FIFO and be interpreted and processed in the slave CPU (no. 6 in table 18.4). The remaining transactions in the control transfer must also be processed in the slave CPU using FIFOs (no. 4 and 5 in table 18.4). In a control transfer, interrupt transfer, and bulk transfer, an IN or OUT token reception is not informed to the CPU and data transfer is performed continuously. In an IN transaction, transmit data is prepared in the FIFO in advance and transmission is initiated if the EPTE bit is set; otherwise a NAK handshaking is performed. After an IN transaction has been completed, transfer normal completion or abnormal completion is determined by the host handshaking and this result is informed to the CPU through the TS and TF bits in USBIFR0, the EPTS bit in TSFR0, and the EPTF bit in TFFR0. In an OUT transaction, an ACK handshaking is performed if the FIFO has received all data items; otherwise an NAK handshaking is performed. In an IN or OUT transaction, a STALL handshaking is performed if the endpoint is specified as a STALL state by EPSTL. 18.4.2 Operation on Receiving a SETUP Token (Endpoint 0) Transactions sequentially initiated when the host has received a SETUP token are called control transfer. The control transfer is comprised of three stages: setup, data, and status stages. The control transfer includes two transfer types: control write transfer and control read transfer. The transfer type such as control write or read transfer and the number of bytes to be transferred in the data stage are determined by the 8-byte command transferred by an OUT transaction in setup stage. The setup stage comprises a SETUP transaction. The data stage comprises no transaction or one or multiple data transactions. The status stage comprises a data transaction. Table 18.5 shows the packets included in each transaction. Rev. 3.00 Jan 25, 2006 page 604 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Table 18.5 Packets Included in Each Transaction Stage Setup stage Control write transfer Data stage Token Phase SETUP token packet OUT token packet Data Phase OUT data packet (8 bytes) (host to slave) OUT data packet (host to slave) 2 IN data packet (0 bytes) * Handshake Phase* 1 ACK handshake packet (slave to host) ACK/NAK/STALL handshake packet (slave to host) ACK handshake packet (host to slave) -- Status stage IN token packet (slave to host) NAK/STALL handshake packet (slave to host) Control read transfer Data stage IN token packet IN data packet (slave to host) NAK/STALL handshake packet (slave to host) ACK handshake packet (host to slave) -- Status stage OUT token packet No data stage Status stage IN token packet OUT data packet (host to slave) 2 IN data packet (0 bytes) * ACK/NAK/STALL handshake packet (slave to host) ACK handshake packet (host to slave) -- (slave to host) NAK/STALL handshake packet (slave to host) Notes: 1. This phase exists only when a data packet has been transferred in the data phase. 2. If the FIFO is empty after all data items in the FIFO have been transferred, the EPTE bit is cleared to 0. If an IN transaction is initiated at this time, a NAK handshake is returned. To transfer a 0-byte data packet, set the EPTE bit to 1 while the FIFO is empty. Figures 18.2 to 18.5 show the USB function core and LSI firmware operations when the USB function core receives a SETUP token (SETUP transaction). Rev. 3.00 Jan 25, 2006 page 605 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP token packet Receive a SETUP token packet Automatically set each flag*1 Request an USBIA interrupt (SETUP) Initiate the USBIA interrupt processing Read USBIFR0*2 Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP0O FIFO Store the information indicating that the decode is performed by the EP0OTS interrupt to be generated in the following sequence in user memory Command data decode Check if decode by the slave CPU is required or not Receive an ACK handshake packet Send ACK to the host CPU Clear the SETUPF bit of USBIFR0 to 0 Send NAK to the slave CPU Do not modify FVSR0O Request an USBID interrupt (EP0OTF) Complete the USBIA interrupt processing Initiate the USBID interrupt processing Read USBIFR0 and check the TF interrupt occurrence Read TFFR0 and check the EP0OTF interrupt occurrence Check if the command decode by the slave CPU is required or not and modify the information to be stored in user memory Clear the EP0OTF bit of TFFR0 to 0 Complete the USBID interrupt processing Notes: 1. Set the EP0OTC bit of USECSR0 to 1, initialize FVSR0I and FVSR0O, clear the EP0ITS and EP0OTS bits of TSFR0 to 0, clear the EP0ITF and EP0OTF bits of TFFR0 to 0, and clear the EP0STL bit of EPSTLR0 to 0. 2. Since a USBIA interrupt is only assigned to a SETUP interrupt, interrupt source determination process is not required. Figure 18.2 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is not Required and When SETICNT = 0) Rev. 3.00 Jan 25, 2006 page 606 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP token packet Receive a SETUP token packet Automatically set each flag*1 Request an USBIA interrupt (SETUP) Initiate the USBIA interrupt processing Read USBIFR0*2 Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP0O FIFO Command data decode Check if decode by the slave CPU is required or not Send ACK to the host CPU Send ACK to the slave CPU Store the information indicating that the decode must be performed by the EP0OTS interrupt to be generated in the following sequence in user memory Receive an ACK handshake packet Clear the SETUPF bit of USBIFR0 to 0 Modify FVSR0O Clear EP0OTC bit of USBCSR0 to 0 Request an USBID interrupt (EP0OTF) Complete the USBIA interrupt processing Initiate the USBID interrupt processing Read USBIFR0 and check the TS interrupt occurrence Read TSFR0 and check the EP0OTS interrupt occurrence Check if the command decode by the slave CPU is required by the stored information Read FVSR0O and check if the EP0 FIFO contains 8-byte data Modify FVSR0O Read EPDR0O Check the instruction by data decode If the instruction is Control-OUT, set the EP0OTC bit of USBCSR0 to 1 (write 1 to EP0OTC after EP0OTC = 1 was read) Clear the EP0OTS bit of TSFR0 to 0 Complete the USBID interrupt processing Notes: 1. Set the EP0OTC bit of USECSR0 to 1, initialize FVSR0I and FVSR0O, clear the EP0ITS and EP0OTS bits of TSFR0 to 0, clear the EP0ITF and EP0OTF bits of TFFR to 0, and clear the EP0STL bit of EPSTLR0 to 0. 2. Since a USBIA interrupt is only assigned to a SETUP interrupt, interrupt source determination process is not required. Figure 18.3 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Required and When SETICNT = 0) Rev. 3.00 Jan 25, 2006 page 607 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP token packet Receive a SETUP token packet Automatically set each flag* Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP0S FIFO Command data decode Check if decode by the slave CPU is required or not Receive an ACK handshake packet Send ACK to the host CPU Send ACK to the slave CPU Do not modify FVSR0S Note: * Set the EP0OTC bit of USECSR0 to 1, initialize FVSR0S, FVSR0I, and FVSR0O, clear the EP0ITS and EP0OTS bits of TSFR0 to 0, clear the EP0ITF and EP0OTF bits of TFFR0 to 0, and clear the EP0STL bit of EPSTLR0 to 0. Figure 18.4 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Not Required and When SETICNT = 1) Rev. 3.00 Jan 25, 2006 page 608 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send a SETUP token packet Receive a SETUP token packet Automatically set each flag*1 Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP0S FIFO Command data decode Check if decode by the slave CPU is required or not Receive an ACK handshake packet Send ACK to the host Send ACK to the slave CPU Modify FVSR0S Request an USBIA interrupt (SETUPF) Initiate the USBIA interrupt processing Read USBIFR0*2 Read FVSR0S and check if the EP0S FIFO contains 8-byte data Read EPDR0S Check the instruction by data decode Set the EP0OTC bit of USBCSR0 to 1 (write 1 to EP0OTC after EP0OTC = 1 was read) Clear the SETUPF bit of USBIFR0 to 0 Complete the USBIA interrupt processing Notes: 1. Set the EP0OTC bit of USECSR0 to 1, initialize FVSR0S, FVSR0I, and FVSR0O, clear the EP0ITS and EP0OTS bits of TSFR0 to 0, clear the EP0ITF and EP0OTF bits of TFFR0 to 0, and clear the EP0STL bit of EPSTLR0 to 0. 2. Since a USBIA interrupt is only assigned to a SETUP interrupt, interrupt source determination process is not required. Figure 18.5 Operation on Receiving a SETUP Token (When Decode by the Slave CPU Is Required and When SETICNT = 1) Rev. 3.00 Jan 25, 2006 page 609 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.4.3 Operation on Receiving an OUT Token (Endpoints 0, 2, and 5) Figures 18.6 to 18.9 show the USB function core and LSI firmware operations when the USB function core receives an OUT token (OUT transaction). An OUT transaction is used for data stage and status stage of control transfer, interrupt transfer, and bulk transfer. USB Host USB Function Core Core Interface Slave CPU Send an OUT token packet Receive an OUT token packet Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP2 FIFO Receive an ACK handshake packet Send ACK to the host Send ACK to the slave CPU Modify FVSR2 Request an USBID interrupt (EP2TS) Initiate the USBID interrupt processing Read USBIFR0 and check if a TS interrupt occurs or not Read TSFR0 and check if an EP2TS interrupt occurs or not Read FVSR2 and check if the EP2 FIFO contains 8-byte data Modify FVSR2 Read EPDR2 Clear the EP2TS bit of TSFR0 to 0 Complete the USBID interrupt processing Note: * When an EP2TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) Figure 18.6 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Empty) Rev. 3.00 Jan 25, 2006 page 610 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT token packet Receive an OUT token packet Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Disable data write because the EP2 FIFO is full Restore FVSR2 Receive a NAK handshake packet Send NAK to the host CPU Send NAK to the slave CPU Request an USBID interrupt (EP2TF)*1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TFFR0 and check if an EP2TF interrupt occurs or not Re-transmission Send an OUT token packet Receive an OUT token packet Modify FVSR2 Read FVSR2 and read EP2 FIFO data from EPDR2 Send an OUT data packet (8 bytes) Receive an OUT data packet (8 bytes) Write data to EP2 FIFO Clear the EP2TF bit of TFFR0 to 0 Receive an ACK handshake packet Send ACK to the host CPU Complete the USBID interrupt processing Send ACK to the slave CPU Modify FVSR2 Request an USBID interrupt (EP2TS)*2 Initiate the USBID interrupt processing The following procedure is the same as that when the initial FIFO is empty. Notes: 1. When an EP2TF interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TFFR0 must be accessed to clear the flags.) 2. When an EP2TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) Figure 18.7 Operation on Receiving an OUT Token (EP2-OUT: Initial FIFO Is Full) Rev. 3.00 Jan 25, 2006 page 611 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT token packet Receive an OUT token packet Send an OUT data packet (64 bytes) Receive an OUT data packet (64 bytes) Write data to the EP5 receive buffer Request RFU transmission Read the receive buffer, write data to RAM-FIFO, and send ACK Receive an ACK handshake packet Send ACK to the host Send ACK to the slave CPU Request to modify the RFU pointer Modify the RFU pointer and send ACK Request an USBID interrupt (EP5TS)*1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TS interrupt occurs or not Read TSFR0 and check if an EP5TS interrupt occurs or not Read the RFU pointer and check if the EP5 RAM-FIFO contains 64-byte data Process RAM-FIFO data Modify the RFU pointer*2 Clear the EP5TS bit of TSFR0 to 0 Complete the USBID interrupt processing Notes: 1. When an EP5TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) 2. If the RAM-FIFO size is increased (defined as larger size), the pointer need not be modified after each data processing. Figure 18.8 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Empty) Rev. 3.00 Jan 25, 2006 page 612 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an OUT token packet Receive an OUT token packet Send an OUT data packet (64 bytes) Receive an OUT data packet (64 bytes) Write data to the EP5 receive buffer Request RFU transmission A RAM-FIFO full error occurs Receive a NAK handshake packet Send NAK to the host CPU A RAM-FIFO full error occurs Request to rewind the RFU pointer Send NAK to the slave CPU Rewind the RFU pointer and send ACK Request an USBID interrupt (EP5TF)*1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TFFR0 and check if an EP5TF interrupt occurs or not Read data and modify the RFU pointer Re-transmission Send an OUT token packet Receive an OUT token packet Clear the EP5TF bit of TFFR0 to 0 Send an OUT data packet (64bytes) Receive an OUT data packet (64 bytes) Write data to the EP5 receive buffer Request RFU transmission Complete the USBID interrupt processing Write data to RAM-FIFO and send ACK Receive an ACK handshake packet Send ACK to the host CPU Request to modify the RFU pointer Modify the RFU pointer and send ACK Send ACK to the slave CPU Request an USBID interrupt (EP5TS)*2 Initiate the USBID interrupt processing The following procedure is the same as that when the initial FIFO is empty. Notes: 1. When an EP5TF interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TFFR0 must be accessed to clear the flags.) 2. When an EP5TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) Figure 18.9 Operation on Receiving an OUT Token (EP5-OUT: Initial FIFO Is Full) Rev. 3.00 Jan 25, 2006 page 613 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.4.4 Operation on Receiving an IN Token (Endpoints 0, 1, 2, 3 and 4) Figures 18.10 to 18.13 show the USB function core and LSI firmware operations when the USB function core receives an IN token (IN transaction). An IN transaction is used for data stage and status stage of control transfer, interrupt transfer, and bulk transfer. USB Host USB Function Core Core Interface Slave CPU Send an IN token packet Receive an IN token packet Receive an IN data packet (8 bytes) Send an IN data packet (8 bytes) Read data from EP2 FIFO Send an ACK handshake packet Receive ACK Send ACK to the slave CPU Modify FVSR2 Request an USBID interrupt (EP2TS)* Initiate the USBID interrupt processing Read USBIFR0 and check if a TS interrupt occurs or not Read TSFR0 and check if an EP2TS interrupt occurs or not Read FVSR2 and write data to EPDR2 for the number of bytes which can be written to the EP2 FIFO Write data to the EP2 FIFO Modify FVSR2 and enable data transmission Set the EP2TE bit of PTTER0 to 1 Clear the EP2TS bit of TSFR0 to 0 Complete the USBID interrupt processing Note: * When an EP2TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) When a NAK handshake is received from the host, FVSR2 must be rewound to generate an EP2TF interrupt. This EP2TF interrupt must be handled in the same way as when an IN token is received while the FIFO is empty since an EP2TF interrupt caused by a NAK handshake and that caused by an IN token are difficult to be distinguished. Figure 18.10 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Full) Rev. 3.00 Jan 25, 2006 page 614 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Disable data read because the EP2 FIFO is empty Slave CPU Send an IN token packet Receive a NAK handshake packet Receive an IN token packet Send NAK to the host CPU Send NAK to the slave CPU Request an USBID interrupt (EP2TF)*1 Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TFFR0 and check if an EP2TF interrupt occurs or not Read FVSR2 and write data to EPDR2 for the number of bytes which can be written to the EP2 FIFO Set the EP2TE bit of PTTER0 to 1 Clear the EP2TF bit of TFFR0 to 0 Complete the USBID interrupt processing Write data to the EP2 FIFO Re-transmission Receive an IN token packet Modify FVSR2 and enable data transmission Read data from the EP2 FIFO Send an IN token packet Receive an IN data packet (8 bytes) Receive an ACK handshake packet Receive an IN data packet (8 bytes) Receive ACK Send ACK to the slave CPU Modify FVSR2 Request an USBID interrupt (EP2TS)*2 Initiate the USBID interrupt processing The following procedure is the same as that when the initial FIFO is full. Notes: 1. When an EP2TF interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TFFR0 must be accessed to clear the flags.) 2. When an EP2TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) Figure 18.11 Operation on Receiving an IN Token (EP2-IN: Initial FIFO Is Empty) Rev. 3.00 Jan 25, 2006 page 615 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Host USB Function Core Core Interface Slave CPU Send an IN token packet Receive an IN token packet Receive an IN data packet (64 bytes) Send an IN data packet (64 bytes) Read data from the EP4 transmission buffer Request the RFU transmission Read the RAM-FIFO, send ACK, and write to the transmit buffer Send an ACK handshake packet Receive ACK Send ACK to the slave CPU Request to modify the RFU pointer Modify the RFU pointer and send ACK Request a USBID interrupt (EP4TS)* Initiate the USBID interrupt processing Read USBIFR0 and check if a TS interrupt occurs or not Read TSFR0 and check if an EP4TS interrupt occurs or not Read the RFU pointer and write data to EP4 RAM-FIFO for the number of bytes which can be written to, and modify the RFU pointer Write data to the EP4 transmission buffer (pre-read) and request the RFU transmission Set the EP4TE bit of PTTER0 to 1 Clear the EP2TS bit of TSFR0 to 0 Complete the USBID interrupt processing Read the RAM-FIFO, send ACK, and write to the transmit buffer Note: * When an EP4TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) When a NAK handshake is received from the host, the RFU pointer must be rewound to generate an EP4TF interrupt. This EP4TF interrupt must be handled in the same way as when an IN token is received while the FIFO is empty since an EP4TF interrupt caused by a NAK handshake and that caused by an IN token are difficult to be distinguished. Setting the EP4TE bit to 1 to generate data write (pre-read) to the transmit buffer is necessary. Figure 18.12 Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Full) Rev. 3.00 Jan 25, 2006 page 616 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Function Core Core Interface USB Host Slave CPU Send an IN token packet Receive an IN token packet Disable data read because the EP4 transmit buffer is empty Receive a NAK handshake packet Send NAK to the host CPU Initiate the USBID interrupt processing Read USBIFR0 and check if a TF interrupt occurs or not Read TSFR0 and check if an EP2TF interrupt occurs or not Read the RFU pointer, write data to EP4 RAM-FIFO for the number of bytes which can be written to, and modify the RFU pointer Write data to the EP4 transmit buffer (pre-read) and request the RFU transmission Receive an IN token packet Set the EP4TE bit of PTTER0 to 1 Clear the EP4TF bit of TFSR0 to 0 Complete the USBID interrupt processing Read the RAM-FIFO, send ACK, and write to the transmit buffer Modify the RFU pointer and send ACK Initiate the USBID interrupt processing The following procedure is the same as that when the initial FIFO is full. Send NAK to the slave CPU Request an USBID interrupt (EP4TF)*1 Re-transmission Send an IN token packet Receive an IN data packet (64 bytes) Send an IN data packet (64 bytes) Read data from the EP4 transmit buffer Request RFU transmission Send an ACK handshake packet Receive ACK Send ACK to the slave CPU Modify the RFU pointer Request an USBID interrupt (EP4TS)*2 Notes: 1. When an EP4TF interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TFFR0 must be accessed to clear the flags.) 2. When an EP4TS interrupt is specified as a USBIB or USBIC interrupt according to the INTSELR0 setting, the corresponding interrupt occurs. In this case, if a USBIB or USBIC interrupt occurs, interrupt source determination process is not required. (Note that TSFR0 must be accessed to clear the flags.) Figure 18.13 Operation on Receiving an IN Token (EP4-IN: Initial FIFO Is Empty) Rev. 3.00 Jan 25, 2006 page 617 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.4.5 Suspend/Resume Operation The USB function core automatically enters a suspend state if the USB data line is placed in an idle state for a time equal to or greater than that specified by the USB standard Rev. 1.1. A suspend state is automatically cancelled (resumed) when the upstream (host) resumes data transfer. A suspend state can also be forcibly cancelled (resumed) by the USB function (remote wakeup). Suspend state and resume state transitions can be detected by the SPNDIF and SPNDOF flags. A SPNDOF interrupt can be accepted by waking up this LSI even if the LSI is placed in software standby mode. In this case, the oscillator and PLL circuit must be started up according to the startup sequence. Whether remote wakeup is enabled or not is checked by the RWUPS flag of DEVRSMR. If remote wakeup is enabled, remote wakeup is performed by setting the DVR bit of DEVRSMR to 1. 18.4.6 USB Module Reset and Operation Stop Modes The USB module can be placed in a reset state or operation stop mode by using multiple control bits. To startup the USB module by sequentially specifying these control bits, refer to section 18.4.7, USB Module Startup Sequence. The USB supports the following reset and operating stop states. Hardware standby and reset states initializes the entire USB module. In each register description, initialization conditions are not described and only initial values are shown. 1. Hardware standby mode 2. Reset state 3. Module stop mode 4. Software standby mode 5. USB bus reset state 6. USB suspend state Hardware Standby Mode: Hardware standby mode is entered by bringing the STBY pin of the LSI to low. In hardware standby mode, registers that can be initialized and the internal status of the LSI are initialized and all pins of the LSI are placed in a high impedance state. XTAL-EXTAL system clock oscillation stops in the clock pulse generator. Rev. 3.00 Jan 25, 2006 page 618 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Reset State: A reset state is entered by bringing the RES pin of the LSI to low. In a reset state, registers that can be initialized and the internal status of the LSI are initialized and all pins of the LSI are placed in input state. XTAL-EXTAL system clock oscillation can be continued in the clock pulse generator. Module Stop Mode: The USB module enters module stop mode when the SMSTPB1 bit in subchip module stop control register BL (SUBMSTPBL) is set to 1. In a module stop mode, the system clock supply to the USB module stops. Note that supply of the USB operating clock (48 MHz) does not stop so, the USB module continues operation. To place the USB module in a module stop mode, initialize the USBCR1 and UPLLCR. In addition, it is recommended that USBCR0 should be initialized to prepare a module stop mode cancellation. Since the module stop bit of SUBMSTPCR is initialized to 1 in hardware standby mode or by a reset, the USB module is placed in a module stop mode after reset cancellation. Software Standby Mode: Software standby mode is entered if the SLEEP instruction is executed while the SSBY bit of SBYCR is set to 1. In software standby mode, the USB module is not placed in a reset or operation stop state. Note that if the slave CPU stops operation in software standby mode, the USB function core operation may not be performed completely. To specify software standby mode regardless of the host status, set the UIFRST, FPLLRST, and FSRST bits of USBCR0 to 1 to stop the USB module operation before software standby mode is entered. Due to this, the registers shown in table 18.6 are initialized. In this case, external pull-up MOSs must be specified to be in a cable disconnected state. These descriptions also apply to watch mode, subactive mode, and subsleep mode. Table 18.6 Registers Initialized by Bit UIFRST or FSRST Register Name EPDR3, EPDR2, EPDR1, EPDR0S, EPDR0O, EPDR0I FVSR3, FVSR2, FVSR1, FVSR0S, FVSR0O, FVSR0I EPSZR1 USBIER0, USBIER1 USBIFR0, USBIFR1, TSFR0, TFFR0, UDTRFR, CONFV USBCSR0, DEVRSMR, EPSTLR0 EPDIR0 INTSELR0, EP4PKTSZR, USBMDCR UIFRST/FSRST FSRST FSRST UIFRST UIFRST FSRST FSRST UIFRST UIFRST When the host enters a suspend state, software standby mode in which the host waits for cancellation (resume) can be specified. Rev. 3.00 Jan 25, 2006 page 619 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) USB Bus Reset State: When a new device is connected to the USB bus or when en error recovery process is executed, the USDP/USDM pin is placed in a bus reset state for a specific period. In the USB module, the bus reset interrupt flag is set to 1 when a USB bus reset is detected. The USB module internal status and control registers that select the USB module operating state are not initialized by a USB bus reset. Registers must be initialized individually as required. When the USB function core is initialized by the FSRST bit in USBCR0, endpoint information (EPINFO) and bus reset detection information of the USB function core are also initialized. Therefore, initialization by the FSRST or UIFRST bit in USBCR0 should not be performed in the bus reset interrupt processing. USB Suspend State: The USB function core enters a suspend state when the USB bus is placed in an idle state for a specific period. In a suspend state, power consumption can be reduced by stopping the PLL circuit after clearing the CK48READY bit in USBCR1 to 0. A suspend state combined with a low-power consumption mode can effectively reduce the power consumption while the system is not in operation. When the USB function core enters a suspend state or when the suspend state is cancelled by the signal change on the USDP/USDM pin, the suspend IN and OUT interrupt flags are set to 1, respectively. An SPNDOF interrupt can be accepted by waking up this LSI even if this LSI is placed in software standby mode. Rev. 3.00 Jan 25, 2006 page 620 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.4.7 USB Module Startup Sequence USB Module Configuration: The USB module is comprised of several components. To correctly operate these components and notify the host, the USB module must be started up by the firmware (this LSI's program) according to the sequence described later. The USB module is comprised of: * USB clock external input pin, USB operating clock PLL (48 MHz) * USB bus clock synchronization DPLL (12 MHz) * EPINFO: Endpoint information * Slave CPU, core interface * USB function core (a) USB clock external input pin, USB operating clock PLL circuit The PLL circuit that generates the USB operating clock multiplies the clock input from the USB clock external input pin or the oscillator to generate a 48-MHz clock. Therefore, the clock input to the PLL circuit must be 8, 12, 16, 20, or 24 MHz. The multiplication rate of the PLL circuit can be specified by the PFSEL bit in UPLLCR. The 48-MHz clock generated by the PLL circuit can be divided to generate a 24-MHz clock. This 24-MHz clock can be used as the system clock. For USB operation clock PLL stabilization time, set the UIFRST, PFLLRST, and FSRST bits of the USBCR0 to 1 to place the USB bus clock synchronization DPLL and USB function core in a reset state. (b) USB bus clock synchronization DPLL (12 MHz) The USB data is transferred at 12 Mbps (maximum). The bit data is sampled at the timing using the 48-MHz USB operating clock and the phase is adjusted while the synchronization pattern is received prior to the packet. This mechanism is called the USB bus clock synchronization DPLL. The USB bus clock synchronization DPLL stabilization time is defined by firmware. For the USB bus clock synchronization DPLL stabilization time, set the FSRST bit of USBCR0 to 1 to place the USB function core in a reset state. It is recommended that the USB bus clock synchronization DPLL stabilization time should be 10 cycles or more in a 48-MHz clock. Rev. 3.00 Jan 25, 2006 page 621 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) (c) EPINFO: Endpoint information The USB function core of this LSI can support isochronous transfer. However, due to the CPU interface specifications, the USB function core of this LSI handles only control transfer, interrupt transfer, and bulk transfer. At each USB function core initialization, the firmware writes endpoint information (EPINFO) such as the number of endpoints and their corresponding transfer type, maximum packet size (bytes) to the USB function core. This LSI prepares three alternatives that can be written in EPINFO. Table 18.7 shows the endpoint information (EPINFO) that can be written in the USB function core. A total of 65 bytes (A1, A2, ..., A5, B1, B2, ..., M4, M5) must be written to EDPR0I in this order. Table 18.7 Endpoint Information 1 A B C D E F G H I J K L M H'00 H'14 H'24 H'14 H'24 H'14 H'35 H'45 H'55 H'65 H'36 H'46 H'56 2 H'00 H'38 H'38 H'78 H'70 H'B8 H'20 H'20 H'20 H'20 H'20 H'20 H'20 3 H'11 H'10 H'10 H'10 H'10 H'20 H'10 H'10 H'10 H'10 H'10 H'10 H'10 4 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 5 H'00 H'01 H'02 H'01 H'02 H'01 H'03 H'04 H'05 H'06 H'03 H'04 H'05 (d) Slave CPU, core interface The slave CPU and core interface are the basic components for firmware execution. The slave CPU starts operating immediately after a reset is cancelled. The core interface, however, can be accessed after module stop mode is cancelled. (e) USB function core The USB function core is the main component of the USB interface. The USB bus interface can be achieved if all components described in (a) to (d) operate correctly. Rev. 3.00 Jan 25, 2006 page 622 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) Initialization Sequence: The USB module is initialized in the sequence shown in figure 18.14. 1. The LSI is placed in a power off state or hardware standby mode. 2. Turn the power on, apply a high level to the STBY pin, and finally apply a high level to the RES pin to initiate the LSI operation. 3. Check the VBUS line (USB cable) by firmware. 4. Cancel module stop mode of the USB module by firmware. 5. Set the VBUSS bit in USBCR1 to 1 by firmware. 6. Specify UPLLCR by firmware and wait for USB operating clock PLL stabilization time (3 ms). 7. Set the CK48READY bit in USBCR1 to 1 by firmware. 8. Clear the UIFRST bit in USBCR0 to 0 by firmware and specify the USB module related registers. 9. Clear the FPLLRST bit in USBCR0 to 0 by firmware. 10. After the DPLL operation stabilization time has passed, clear the FSRST bit in USBCSR0 to 0 by firmware. 11. Write EPINFO to the USB function core and set the EPIVLD bit in USBCR0 to 1 by firmware. 12. Specify external pull-up resistors to be connected by firmware. 13. Wait for a bus reset interrupt . * * The host executes the bus reset. The host configures the USB function core. The USB function core initiates operation. Rev. 3.00 Jan 25, 2006 page 623 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) External Event, Host USB Function Core Core Interface Slave CPU Start system operation Cancel reset (RES = 1) Check if the USB cable is connected Cancel the module stop state of the USB module Set the VBUSS bit of USBCR1 to 1 Start USB operating clock oscillation Set UPLLCR Wait for the PLL stabilization time (3 ms) Supply the USB operating clock Set the CK48READY bit of USBCR1 to 1 Clear the UIFRST bit of USBCR0 to 0 Set the USB function core to operate Write to the USB function core control registers Start DPLL operation Clear the FPLLRST bit of USBCR0 to 0 Wait for the DPLL stabilization time Cancel the USB function core reset Clear the FSRST bit of USBCR0 to 0 Set EPINFO Write EPINFO to EPDR0I and set the EPIVLD bit of USBCSR0 to 1 Check if a new device is connected Externally pull up the USDP pin Receive a bus reset signal Set the BRSTF bit of USBIFR0 to 1 Send a bus reset signal Process a bus reset Request an USBID interrupt (BRSTF) Initiate the USBID interrupt processing Read USBIFR0 and check if a BRSTF interrupt occurs or not Complete the USBID interrupt processing Figure 18.14 Operation Procedure for Initializing USB Module Rev. 3.00 Jan 25, 2006 page 624 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.5 Interrupt Sources The USB module's slave CPU interrupts are USBIA, USBIB, UABIC, and USBID interrupts. Tables 18.8 and 18.9 show interrupt sources and their priorities. Interrupt sources are interrupt flags of USBIRF0, USBIFR1, TSFR0, TFFR0, and UDTRFR. Each interrupt can be enabled or disabled according to each interrupt enable bit of USBIER0 and USBIER1. Before initiating the USBID interrupt process routine, the interrupt source must be determined by reading USBIRF0, USBIFR1, TSFR0, TFFR0, and UDTRFR. The USBIA, USBIB, UABIC, and USBID interrupts can be used as DTC activation interrupt sources. Table 18.8 USB Interrupt Sources (When SETICNT of USBMDCR Is 0) Interrupt Source USBI0 USBI1 USBI2 USBI3 USBIA USBIB USBIC USBID Description An interrupt by SETUP An interrupt by EPTS or EPTF of the endpoint specified by INTSELR0 An interrupt by EPTS or EPTF of the endpoint specified by INTSELR0 An interrupt by SOF, SPND, BRST, TS, TF, UDTR, SETI, or SETC DTC Activation Possible Possible Possible Possible Low Priority High Table 18.9 USB Interrupt Sources (When SETICNT of USBMDCR Is 1) Interrupt Source USBI0 USBI1 USBI2 USBI3 USBIB USBIC USBID USBIA Description An interrupt by EPTS or EPTF of the endpoint specified by INTSELR0 An interrupt by EPTS or EPTF of the endpoint specified by INTSELR0 An interrupt by SOF, SPND, BRST, TS, TF, UDTR, SETI, or SETC An interrupt by SETUP DTC Activation Possible Possible Possible Possible Low Priority High Rev. 3.00 Jan 25, 2006 page 625 of 872 REJ09B0286-0300 Section 18 Universal Serial Bus Interface (USB) 18.6 Usage Notes 1. When activating the DTC by a USB interrupt source, correct operation is not guaranteed if the DISEL bit in DTC mode register B (MRB) is cleared to 0. Be sure to set the DISEL bit to before DTC activation. 2. USB module operation can be enabled or disabled by the SMSTPB1 bit in subchip module stop control register BL (SUBMSTPBL). In the initial state, USB module operation is enabled. The USB module registers can be accessed by clearing module stop mode. 3. It is not recommended to use the USB simultaneously with the A/D converter or D/A converter because the bus driver/receiver power supply pin DrVCC/DrVSS is shared with the analog power supply pin AVCC/AVSS. Rev. 3.00 Jan 25, 2006 page 626 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Section 19 Multimedia Card Interface (MCIF) This LSI supports a multimedia card (MultiMediaCardTM*1, hereafter referred to as MMC) interface (MCIF)*2. The MCIF has two operating modes: MultiMediaCard mode (hereafter referred to as MMC mode) and SPI mode. The MCIF is a clocked-synchronous serial interface that transmits/receives data that is distinguished in terms of command and response. A number of command/responses are predefined in the MMC. As the MCIF specifies a command code and command type/response type upon the issuance of a command, additional commands can be supported in future within the range of combinations of currently defined command types/response types. The command system of the MMC supports a command extension function specific for the application. The MCIF also supports commands extended by the secure multimedia card (Secure-MultiMediaCardTM*1, hereafter referred to as Secure-MMC). Notes: 1. MultiMediaCardTM is a trademark of Infineon Technologies AG. Secure-MultiMediaCardTM is a multimedia card with a content protection function. 2. Supports a multimedia card that conforms to the MultiMediaCard System Specification Version 2.11. SPI mode is not supported in a multimedia card that conforms to the MultiMediaCard System Specification Version 3.1. 19.1 Features * Two operating modes: MMC mode and SPI mode * Two MMCs can be inserted in SPI mode (two chip select outputs) * 20-Mbps bit rate (max) (system clock of 20 MHz) * Supports MMC commands including the Secure-MMC * RAM-FIFO by the RFU can be used * Three interrupt sources: FIFO empty/full, command/response/data transfer complete, and transfer error MMC mode: * Interface via the MCCLK pin (transfer clock output) pin, MCCMD pin (command transmission/response reception) , and MCDAT pin (data transmission/reception) * Monitor output function of the MCCMD and MCDAT pin input/output status Rev. 3.00 Jan 25, 2006 page 627 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) SPI mode: * Interface via the MCCLK pin (transfer clock output) , MCTxD pin (command transmission/data transmission) , MCRxD pin (response reception/data transmission) and MCCSA and MCCSB pins (chip select) for each MMC. Internal data bus Module data bus Command transmission/ response reception control CMDR0 to CMDR5 RSPR0 to RSPR16 CMDTYR RSPTYR CMDSTRT CTOCR RFU request RFU interface Data transmission/ reception control RSPRD OPCR TBCR TBNCR DTOUTR Internal interrupt Interrupt control MMC/SPI mode control INTCR0, INTCR1 INTSTR0, INTSTR1 CSTR IOMCR MODER Card clock generator CLKON Legend: TBNCR CMDR0 to 5 : Command registers 0 to 5 : Transfer block number counter DTOUTR RSPR0 to 16 : Response registers 0 to 16 : Data timeout register IOMCR RSPRD : Pin mode control register : Response register D MODER CMDTYR : Mode register : Command type register CLKON RSPTYR : Transfer clock control register : Response type register INTCR0, INTCR1 CMDSTRT : Interrupt control registers 0, 1 : Command start register INTSTR0, INTSTR1 : Interrupt status registers 0, 1 CTOCR : Command timeout control register CSTR OPCR : Card status register : Operation control register TBCR : Transfer byte number count register MCCLK, MCTxD, MCRxD, MCCSA, MCCSB, MCCMD, MCDAT, MCDATDIR, MCCMDDIR : MMC connection signals (see table 19.1) Figure 19.1 Block Diagram of MCIF Rev. 3.00 Jan 25, 2006 page 628 of 872 REJ09B0286-0300 Multimedia card bus interface MCCLK MCTxD MCRxD MCCSA MCCSB MCCMD MCDAT MCDATDIR MCCMDDIR Bus interface Section 19 Multimedia Card Interface (MCIF) 19.2 Input/Output Pins Table 19.1 summarizes the pins of the MCIF. Table 19.1 Pin Configuration Name MCCLK, ExMCCLK MCTxD, ExMCTxD I/O Output Output Function Common clock output pins in MMC mode/SPI mode Command/data output pins in SPI mode These pins are connected to the Data in pin on the MMC side MCRxD, ExMCRxD Input Response/data input pins in SPI mode These pins are connected to the Data out pin on the MMC side MCCSA, ExMCCSA Output Card A selection output pins in SPI mode (activelow signal) These pins are connected to the CS pin on the MMC side MCCSB, ExMCCSB Output Card B selection output pins in SPI mode (activelow signal) These pins are connected to the CS pin on the MMC side MCCMD, ExMCCMD MCDAT, ExMCDAT MCDATDIR, ExMCDATDIR MCCMDDIR, ExMCCMDDIR Input/Output Input/Output Output Output Command output/response input pins in MMC mode Data input/output pins in MMC mode Output pins indicating input/output directions of the MCDAT and ExMCDAT pins Output pins indicating input/output directions of the MCCMD and ExMCCMD pins Rev. 3.00 Jan 25, 2006 page 629 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3 Register Descriptions The MCIF has the following registers. * Mode register (MODER) * Command type register (CMDTYR) * Response type register (RSPTYR) * Transfer byte number count register (TBCR) * Transfer block number counter (TBNCR) * Command registers 0 to 5 (CMDR0 to CMDR5) * Response registers 0 to 16 (RSPR0 to RSPR16) * Response register D (RSPRD) * Command start register (CMDSTRT) * Operation control register (OPCR) * Command timeout control register (CTOCR) * Data timeout register (DTOUTR) * Card status register (CSTR) * Interrupt control registers 0, 1 (INTCR0, INTCR1) * Interrupt status registers 0, 1 (INTSTR0, INTSTR1) * Pin mode control register (IOMCR) * Transfer clock control register (CLKON) Rev. 3.00 Jan 25, 2006 page 630 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.1 Mode Register (MODER) MODER specifies the MCIF operating mode. The two operating modes have different input/output pin functions, usable command types, and command sequence. In each mode, the following sequence should be repeated when the MCIF uses the MMC: Send a command, wait for the end of the command sequence and the end of the data busy state, and send the next command. The series of operations from command sending, command response reception, data transmission/reception, and data response reception is called the command sequence. The command sequence starts from sending a command by setting the START bit in CMDSTRT to 1, and ends when all necessary data transmission/reception and response reception has been completed. The MMC supports the data busy state in which the next command is not accepted to write/erase data to/from the flash memory in the MMC during command sequence execution and after command sequence execution has ended. The data busy state is indicated by a 0 output from the MMC side to the MCDAT pin in MMC mode, and to the MCRxD pin in SPI mode. Bit 7 to 3 2, 1 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. -- SPI All 0 0 R/(W) R/W Reserved The initial value should not be changed. SPI/MMC Mode Specifies the MCIF operating mode. 0: Operates in MMC mode 1: Operates in SPI mode Rev. 3.00 Jan 25, 2006 page 631 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.2 Command Type Register (CMDTYR) CMDTYR specifies the command format in conjunction with RSPTYR. For details, refer to table 19.2. Bit 7, 6 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 5 TY5 0 R/W Specifies multiblock transfer when an extended command is used in SPI mode. Bits TY1 and TY0 should be set to B'01 or B'10. The transfer block size should be set in TBCR, and the number of transfer blocks should be set in TBNCR when a command to specify this bit is used. 4 TY4 0 R/W This bit is set to 1 when the CMD12M command is specified. The CMD12M command can be used only in MMC mode. Bits TY1 and TY0 should be cleared to B'00. Specifies stream transfer. Bits TY1 and TY0 should be set to B'01 or B'10. The stream transfer can be used only in MMC mode. The command sequence of the stream transfer specified by this bit ends when it is aborted by the CMD12M command. 2 TY2 0 R/W Specifies multiblock transfer in MMC mode. Bits TY1 and TY0 should be set to B'01 or B'10. The command sequence of the multiblock transfer specified by this bit ends when it is aborted by the CMD12M command. 1 0 TY1 TY0 0 0 R/W R/W These bits specify the existence and direction of transfer data. 00: A command without data transfer 01: A command with read data reception 10: A command with write data transmission 11: Setting prohibited 3 TY3 0 R/W Rev. 3.00 Jan 25, 2006 page 632 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.3 Response Type Register (RSPTYR) RSPTYR specifies the command format in conjunction with CMDTYR. For details, refer to table 19.2. Bit 7, 6 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. 5 4 RTY5 RTY4 0 0 R/W R/W This bit is specified by the R1b response in MMC mode/SPI mode. Makes settings so that the command response CRC is checked by bit CRC7. Bits RTY2 to RTY0 should be set to B'011, B'100, or B'101. Reserved This bit is always read as 0 and cannot be modified. 2 1 0 RTY2 RTY1 RTY0 0 0 0 R/W R/W R/W These bits specify the number of command response bytes. 000: Command needs no command response 001: Command needs a 1-byte command response (specified by R1 and R1b responses in SPI mode) 010: Command needs a 2-byte command response (specified by R2 response in SPI mode) 011: Command needs a 5-byte command response (specified by R3 response in SPI mode) 100: Command needs a 6-byte command response (specified by R1, R1b, R3, R4, and R5 responses in MMC mode) 101: Command needs a 17-byte command response (specified by R2 response in MMC mode) 11X: Setting prohibited Legend: X: Don't Care 3 -- 0 R Rev. 3.00 Jan 25, 2006 page 633 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Table 19.2 summarizes the correspondence between the commands listed in the MultiMediaCard System Specification Version 2.11 and the settings of CMDTYR and RSPTYR. In MMC mode and SPI mode, the response format is different. Also, in SPI mode, there are commands that require a data response. Table 19.2 Correspondence between Commands and Settings of CMDTYR and RSPTYR Command Index CMD0 CMD1 CMD2M*1 CMD3M* CMD4M* CMD7M* CMD9 CMD10 CMD11M*1 CMD12M*1 CMD13 CMD15M*1 CMD16 CMD17 CMD18M*1 CMD20M*1 CMD24 CMD25M*1 CMD26M*1 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 1 1 1 CMDTYR Abbreviation GO_IDLE_STATE SEND_OP_COND ALL_SEND_CID SET_RELATIVE_ADDR SET_DSR SELECT/DESELECT_CARD SEND_CSD SEND_CID READ_DAT_UNTIL_STOP STOP_TRANSMISSION SEND_STATUS GO_INACTIVE_STATE SET_BLOCKLEN READ_SINGLE_BLOCK READ_MULTIPLE_BLOCK WRITE_DAT_UNTIL_STOP WRITE_SINGLE_BLOCK WRITE_MULTIPLE_BLOCK PROGRAM_CID PROGRAM_CSD SET_WRITE_PROT CLR_WRITE_PROT SEND_WRITE_PROT TAG_SECTOR_START TAG_SECTOR_END UNTAG_SECTOR 2 resp* RSPTYR TY1, TY0 00 00 00 00 00 00 00 00 1 1 1 RTY5 3 RTY2 to RTY4* 2 RTY0* TY5 TY4 TY3 TY2 --/R1 R3/R1 R2 R1 -- R1b R2/R1 R2/R1 R1 R1b R1/R2 -- R1 R1 R1 R1 R1 R1 R1 R1 R1b R1b R1 R1 R1 R1 1 1 1 1 1 000/001 100/001 101 100 000 100 101/001 101/001 1 1 1 1/0 100 100 100/010 000 1/0 1/0 1 1 1/0 1 1 1/0 1 1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 100/001 100/001 100 100 100/001 100 100 100/001 100/001 100/001 100/001 100/001 100/001 100/001 100/001 100/001 100/001 01 00 00 00 00 01 01 10 10 10 10 10 00 00 01 00 00 00 00 00 00 TAG_ERASE_GROUP_START R1 TAG_ERASE_GROUP_END UNTAG_ERASE_GROUP R1 R1 Rev. 3.00 Jan 25, 2006 page 634 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Command Index CMD38 CMD39M*1 CMD40M* CMD42 CMD55 CMD56 CMD58S* CMD59S* 1 1 1 CMDTYR Abbreviation ERASE FAST_IO GO_IRQ_STATE LOCK_UNLOCK APP_CMD GEN_CMD READ_OCR CRC_ON_OFF 2 resp* RSPTYR TY1, TY0 00 00 00 10*2 00 10*2, 01*4 00 00 1 1 RTY5 1 3 RTY2 to RTY4* RTY0*2 TY5 TY4 TY3 TY2 R1b R4 R5 R1b R1 R1b R3 R1 1/0 1 1 1/0 1/0 1/0 100/001 100 100 100/001 100/001 100/001 011 001 Notes: 1. M is added to the end of the command index of commands that are available only in MMC mode. Similarly, S is added to the end of the command index of commands that are available only in SPI mode. 2. If there is a difference between the response types in MMC mode and SPI mode, they are both listed in the resp column with MMC mode preceding SPI mode. Similarly, the difference between the number of response bytes in the two modes is listed in the RTY2 to RTY0 bit columns in the same order. A data response is used in a command for which the TY1 and TY0 bits are set to B'10 in SPI mode. 3. Clear the RTY4 bit to 0 in SPI mode. When this bit is set to 1 in MMC mode, command response CRC can be checked. 4. Can be used as a command with read data. Rev. 3.00 Jan 25, 2006 page 635 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.4 Transfer Byte Number Count Register (TBCR) TBCR specifies the number of bytes to be transferred (block size) for a block transfer command. The block size is the number of data block bytes not including the start bit (byte in SPI mode) and CRC. The multiblock transfer command in MMC mode corresponds to the number of bytes of each data block. This register setting is ignored in the stream transfer command in MMC mode. Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. CS3 CS2 CS1 CS0 0 0 0 0 R/W R/W R/W R/W Transfer Data Block Size 0000: 1 byte 0001: 2 bytes 0010: 4 bytes 0011: 8 bytes 0100: 16 bytes 0101: 32 bytes 0110: 64 bytes 0111: 128 bytes 1000: 256 bytes 1001: 512 bytes 1010: 1024 bytes 1011: 2048 bytes 11XX: Setting prohibited Legend: X: Don't Care 19.3.5 Transfer Block Number Counter (TBNCR) TBNCR sets the number of blocks to be transferred when multiblock transfer is specified by bit TY5 in CMDTYR. The contents of TBNCR is decremented for every 1-block transfer completion. When the contents of TBNCR is 0, the command sequence is terminated, and an interrupt is generated. Bit 15 to 0 Bit Name -- Initial Value All 0 R/W R/W Description Transfer Block Number Counter Rev. 3.00 Jan 25, 2006 page 636 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5) A command is written to CMDR as shown in table 19.3, and a command is transmitted by setting the START bit in CMDSTRT to 1. Table 19.3 CMDR Configuration Register CMDR0 Contents Start bit Host bit Command index of 6 bits Command argument of 32 bits CRC of 7 bits End bit Operation Command index writing Start bit is 0 Host bit is 1 Command argument writing Automatic calculation for CRC End bit is fixed to 1. Initial value: H'00 Initial value : Undefined Always read as H'00 Remarks Initial value: H'00 CMDR1 to CMDR4 CMDR5 CMDR0 Bit 7 6 5 to 0 Bit Name Start Host -- Initial Value 0 0 All 0 R/W R/W R/W R/W Description Start Bit (This bit should be cleared to 0) Transmission Bit (This bit should be set to 1) Command Indexes CMDR1, CMDR2, CMDR3, CMDR4 Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R/W Description Command arguments CMDR5 Bit 7 to 1 0 Bit Name CRC End Initial Value -- -- R/W -- -- Description CRC code (automatic calculation) End bit (fixed to 1) Rev. 3.00 Jan 25, 2006 page 637 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) The RSPR registers are eighteen 8-bit registers. RSPR0 to RSPR16 are command response registers. RSPRD is a data response register that is used in only SPI mode. The number of command response bytes differs according to the command. The number of command response bytes can be specified by RSPTYR in the MCIF. The command response is shifted-in from bit 0 in RSPR16, and shifted to the number of command response bytes x 8 bits. Table 19.4 summarizes the correspondence between the number of command response bytes and valid RSPR register. The data response is shifted-in from bit 0 in RSPRD, and shifted 8 bits only when a command includes write data in SPI mode. For other commands, the data response is not shifted. RSPRD is cleared to H'00 by writing an arbitrary value*1. The initial value of the RSPR registers is H'00. RSPR0 to RSPR16 are simple shift registers. A command response that has been shifted in is not automatically cleared, and is continuously shifted until it is shifted out from bit 7 in RSPR0. To clear unnecessary bytes to H'00, write arbitrary values to each RSPR*2. Notes: 1. Bits 7 to 5 in RSPRD are fixed at 0. 2. Reading the data response from RSPR should be executed after one transfer clock cycle following the DRPI interrupt occurrence. Clearing of RSPR is completed after two transfer clock cycles following the write of arbitrary values. Rev. 3.00 Jan 25, 2006 page 638 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Table 19.4 Correspondence between Number of Command Response Bytes and RSPR Register SPI Mode Response RSPR Register RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 1 Byte in SPI Mode (R1, R1b) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1st byte 2 Bytes in SPI Mode (R2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1st byte 2nd byte 5 Bytes in SPI Mode (R3) -- -- -- -- -- -- -- -- -- -- -- -- 1st byte 2nd byte 3rd byte 4th byte 5th byte MMC Mode Response 6 Bytes in MMC Mode (R1, R1b, R3, R4) -- -- -- -- -- -- -- -- -- -- -- 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 17 Bytes in MMC Mode (R2) 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte 17th byte Rev. 3.00 Jan 25, 2006 page 639 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.8 Command Start Register (CMDSTRT) CMDSTRT triggers the start of command transmission, representing the start of a command sequence. The following operations should be completed before the command sequence starts. * Analysis of prior command response, clearing the command response register write if necessary * Analysis/transfer of receive data of prior command if necessary * Preparation of transmission data of the next command if necessary * Setting of CMDTYR, RSPTYR, TBCR, and TBNCR CMDTYR, RSPTYR, TBCR, and TBNCR should not be changed until the command sequence has ended. * Setting of CMDR0 to CMDR4 CMDR0 to CMDR4 should not be changed until the command sequence has ended (the CWRE flag in CSTR has been reset, or a command transmission end interrupt has been generated). The command sequences are controlled by the sequencers in each MCIF side and MMC side. Normally, these operate synchronously, however, these may temporarily become unsynchronized when an error occurs or when a command is aborted. Take care to set the CMDOFF bit in OPCR, to issue the CMD12 command, and to process an error in MMC mode. A new command sequence should be started after confirming that the command sequences on both the MCIF and MMC sides have ended. Bit 7 to 1 0 Bit Name -- START Initial Value All 0 0 R/W R/(W) R/W Description Reserved The initial value should not be changed. Command Sequence Start Bit Starts command transmission when 1 is written. This bit is always read as 0. [Clearing condition] * Automatically cleared when command transmission starts Rev. 3.00 Jan 25, 2006 page 640 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.9 Operation Control Register (OPCR) OPCR controls command operation abort, and suspends or continues data transfer. Bit 7 Bit Name CMDOFF Initial Value 0 R/W W Description Command Off Always read as 0. Aborts all command operations (MCIF command sequence) when 1 is written after a command is transmitted. Write enable period: From command transmission completion to command sequence end 0: Operation is not affected. 1: Command sequence is forcibly aborted. Byte transfer during transfer is also suspended. After command sequence abort, the transfer clock output resumes if the transfer clock has been halted during the command sequence. 6 5 -- RD_CONTI 0 0 R/(W) W Reserved The initial value should not be changed. Read Continue Read as 1 until resuming read when 1 is written. Otherwise, read as 0. Resumes transfer clock output and read data reception when the transfer clock is halted according to FIFO full or termination of block reading in multiblock read. Write enable period: While MCCLK for read data reception is halted 0: Operation is not affected. 1: Resumes MCCLK output and read data reception. Rev. 3.00 Jan 25, 2006 page 641 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 4 Bit Name DATAEN Initial Value 0 R/W R/W Description Data Enable Read as 1 during data transfer period after 1 is written. Otherwise, read as 0. Starts write data transmission by a command with write data. Resumes transfer clock output and write data transmission when the transfer clock is halted according to FIFO empty or termination of one block writing in multiblock write. Write enable period: * * * After transmission of a command with write data While transfer clock is halted according to FIFO empty When one block writing in multiblock write is terminated 0: Operation is not affected. 1: Starts or resumes transfer clock output and write data transmission. 3 to 0 -- All 0 R/(W) Reserved The initial value should not be changed. The command sequence on the MMC side may be halted according to the status of MMC. Table 19.5 shows the MMC states in which the command sequence is halted. In this case, the command sequence should be aborted by setting the CMDOFF bit to 1 on the MCIF side as required. Table 19.5 Card States in which Command Sequence Is Halted Operating Mode MMC mode Command response Data status Error Status When the error detection bit in the card status (32 bits) in the command response transmitted by the MMC is set. When the error detection bit in the CRC status (3 bits) to be transmitted from the MMC while block data is transmitted to the MMC is set. When the error detection bit in the card status (8 bits) in the command response transmitted by the MMC is set. When the error detection bit in the data response (8 bits) to be transmitted from the MMC while block data is transmitted to the MMC is set. SPI mode Command response Data response Rev. 3.00 Jan 25, 2006 page 642 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) For write data transmission, the contents of the command response and data response should be analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK) output should be temporarily halted according to FIFO full/empty, and it should be resumed when preparation has been completed. For multiblock transfer in MMC mode, the command sequence should be temporarily halted for every block break to select either to continue to the next block or to abort the multiblock transfer command by issuing the CMD12 command, and then the command sequence should be resumed. The transfer clock output is also halted while the command sequence is halted in a multiblock read. To continue to the next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command sequence on the MCIF side. Any temporary halt of the transfer clock is determined one byte before the FIFO becomes full/empty. The DATAEN bit should not be set to 1 when only one byte of data remains in the transmit data FIFO. The receive data FIFO should be read when the FIFO becomes full, and the RD_CONTI bit should be set to 1 after three bytes or more have been read. 19.3.10 Command Timeout Control Register (CTOCR) CTOCR specifies the cycle to generate a timeout for the command response. The counter (CTOUTC), to which the CPU does not have access, counts the transfer clock to monitor the command timeout. The CTOUTC starts counting the transfer clock from the start of command transmission. The CTOUTC stops counting the transfer clock when command response reception has been completed, or when the command sequence has been aborted by setting the CMDOFF bit to 1. When the command response cannot be received, the CTOUTC continues counting the transfer clock, and enters the command timeout error state when the number of transfer clock reaches the number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is set. As the CTOUTC continues counting the transfer clock, the CTERI flag setting condition is repeatedly generated. To perform command timeout error handling, the command sequence should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be cleared to prevent extra-interrupt generation. Rev. 3.00 Jan 25, 2006 page 643 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 7 to 1 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. CTSEL0 0 R/W Command Timeout Select Specifies the number of transfer clocks from command transmission completion to response reception completion. 0: 128 transfer clocks 1: 256 transfer clocks 19.3.11 Data Timeout Register (DTOUTR) DTOUTR specifies the cycle to generate a data timeout. The 16-bit counter (DTOUTC) and a prescaler, to which the CPU does not have access, count the system clock to monitor the data timeout. The prescaler always counts the system clock, and outputs a count pulse for every 10000 system clocks. The DTOUTC starts counting the prescaler output from the start of the command sequence. The DTOUTC is cleared when the command sequence has ended, or when the command sequence has been aborted by setting the CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output. When the command sequence does not end, the DTOUTC continues counting the prescaler output, and enters the data timeout error state when the number of prescaler outputs reaches the number specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1 is set. As the DTOUTC continues counting prescaler output, the DTERI flag setting condition is repeatedly generated. To perform data timeout error handling, the command sequence should be aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent extra-interrupt generation. For a command with data busy status, as the command sequence is terminated before entering the data busy state, data timeout cannot be monitored. Timeout in the data busy state should be monitored by firmware. Bit 15 to 0 Bit Name -- Initial Value All 1 R/W R/W Description Data Timeout Time/10000 Data timeout time can be obtained by system clock cycle x DTOUTR setting value x 10000. Rev. 3.00 Jan 25, 2006 page 644 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.12 Card Status Register (CSTR) CSTR indicates the MCIF status during command sequence execution. Bit 7 Bit Name BUSY Initial Value 0 R/W R Description Command Busy Indicates command execution status. When the CMDOFF bit in OPCR is set to 1, this bit is cleared to 0 because the MCIF command sequence is aborted. 0: Command sequence has ended. 1: Command sequence execution in progress. 6 FIFO_FULL 0 R FIFO Full Indicates whether receive data FIFO full has been detected. 0: Receive data FIFO full is not detected. 1: Receive data FIFO full is detected. After FIFO full detection, this bit is cleared to 0 when resuming to receive read data from the MMC or when the command sequence ends. 5 FIFO_EMPTY 0 R FIFO Empty Indicates whether transmit data FIFO empty has been detected. 0: Transmit data FIFO empty is not detected. 1: Transmit data FIFO empty is detected. After FIFO empty detection, this bit is cleared to 0 when resuming to transmit data to the MMC or when the command sequence ends. 4 CWRE 0 R Command Register Write Enable Indicates whether the CMDR command is being transmitted or has been transmitted. 0: The CMDR command has been transmitted, or the START bit in CMDSTRT has not been set yet, so the new command can be written. 1: The CMDR command is waiting for transmission or is being transmitted. If the new command is written, a malfunction will result. Rev. 3.00 Jan 25, 2006 page 645 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 3 Bit Name DTBUSY Initial Value 0 R/W R Description Data Busy Indicates command execution status. Indicates that the MMC is in the busy state during or after the command sequence of a command without data transfer, which includes the busy state in the response, or of a command with write data has been ended. 0: Idle state waiting for a command, or command sequence execution in progress 1: MMC indicates data busy after command sequence ends. 2 DTBUSY_TU -- R Data Busy Pin Status Monitors level of the MCDAT pin in MMC mode or MCRxD pin in SPI mode. This bit is monitored to confirm whether the MMC is in busy state by deselecting the MMC in busy state, and then selecting the MMC, again. 1 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 0 REQ 0 R Interrupt Request Indicates whether an interrupt is requested. An interrupt request is the logical sum of the INTSTR0 and INTSTR1 flags. The INTSTR0 and INTSTR1 flags are set by the enable bits in INTCR0 and INTCR1. 0: No interrupts requested. 1: An interrupt is requested. Rev. 3.00 Jan 25, 2006 page 646 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1) The INTCR registers enable or disable an interrupt. INTCR0 Bit 7 Bit Name FEIE Initial Value 0 R/W R/W Description FIFO Empty Interrupt Enable When this bit is set to 1 while the INTRQ0E bit is 1, the data FIFO empty interrupt request is enabled. 6 FFIE 0 R/W FIFO Full Interrupt Enable When this bit is set to 1 while the INTRQ0E bit is 1, the receive data FIFO full interrupt request is enabled. 5 DRPIE 0 R/W Data Response Interrupt Enable When this bit is set to 1 in SPI mode with the INTRQ1E bit as 1, the data response interrupt request is enabled. 4 DTIE 0 R/W Data Transfer End Interrupt Enable When this bit is set to 1 while the INTRQ1E bit is 1, the data transfer end interrupt request is enabled. 3 CRPIE 0 R/W Command Response End Interrupt Enable When this bit is set to 1 while the INTRQ1E bit is 1, the command response end interrupt request is enabled. 2 CMDIE 0 R/W Command Transmission End Interrupt Enable When this bit is set to 1 while the INTRQ1E bit is 1, the command transmission end interrupt request is enabled. 1 DBSYIE 0 R/W Data Busy End Interrupt Enable When this bit is set to 1 while the INTRQ1E bit is 1, the data busy end interrupt request is enabled. 0 BTIE 0 R/W Multiblock Transfer End Interrupt Enable When this bit is set to 1 with the INTRQ1E bit as 1, the multiblock transfer end interrupt request is enabled. Rev. 3.00 Jan 25, 2006 page 647 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) INTCR1 Bit 7 Bit Name INTRQ2E Initial Value 0 R/W R/W Description Source 2 Interrupt Enable 0: Disables MCIF2 interrupt to the CPU. 1: Enables MCIF2 interrupt to the CPU. 6 INTRQ1E 0 R/W Source 1 Interrupt Enable 0: Disables MCIF1 interrupt to the CPU. 1: Enables MCIF1 interrupt to the CPU. 5 INTRQ0E 0 R/W Source 0 Interrupt Enable 0: Disables MCIF0 interrupt to the CPU. 1: Enables MCIF0 interrupt to the CPU. 4, 3 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 2 CRCERIE 0 R/W CRC Error Interrupt Enable When this bit is set to 1 while the INTRQ2E bit is 1, the CRC error interrupt request is enabled. 1 DTERIE 0 R/W Data Timeout Error Interrupt Enable When this bit is set to 1 while the INTRQ2E bit is 1, the data timeout error interrupt request is enabled. 0 CTERIE 0 R/W Command Timeout Error Interrupt Enable When this bit is set to 1 while the INTRQ2E bit is 1, the command timeout error interrupt request is enabled. Rev. 3.00 Jan 25, 2006 page 648 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1) The INTSTR registers enable or disable the MCIFI0 to MCIFI2 interrupt requests of MCIF. INTSTR0 Bit 7 Bit Name FEI Initial Value 0 R/W R/(W)* Description FIFO Empty Interrupt Flag 0: No interrupts 1: MCIFI0 interrupt requested. [Setting condition] * When transmit data FIFO becomes empty while FEIE = 1 in INTCR0 (when the FIFO_EMPTY bit in CSTR is set) Write 0 after reading FEI = 1. [Clearing condition] * 6 FFI 0 R/(W)* FIFO Full Interrupt Flag 0: No interrupts 1: MCIFI0 interrupt requested. [Setting condition] * When receive data FIFO becomes full while FFIE = 1 in INTCR0 (when the FIFO_FULL bit in CSTR is set) Write 0 after reading FFI = 1. [Clearing condition] * 5 DRPI 0 R/(W)* Data Response Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * If DRPIE = 1 in INTCR0, when CRC status (in MMC mode) or data response (in SPI mode) is received from the MMC after single-block transmission. Write 0 after reading DRPI = 1. [Clearing condition] * Rev. 3.00 Jan 25, 2006 page 649 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 4 Bit Name DTI Initial Value 0 R/W R/(W)* Description Data Transfer End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * When the number of bytes of data transfer specified in TBCR ends while DTIE = 1 in INTCR0. Write 0 after reading DTI = 1. [Clearing condition] * 3 CRPI 0 R/(W)* Command Response End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * When command response reception ends while CRPIE = 1 in INTCR0. Write 0 after reading CRPI = 1. [Clearing condition] * 2 CMDI 0 R/(W)* Command Transmission End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * When command transmission ends while CMDIE = 1 in INTCR0. (When the CWRE bit in CSTR is cleared.) Write 0 after reading CMDI = 1. [Clearing condition] * Rev. 3.00 Jan 25, 2006 page 650 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 1 Bit Name DBSYI Initial Value 0 R/W R/(W)* Description Data Busy End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * When data busy state ends while DBSYIE = 1 in INTCR0. (When the DTBUSY bit in CSTR is cleared.) Write 0 after reading DBSYI = 1. [Clearing condition] * 0 BTI 0 R/(W)* Multiblock Transfer End Interrupt Flag 0: No interrupts 1: MCIFI1 interrupt requested. [Setting condition] * When the number of bytes of data transfer specified in TBCR ends after TBNCR has been decremented to 0 by the extension command (multiblock transfer) in SPI mode while BTIE = 1 in INTCR0. Write 0 after reading BTI = 1. [Clearing condition] * Note: * Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 651 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) INTSTR1 Bit 7 to 3 2 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and cannot be modified. CRCERI 0 R/(W)* CRC Error Interrupt Flag 0: No interrupts 1: MCIFI2 interrupt requested. [Setting condition] * When a CRC error for command response or receive data, and status error (CRC error) for transmission data response is detected while CRCERIE = 1 in INTCR1. For the command response, CRC should be checked when the RTY4 bit in RSPTYR is enabled. [Clearing condition] * 1 DTERI 0 R/(W)* Write 0 after reading CRCERI = 1. Data Timeout Error Interrupt Flag 0: No interrupts 1: MCIFI2 interrupt requested. [Setting condition] * When a data timeout error specified in DTOUTR occurs while DTERIE = 1 in INTCR1. Write 0 after reading DTERI = 1. [Clearing condition] * 0 CTERI 0 R/(W)* Command Timeout Error Interrupt Flag 0: No interrupts 1: MCIFI2 interrupt requested. [Setting condition] * When a command timeout error specified in CTOCR occurs while CTERIE = 1 in INTCR1. Write 0 after reading CTERI = 1. [Clearing condition] * Note: * Only 0 can be written to clear the flag. Rev. 3.00 Jan 25, 2006 page 652 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.3.15 Pin Mode Control Register (IOMCR) IOMCR controls chip select pin operation in SPI mode and input/output direction output pin operation in MMC mode. Bit 7 Bit Name SPCNUM Initial Value 0 R/W R/W Description Number of SPI Mode MMCs Specifies whether one or two MMCs are to be operated in SPI mode. 0: One MMC is connected to the MCCSA pin. Disables MCCSB pin output. 1: Maximum of two MMCs are connected to the MCCSA and MCCSB pins. 6 CHIPSA 0 R/W MMC Selection A/B Specifies selection of two MMCs while SPCNUM = 1. 0: Outputs CS signal from the MCCSA pin, and sets the MCCSB pin high (no selection). 1: Sets the MCCSA pin high (no selection), and outputs CS signal from the MCCSB pin. 5 to 2 1 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. DIRME 0 R/W Signal Direction Output Enable Enables/disables the outputs of the MCCMDDIR and MCDATDIR pins that output the input/output direction of the MCCMD and MCDAT pins, in MMC mode. 0: Disables MCCMDDIR pin and MCDATDIR pin outputs. 1: Enables MCCMDDIR pin and MCDATDIR pin outputs. Rev. 3.00 Jan 25, 2006 page 653 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Bit 0 Bit Name MMCPE Initial Value 0 R/W R/W Description MCIF Pin Function Enable Enables/disables input/output of all MCIF input/output pins. 0: Disables all inputs/outputs. 1: Enables MCCLK, MCCMD/MCTxD, MCDAT/MCRxD, MCCSA/MCDATDIR, and MCCSB/MCCMDDIR pin inputs/outputs. Outputs of the MCCSB and MCDATDIR and MCCMDDIR pins are also disabled via the SPCNUM bit and DIRME bit, respectively. 19.3.16 Transfer Clock Control Register (CLKON) CLKON controls the transfer clock frequency and clock ON/OFF. A 20-MHz system clock is needed, and bits CSEL2 to CSEL0 should be set to B'100 for a 20Mbps transfer clock according to the limitation of the maximum operating frequency of this LSI. At this time, bits CSEL2 to CSEL0 should be cleared to B'000 for a 200-kbps transfer clock in the open drain format output status in MMC mode. Bit 7 Bit Name CLKON Initial Value 0 R/W R/W Description Clock On 0: Fixes the transfer clock output from the MCCLK pin to low. 1: Outputs the transfer clock from the MCCLK pin. 6 to 3 2 1 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. CSEL2 CSEL1 CSEL0 0 0 0 R/W R/W R/W Transfer Clock Frequency Select 000: Uses /100 as a transfer clock. 001: Uses /8 as a transfer clock. 010: Uses /4 as a transfer clock. 011: Uses /2 as a transfer clock. 100: Uses as a transfer clock. 101 to 111: Setting prohibited Rev. 3.00 Jan 25, 2006 page 654 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.4 MCIF Activation The MMC is an external storage media that can be disconnected. The MCIF controls data transfer with the MMC, however, it cannot control insertion and ejection of the MMC successfully. Firmware should be used to control insertion and ejection of the MMC by using an external interrupt and general ports of this LSI. 19.4.1 Initial Status The power supplied to the MMC is turned on or off by general port output of this LSI. Inputs/outputs of the input/output pins such as MCCLK, MCCMD/MCTxD, MCDAT/MCRxD, MCCSA/MCDATDIR, and MCCSB/MCCMDDIR are enabled/disabled by the MMCPE bit in IOMCR. When the MMCPE bit is set to 1, the CLKON bit should be cleared to 0 so that the transfer clock is applied after the other inputs/outputs are stabilized. 19.4.2 Activation Procedure When MMC insertion is detected, the MCIF should be activated by the following procedures: MMC Mode: * Enable power supply to the MMC by general port output. * Enable input/output signals by setting the MMCPE bit to 1. * Start transfer clock application by setting the CLKON bit to 1. SPI Mode: * Enable power supply to the MMC by general port output. * Specify bits for SPCNUM and CHIPSA in IOMCR according to the number of MMC slots and inserted MMCs. * Enable input/output signals by setting the MMCPE bit to 1. * Start transfer clock application by setting the CLKON bit to 1. Rev. 3.00 Jan 25, 2006 page 655 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.5 Operations in MMC Mode MMC mode is an operating mode in which the transfer clock is output from the MCCLK pin, command transmission/response receive occurs via the MCCMD pin, and data is transmitted/received via the MCDAT pin. In this mode the next command can be issued while data is being transmitted/received. This feature can be applied to the multiblock transfer and stream transfer in which the number of bytes for data transfer does not need to be specified beforehand. In this case, the next command is the CMD12 command, which aborts the current command sequence. In MMC mode, a broadcast command that simultaneously issues a command to multiple MMCs is supported. After the information for the MMC that is inserted by using the broadcast command is acknowledged, a relative address is given to each MMC. One MMC is selected by the relative address, other MMCs are deselected, and various commands are issued to the selected MMC. 19.5.1 Operation of Broadcast Commands The CMD0, CMD1, CMD2M, and CMD4M are broadcast commands. The command sequence assigning relative addresses to individual MMCs consists of these commands and the CMD3M command. In this command sequence, the CMD output format of the MMC side is open drain, and the command response is wired-OR. During the issuance of this command sequence, the transfer clock frequency should be set sufficiently slow. Operation of a typical command is summarized below. * All MMCs are initialized to the idle state by CMD0. * The operation condition register (OCR) of all MMCs is read by CMD1 via wired-OR, and MMCs that cannot operate are deactivated. The deactivated MMCs enter the ready state. * The card identification (CID) of all MMCs in the ready state is read by CMD2M via wiredOR. The individual MMC compares its CID and data on the CMD, and if different, aborts CID output. A single MMC in which the CID can be entirely output enters the acknowledge state. * A relative address (RCA) is given to the MMC in the acknowledge state by the CMD3M. The MMC to which the RCA is given enters the standby state. * CMD2M and CMD3M are repeated, assigning RCAs to all MMCs in the ready state, entering each into the standby state. Rev. 3.00 Jan 25, 2006 page 656 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.5.2 Operation of Relative Address Commands The CMD7M, CMD9, CMD10, CMD13, CMD15M, CMD39M, and CMD55 are relative address commands that address the MMC by the RCA. The relative address commands are used to read MMC administration information and original information, and to change the specific MMC status. Operation of a typical command is summarized below. * CMD7M sets one addressed MMC to the transfer state, and other MMCs to the standby state. Commands requiring data transmission/reception can be executed for the MMC in the transfer state. * CMD15M sets the addressed MMC to the inactive state. * CMD55 sets the addressed MMC to the application original extension command acceptance state. 19.5.3 Operation of Commands Not Requiring Command Response In MMC mode, commands do not require command responses. Figure 19.2 shows an example of the command sequence for commands that do not require command responses. Figure 19.3 shows the operational flow for commands that do not require command responses. * The settings needed to issue a command are made. * The START bit in CMDSTRT is set to 1 to start command transmission. * The end of a command sequence is detected by poling the BUSY flag in CSTR or by the command transmission end interrupt (CMDI). Rev. 3.00 Jan 25, 2006 page 657 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK MCCMD MCDAT (CMDSTRT) Command output (48 bits) Command transmission started START (INTSTR0) CMDIE (CSTR) CWRE Command transmission period BUSY Command sequence execution period REQ Command transmission ended Figure 19.2 Example of Command Sequence for Commands that Do Not Require Command Response Command sequence start Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set START bit in CMDSTRT to 1 CMDI interrupt detected? Yes Command sequence end No Figure 19.3 Operational Flow for Commands that Do Not Require Command Response Rev. 3.00 Jan 25, 2006 page 658 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.5.4 Operation of Commands without Data Transfer The broadcast and relative address commands include a number of commands that do not include data transfer. Such commands execute the desired data transfer using command arguments and command responses. For a command that is related to time-consuming processing such as flash memory write/erase, the MMC indicates the data busy state via the DAT pin. Figures 19.4 and 19.5 show examples of the command sequence for commands without data transfer. Figure 19.6 shows the operational flow for commands without data transfer. * Settings needed to issue a command are made. * The START bit in CMDSTRT is set to 1 to start command transmission. Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * A command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * The end of a command sequence is detected by poling the BUSY flag in CSTR or by the command response end interrupt (CRPI). * The end of the data busy state is detected by poling the DTBUSY flag in CSTR or by the data busy end interrupt (DBSYI). Rev. 3.00 Jan 25, 2006 page 659 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK MCCMD MCDAT (CMDSTRT) START (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command output (48 bits) Command response reception (No busy state) Command transmission started Response reception completed Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY REQ Figure 19.4 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) Rev. 3.00 Jan 25, 2006 page 660 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK MCCMD MCDAT (CMDSTRT) START (INTSTR0) CMDI Command output (48 bits) Command response reception (Busy state) Command transmission started Response reception completed Busy state completed CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY REQ Data busy period Figure 19.5 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) Rev. 3.00 Jan 25, 2006 page 661 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Command sequence start Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Yes Is CRPI interrupt detected? No Is CTERI or CRCERI interrupt detected? Yes Not Busy Is data busy state judged? Busy No No Is DBSYI interrupt detected? Yes Command sequence end Command sequence abnormally ended Figure 19.6 Operational Flow for Commands without Data Transfer Rev. 3.00 Jan 25, 2006 page 662 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.5.5 Commands with Read Data Commands involving read data confirm the MMC status by the command arguments and command responses, and then receive MMC information and flash memory data from the MCDAT pin. The number of bytes of flash memory to be read is a block size specified by CMD16, or if not specified, reading is continued until it is aborted by CMD12M in multiblock transfer and stream transfer. For multiblock transfer, the transfer is suspended at the end of to wait for every block the instruction for continuing the command sequence. Whether the command sequence is suspended or not during the command sequence depends on the size of the block and receive data FIFO. The command sequence is executed without suspending the data transfer when block size receive data FIFO size in single-block transfer. In multiblock transfer, the command sequence is suspended for every block. When block size > receive data FIFO size in single-block transfer, the command sequence is suspended by FIFO full. When the command sequence is suspended, data in the receive data FIFO is processed, and the command sequence is then continued. Figures 19.7 to 19.10 show examples of the command sequence for commands with read data. Figure 19.11 shows the operational flow for commands with read data. * Settings needed to issue a command are made. Receive data FIFO is cleared. * The START bit in CMDSTRT is set to 1 to start command transmission. Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * A command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * Read data from the MMC is detected. * The suspension inter-blocks in multiblock transfer and suspension according to the receive data FIFO full are detected by the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively. To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To abort the command sequence, the CMDOFF bit in OPCR should be set to 1, and CMD12 should be issued. * Detection of the end of a command sequence depends on the command types. In multiblock transfer of an extended command in SPI mode, the end of the command sequence is detected by the block transfer end interrupt (BTI) after the desired number of blocks has been received. In other commands, the end of the command sequence is detected by poling the BUSY flag in CSTR or by the data transfer end interrupt (DTI). Rev. 3.00 Jan 25, 2006 page 663 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Single block data read (Block size receive data FIFO size) MCCLK CMD17 (READ_SINGLE_BLOCK) MCCMD Command response Command MCDAT (CMDSTRT) START (OPCR) RD_CONTI CMDOFF (INTSTR0) CMDI Command transmission started Read data CRPI DTI FFI (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_FULL REQ Figure 19.7 Example of Command Sequence for Commands with Read Data (1) Rev. 3.00 Jan 25, 2006 page 664 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Single block data read (Block size > receive data FIFO size) MCCLK CMD17 (READ_SINGLE_BLOCK) MCCMD Transfer clock transmission halted Transfer clock transmission resumed Command Command response Block data reception suspended Read data Block data reception resumed Read data MCDAT (CMDSTRT) START (OPCR) RD_CONTI CMDOFF (INTSTR0) CMDI Command transmission started CRPI DTI FFI Writing data to FIFO (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_FULL REQ Figure 19.8 Example of Command Sequence for Commands with Read Data (2) Rev. 3.00 Jan 25, 2006 page 665 of 872 REJ09B0286-0300 Multiblock data read MCCLK Transfer clock transmission halted Transfer clock transmission resumed CMD12 (STOP_TRANSMISSION) CMD18 (READ_MULTIPLE_BLOCK) MCCMD Command Command response Command Command response MCDAT Read data Read data Read data Block data reception ended (CMDSTRT) START Command transmission started (OPCR) Next block data reception started Rev. 3.00 Jan 25, 2006 page 666 of 872 REJ09B0286-0300 Multiblock read command execution sequence Stop command execution sequence RD_CONTI Section 19 Multimedia Card Interface (MCIF) CMDOFF (INTSTR0) CMDI CRPI DTI FFI BTI (CSTR) CWRE BUSY FIFO_FULL Figure 19.9 Example of Command Sequence for Commands with Read Data (3) REQ Stream data read MCCLK Transfer clock transmission resumed Transfer clock transmission resumed CMD12 (STOP_TRANSMISSION) CMD11 (READ_DAT_UNTIL_STOP) Transfer clock transmission halted Data reception suspended Data reception resumed Read data Read data Read data Command MCCMD Command Command response Command response MCDAT (CMDSTRT) START Command transmission started Data reception ended (OPCR) RD_CONTI CMDOFF (INTSTR0) CMDI CRPI DTI FFI Writing data to FIFO BTI (CSTR) CWRE BUSY Stream read command execution sequence Stop command execution sequence FIFO_FULL Figure 19.10 Example of Command Sequence for Commands with Read Data (4) Section 19 Multimedia Card Interface (MCIF) Rev. 3.00 Jan 25, 2006 page 667 of 872 REJ09B0286-0300 REQ Section 19 Multimedia Card Interface (MCIF) Command sequence start Execute CMD16 Set the number of transfer bytes (block size) to TBCR Execute CMD18M Is CTERI or CRCERI interrupt detected? : Set block length : Execute multiblock data read Yes No No Is CRPI interrupt detected? Yes Read response register Error Response status? No error No Is FFI interrupt detected? Yes Is DTI interrupt detected? Yes No Is DTERI or CRCERI interrupt detected? No Yes No Is block data read completed? Yes Is next block read? Yes Set the CMDOFF bit to 1 Set the RD_CONTI bit to 1 Set the CMDOFF bit to 1 Set the CMDOFF bit to 1 Read data from FIFO Execute CMD12M Set the RD_CONTI bit to 1 Command sequence end Command sequence abnormal end Execute CMD12M Figure 19.11 Operational Flow for Commands with Read Data Rev. 3.00 Jan 25, 2006 page 668 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.5.6 Commands with Write Data Commands involving write data confirm the MMC status by the command responses after command transmission, and then transmit MMC information and flash memory data from the MCDAT pin. For a command that is related to time-consuming processing such as flash memory write, the MMC indicates the data busy state via the DAT pin. The number of bytes of flash memory to be written is a block size specified by CMD16, or if not specified, writing is continued until it is aborted by CMD12M in multiblock transfer and stream transfer. For multiblock transfer, the instruction for continuing the command sequence is made by suspending the transfer for every block. The suspension of the command sequence depends on the sizes of the block and transmit data FIFO. The command sequence is executed without suspending the data transfer when block size transmit data FIFO size in single-block transfer. In multiblock transfer, the command sequence is suspended for every block. When block size > transmit data FIFO size, the command sequence is suspended by FIFO empty. When the command sequence is suspended, the next data is written to the transmit data FIFO, and the command sequence is then continued. Figures 19.12 to 19.15 show examples of the command sequence for commands with write data. Figure 19.16 shows the operational flow for commands with write data. * Settings needed to issue a command are made. Write data is set to the transmit data FIFO. * The START bit in CMDSTRT is set to 1 to start command transmission. Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * A command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * The DATAEN bit in OPCR is set to start write data transmission. * Suspension inter-blocks in multiblock transfer and suspension according to the transmit data FIFO empty are detected by the data transfer end interrupt (DTI), data response end interrupt (DRPI), and FIFO empty interrupt (FEI), respectively. In addition, when the command sequence is suspended by the end of data transfer, cancellation of the data busy status is detected by the data busy end interrupt (DBSYI). To continue the command sequence, data should be written to the transmit data FIFO, and the DATAEN bit in OPCR should be set to 1. To abort the command sequence, the CMDOFF bit in OPCR should be set to 1, and CMD12M should be issued. * Detection of the end of a command sequence depends on the command types. In multiblock transfer of an extended command in SPI mode, the end of the command sequence is detected by the block transfer end interrupt (BTI) or data response end interrupt (DRPI) after the desired number of blocks has been transmitted. In other commands, the end of the command Rev. 3.00 Jan 25, 2006 page 669 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) sequence is detected by poling the BUSY flag in CSTR, the data transfer end interrupt (DTI), or the data response end interrupt (DPRI). * The end of the data busy state is detected by poling the DTBUSY flag in CSTR or by the data busy end interrupt (DBSYI). Single-block data write (Block size Transmit data FIFO size) MCCLK CMD24 (WRITE_SINGLE_BLOCK) MCCMD Command response Status Write data (CMDSTRT) START (OPCR) DATAEN CMDOFF (INTSTR0) CMDI CRPI DTI DRPI DBSYI FEI (CSTR) CWRE Command transmission started Busy Command MCDAT BUSY Single-block write command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU REQ Figure 19.12 Example of Command Sequence for Commands with Write Data (1) Rev. 3.00 Jan 25, 2006 page 670 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Single-block data write (Block size > Transmit data FIFO size) MCCLK CMD24 (WRITE_SINGLE_BLOCK) Transfer clock transmission halted Transfer clock transmission resumed MCCMD Command Command response Status MCDAT (CMDSTRT) START Command transmission started Write data Block data transmission suspended Reading data from FIFO Write data Block data transmission resumed Busy (OPCR) DA TA EN CMDOFF (INTSTR0) CMDI CRPI DTI DRPI DBSYI FEI (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU REQ Figure 19.13 Example of Command Sequence for Commands with Write Data (2) Rev. 3.00 Jan 25, 2006 page 671 of 872 REJ09B0286-0300 Multiblock data write MCCLK CMD12M (STOP_TRANSMISSION) CMD25 (WRITE_MULTIPE_BLOCK) MCCMD Command Status Write data Write data Write data Command transmission started Command response Command Command response MCDAT (CMDSTRT) START (OPCR) Block data transmission started Next block data transmission started Block data reception end DATAEN Rev. 3.00 Jan 25, 2006 page 672 of 872 REJ09B0286-0300 Multibreak write command sequence Stop command execution sequence CMDOFF Section 19 Multimedia Card Interface (MCIF) (INTSTR0) CMDI CRPI DTI DRPI DBSYI FEI (CSTR) CWRE BUSY FIFO_EMPTY DTBUSY DTBUSY_TU Figure 19.14 Example of Command Sequence for Commands with Write Data (3) REQ Stream data write MCCLK Transfer clock transmission halted Transfer clock transmission resumed Transfer clock transmission resumed Transfer clock transmission halted Data transmission suspended Write data Command CMD20 (WRITE_DAT_UNTIL_STOP) Command response Data transmission suspended Write data Write data Data transmission resumed CMD12M (STOP_TRANSMISSION) Command response MCCMD Command MCDAT Busy (CMDSTRT) START Reading data from FIFO Command transmission started Data transmission ended (OPCR) DATAEN CMDOFF (INTSTR0) CMDI CRPI DTI DRPI DBSYI FEI (CSTR) CWRE BUSY Stream write command execution sequence Stop command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU Figure 19.15 Example of Command Sequence for Commands with Write Data (4) Section 19 Multimedia Card Interface (MCIF) Rev. 3.00 Jan 25, 2006 page 673 of 872 REJ09B0286-0300 REQ Section 19 Multimedia Card Interface (MCIF) Command sequence start Execute CMD16 Set the number of transfer bytes (block size) to TBCR Execute CMD25M : Execute multiblock data write : Set block length Is CTERI or CRCERI interrupt detected? Yes No No Is CRPI interrupt detected? Yes Read response register Response status? No error Error Set the DATAEN bit to 1 Is FFI interrupt detected? Yes No No No Is DTI interrupt detected? Yes Is DTERI or CRCERI interrupt detected? No Yes Is block data write completed? Yes No Is DPRI interrupt detected? Yes Set the CMDOFF bit to 1 No Is next block read? Yes Write data to FIFO Set the CMDOFF bit to 1 Execute CMD12M Set the DATAEN bit to 1 Set the DATAEN bit to 1 Set the CMDOFF bit to 1 Execute CMD12M Command sequence end Command sequence abnormal end Figure 19.16 Operational Flow for Commands with Write Data Rev. 3.00 Jan 25, 2006 page 674 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.6 Operations in SPI Mode SPI mode is an operating mode in which the transfer clock is output from the MCCLK pin, and command/response/data is input/output via the MCRxD pin and MCTxD pin. In SPI mode, one of multiple MMCs is selected by the chip select (CS) pin. Therefore, card selection using broadcast commands for MMC mode is not supported. In SPI mode, data response to write data is supported. 19.6.1 Operation of Commands without Data Transfer Commands without data transfer execute the desired data transfer using command arguments and command responses. For a command that is related to time-consuming processing such as flash memory write/erase, the MMC displays the data busy state. Figures 19.17 and 19.18 show examples of the command sequence for commands without data transfer. Figure 19.19 shows the operational flow for commands without data transfer. * Settings needed to issue a command are made. * The START bit in CMDSTRT is set to 1 to start command transmission. The CS signal goes low (select). Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * A command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * When the command sequence ends, the CS signal goes high (not select). The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command output end interrupt (CRPI). * The end of the data busy state is detected by poling the DTBUSY flag in CSTR or by the data busy end interrupt (DBSYI). Rev. 3.00 Jan 25, 2006 page 675 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK MCTxD Command output (48 bits) Command transmission ended MCRxD Command response reception (No busy state) Response reception ended MCCSA Command transmission started (CMDSTRT) START (INTSTR0) CMDI CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY REQ Figure 19.17 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) Rev. 3.00 Jan 25, 2006 page 676 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK MCTxD Command output (48 bits) Command transmission ended Command response completed MCRxD Command response reception (Busy state) Response reception ended MCCSA (CMDSTRT) START (INTSTR0) CMDI Command transmission started CRPI DBSYI (CSTR) CWRE Command transmission period BUSY Command sequence execution period DTBUSY_TU DTBUSY Data busy period REQ Figure 19.18 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) Rev. 3.00 Jan 25, 2006 page 677 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Command sequence start Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Yes Is CRPI interrupt detected? No Is CTERI interrupt detected? Yes Not Busy Is data busy state judged? Busy No No Is DBSYI interrupt detected? Yes Command sequence end Command sequence abnormal end Figure 19.19 Operational Flow for Commands without Data Transfer Rev. 3.00 Jan 25, 2006 page 678 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.6.2 Commands with Read Data Commands with read data confirm the MMC status by the command responses, and then receive MMC information and flash memory data. The number of bytes of flash memory to be read is a block size specified by CMD16. When block size > receive data FIFO size, the command sequence is suspended by FIFO full. When the command sequence is suspended, data in the receive data FIFO is processed, and the command sequence is then continued. Figures 19.20 and 19.21 show examples of the command sequence for commands with read data. Figure 19.22 shows the operational flow for commands with read data. * Settings needed to issue a command are made. * The START bit in CMDSTRT is set to 1 to start command transmission. The CS signal goes low (select). Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * The command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * Read data is received from the MMC. * Command abortion is detected according to the receive data FIFO full by the FIFO full interrupt (FFI). To continue the command sequence, the RD_CONTI bit in OCR should be set to 1. * When the command sequence ends, the CS signal goes high (not select). The end of the command sequence is detected by poling the BUSY flag in CSTR or by the data transfer end interrupt (DTI). Rev. 3.00 Jan 25, 2006 page 679 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK CMD17 (READ_SINGLE_BLOCK) MCDWR Command MCDRD Command response Read data MCCSA (CMDSTRT) START (OPCR) RD_CONTI CMDOFF (IINTSTR0) CMDI CRPI Command transmission started DTI FFI BTI (CSTR) CWRE BUSY Single-block read command execution sequence FIFO_FULL REQ Figure 19.20 Example of Command Sequence for Commands with Read Data (1) Rev. 3.00 Jan 25, 2006 page 680 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK CMD17 (READ_SINGLE_BLOCK) MCDWR Transfer clock transmission halted Block data reception suspended Transfer clock transmission resumed Block data reception resumed Read data Command MCDRD MCCSA (CMDSTRT) START (OPCR) RD_CONTI CMDOFF (IINTSTR0) CMDI CRPI Command response Read data Command transmission started DTI FFI BTI (CSTR) CWRE Writing data to FIFO BUSY Single-block read command execution sequence FIFO_FULL REQ Figure 19.21 Example of Command Sequence for Commands with Read Data (2) Rev. 3.00 Jan 25, 2006 page 681 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Command sequence start Set the number of transfer bytes (block size) to TBCR Execute CMD16 Execute CMD17 : Set block length : Execute single-block data read Is CTERI interrupt detected? Yes No No Is CRPI interrupt detected? Yes Read response register Error No error Set the CMDOFF bit to 1 Response status? No Is FFI interrupt detected? No Yes Is DTI interrupt detected? Yes Is DTERI or CRCERI interrupt detected? No Does block data read end? Yes Yes Read data from FIFO Set the RD_CONTI bit to 1 Command sequence end Command sequence abnormal end Figure 19.22 Operational Flow for Commands with Read Data Rev. 3.00 Jan 25, 2006 page 682 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.6.3 Commands with Write Data Commands with write data confirm the MMC status by the command responses, and then transmit MMC information and flash memory data. For a command that is related to time-consuming processing such as flash memory write, the MMC indicates the data busy state. The number of bytes of flash memory to be written is a block size specified by CMD16. When block size > transmit data FIFO size, the command sequence is suspended by FIFO empty. When the command sequence is suspended, the next data is written to the transmit data FIFO, and the command sequence is then continued. Figures 19.23 and 19.24 show examples of the command sequence for commands with write data. Figure 19.25 shows the operational flow for commands with write data. * Settings needed to issue a command are made. Write data is set to the transmit data FIFO. * The START bit in CMDSTRT is set to 1 to start command transmission. The CS signal goes low (select). Command transmission complete can be confirmed by the command transmission end interrupt (CMDI). * A command response is received from the MMC. If the MMC does not return the command response, the command response is detected by the command timeout error (CTERI). * The DATAEN bit in OPCR is set to 1 to start write data transmission. * Suspension according to the transmit data FIFO empty is detected by the FIFO empty interrupt (FEI). Data is written to the transmit data FIFO, and the DATAEN bit in OPCR is set to 1. * The end of the command sequence is detected by poling the BUSY flag in CSTR or the data transfer end interrupt (DTI). Reception of data response can be confirmed by the data response end interrupt (DPRI). * When the command sequence ends, the CS signal goes high (not select). The end of the data busy state is detected by poling the DTBUSY flag in CSTR or by the data busy end interrupt (DBSYI). Rev. 3.00 Jan 25, 2006 page 683 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK CMD24 (WRITE_SINGLE_BLOCK) MCDWR Command Write data Data response MCDRD MCCSA (CMDSTRT) START (OPCR) DATAEN CMDOFF (IINTSTR0) CMDI Command transmission started Command response Busy CRPI DTI DRPI DBSYI FFI (CSTR) CWRE BUSY Single-block write command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU REQ Figure 19.23 Example of Command Sequence for Commands with Write Data (1) Rev. 3.00 Jan 25, 2006 page 684 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) MCCLK CMD24 (WRITE_SINGLE_BLOCK) Transfer clock Transfer clock transmission halted transmission resumed Write data Write data Data response MCDRD MCDWR Command Command response MCCSA (CMDSTRT) START Command transmission started Block data transmission suspended Block data transmission resumed Busy (OPCR) DATAEN CMDOFF (IINTSTR0) CMDI Reading data from FIFO CRPI DTI DRPI DBSYI FEI (CSTR) CWRE BUSY Single-block write command execution sequence FIFO_EMPTY DTBUSY DTBUSY_TU REQ Figure 19.24 Example of Command Sequence for Commands with Write Data (2) Rev. 3.00 Jan 25, 2006 page 685 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Command sequence start Set the number of transfer bytes (block size) to TBCR Execute CMD16 Execute CMD24 : Set block length : Execute single-block data write Is CTERI interrupt detected? Yes No No Is CRPI interrupt detected? Yes Read response register Error No error Set the DATAEN bit to 1 Set the CMDOFF bit to 1 Response status? No Is FFI interrupt detected? No Yes Is DTI interrupt detected? Yes No Is DPRI interrupt detected? Yes Write data to FIFO Command sequence end Command sequence abnormal end Is CTERI or CRCERI interrupt detected? No No Does block data write end? Yes Yes Set the DATAEN bit to 1 Figure 19.25 Operational Flow for Commands with Write Data Rev. 3.00 Jan 25, 2006 page 686 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) 19.7 Interrupt Sources Table 19.6 lists the MCIF interrupt sources. The interrupt sources are classified into three groups, each to which an interrupt vector is assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 and INTCR1. A disabled interrupt source does not set the flag. The MMCIA interrupts can be used as DTC activation interrupt sources. Table 19.6 MCIF Interrupt Sources Name MMCIA MMCIB MCIFI0 MCIFI1 Interrupt Source FIFO empty FIFO full Data response Data transfer end Command response end Command transmission end Data busy end Block transfer end MMCIC MCIFI2 CRC error Data timeout error Command timeout error Interrupt Flag FEI FFI DPRI DTI CRPI CMDI DBSYI BTI CRCERI DTERI CTERI DTC Activation Possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Low Priority High 19.8 Usage Notes 1. When activating the DTC with an MCIF interrupt source, correct operation is not guaranteed if the DISEL bit in DTC mode register B (MRB) is cleared to 0. Be sure to set the DISEL bit to 1 before DTC activation. 2. MCIF operation can be enabled or disabled by the SMSTPB6 bit in subchip module stop control register BL (SUBMSTPBL). In the initial state, MCIF operation is enabled. The MCIF registers can be accessed by clearing module stop mode. Rev. 3.00 Jan 25, 2006 page 687 of 872 REJ09B0286-0300 Section 19 Multimedia Card Interface (MCIF) Rev. 3.00 Jan 25, 2006 page 688 of 872 REJ09B0286-0300 Section 20 Encryption Operation Circuit (DES and GF) Section 20 Encryption Operation Circuit (DES and GF) This section will be made available on conclusion of a nondisclosure agreement. For details, contact your Renesas sales agency. DESGE00A_000020020300 Rev. 3.00 Jan 25, 2006 page 689 of 872 REJ09B0286-0300 Section 20 Encryption Operation Circuit (DES and GF) Rev. 3.00 Jan 25, 2006 page 690 of 872 REJ09B0286-0300 Section 21 D/A Converter Section 21 D/A Converter 21.1 Features * 8-bit resolution * Two output channels * Conversion time: Max. 10 s (when load capacitance is 20 pF) * Output voltage: 0 V to AVref * D/A output retaining function in software standby mode Module data bus Bus interface Internal data bus AVref AVCC DA1 DA0 AVSS 8-bit D/A D A D R 0 D A D R 1 D A C R Control circuit Legend: DACR : D/A control register DADR0 : D/A data register 0 DADR1 : D/A data register 1 Figure 21.1 Block Diagram of D/A Converter DAC0002A_000020020300 Rev. 3.00 Jan 25, 2006 page 691 of 872 REJ09B0286-0300 Section 21 D/A Converter 21.2 Input/Output Pins Table 21.1 summarizes the input/output pins used by the D/A converter. Table 21.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference power supply pin Symbol AVCC AVSS DA0 DA1 AVref I/O Input Input Output Output Input Function Analog block power supply Analog block ground and reference voltage Channel 0 analog output Channel 1 analog output Analog block reference voltage 21.3 Register Descriptions The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 21.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, D/A data register contents are converted and output to analog output pins. 21.3.2 D/A Control Register (DACR) DACR controls D/A converter operation. Rev. 3.00 Jan 25, 2006 page 692 of 872 REJ09B0286-0300 Section 21 D/A Converter Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output DA0 is disabled 1: D/A conversion for channel 0 and analog output DA0 are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion in conjunction with the DAOE0 and DAOE1 bits. When the DAE bit is cleared to 0, D/A conversion for channels 0 and 1 are controlled individually. When the DAE bit is set to 1, D/A conversion for channels 0 and 1 are controlled as one. Conversion result output is controlled by the DAOE0 and DAOE1 bits. For details, see table 21.2 below. 4 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Table 21.2 D/A Channel Enable Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE X 0 1 1 0 0 1 1 Legend: X: Don't care X Description Disables D/A conversion Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Enables D/A conversion for channels 0 and 1 Rev. 3.00 Jan 25, 2006 page 693 of 872 REJ09B0286-0300 Section 21 D/A Converter 21.4 Operation The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 21.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, conversion results are output from the analog output pin DA0. The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output value is calculated by the following formula: DADR0 contents/256 x AVref 3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV, conversion results are output. 4. When the DAOE bit is cleared to 0, analog output is disabled. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data (1) Conversion data (2) DAOE0 Conversion result (2) tDCONV DA0 High impedance state tDCONV Conversion result (1) Legend: tDCONV : D/A conversion time Figure 21.2 D/A Converter Operation Example Rev. 3.00 Jan 25, 2006 page 694 of 872 REJ09B0286-0300 Section 21 D/A Converter 21.5 Usage Notes 1. When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output. 2. It is not recommended to use the D/A converter or A/D converter simultaneously with the USB because the bus driver/receiver power supply pin DrVCC/DrVSS is shared with the analog power supply pin AVCC/AVSS. Rev. 3.00 Jan 25, 2006 page 695 of 872 REJ09B0286-0300 Section 21 D/A Converter Rev. 3.00 Jan 25, 2006 page 696 of 872 REJ09B0286-0300 Section 22 A/D Converter Section 22 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to six analog input channels and up to eight digital input channels to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 22.1 * * Features 10-bit resolution nput channels: six analog input channels and eight digital input channels * Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage. * * Conversion time: Max. 5.36 s per channel (at 25-MHz operation) Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * * * * * Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Three kinds of conversion start Software, 8-bit timer (TMR) conversion start trigger, or external trigger signal. Interrupt request A/D conversion end interrupt (ADI) request can be generated Module stop mode can be set A block diagram of the A/D converter is shown in figure 22.1. ADCMS33A_000020020300 Rev. 3.00 Jan 25, 2006 page 697 of 872 REJ09B0286-0300 Section 22 A/D Converter Module data bus Bus interface Internal data bus AVCC AVref AVSS 10-bit D/A Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN2 AN3 AN4 AN5 AN6 AN7 CIN0 to CIN7 Multiplexer + /8 Control circuit /16 Comparator Sample-and-hold circuit ADI interrupt signal Conversion start trigger from 8-bit timer ADTRG Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 22.1 Block Diagram of A/D Converter Rev. 3.00 Jan 25, 2006 page 698 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1. Note that this LSI does not provide the AN0 and AN1 pins. Expanded A/D conversion input pins (CIN0 to CIN7) can be used instead of AN0. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 22.1 Pin Configuration Pin Name Symbol I/O Input Input Input Not Installed Not Installed Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Expanded A/D conversion input (digital input) channels 0 to 7 Can be used as group 0 analog input pins instead of AN0. Group 1 analog input pins Function Analog block power supply Analog block ground and reference voltage Analog block reference voltage Group 0 analog input pins Analog power supply AVCC pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Expanded A/D conversion input pins 0 to 7 AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG CIN0 to CIN7 Rev. 3.00 Jan 25, 2006 page 699 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D control/status register (ADCSR) * A/D control register (ADCR) * Keyboard comparator control register (KBCOMP) 22.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 22.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read directly from the CPU, but the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read only the upper byte in word units. Table 22.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 CIN0 to CIN7 -- AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD Rev. 3.00 Jan 25, 2006 page 700 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1 When DTC starts by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 5 ADIE ADST 0 0 R/W R/W A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1 A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Sets A/D conversion time. 0: Conversion time is 266 states (max) 1: Conversion time is 134 states (max) Switch conversion time while ADST is 0. Rev. 3.00 Jan 25, 2006 page 701 of 872 REJ09B0286-0300 Section 22 A/D Converter Bit 2 1 0 Bit Name CH2 CH1 CH0 Initial Value 0 0 0 R/W R/W R/W R/W Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 000: CIN0 to CIN7 001: Setting prohibited 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 Note: * Only 0 can be written for clearing the flag. When SCAN = 1 000: CIN0 to CIN7 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7 22.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while A/D conversion is stopped (ADST = 0). 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger is disabled 10: A/D conversion start by conversion trigger from TMR 11: A/D conversion start by ADTRG pin 5 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 702 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.3.4 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the CIN input channel for which A/D conversion is performed and enables or disables the comparator scan function of CIN7 to CIN0. The DTC decides where to store the A/D conversion result according to settings of the KBCH2 to KBCH0 bits. Bit 7 Bit Name -- Initial Value 0 All 0 R/W Description The initial value should not be changed. 6, 5 -- R Reserved These bits are always read as 0 and cannot be modified. 4 SCANE 0 R/W DTC Comparator Scan Enable Enables or disables the DTC comparator scan function. 0: Disables DTC comparator scan function 1: Enables DTC comparator scan function 3 KBADE 0 R/W Keyboard A/D Enable Sets analog pin 0 (AN0) of the A/D converter to digital input pins (CIN7 to CIN0). 0: Selects AN0 (not mounted on this LSI) 1: Selects CIN7 to CIN0 2 1 0 KBCH2 KBCH1 KBCH0 0 0 0 R/W R/W R/W Keyboard A/D Channel Select 2 to 0 These bits select a channel of digital input pins (CIN7 to CIN0) for A/D conversion. The input channel setting must be made while conversion is halted. When the SCANE bit is set to 1, these bits are automatically incremented by the DTC. 000: Selects CIN0 001: Selects CIN1 010: Selects CIN2 011: Selects CIN3 100: Selects CIN4 101: Selects CIN5 110: Selects CIN6 111: Selects CIN7 R/(W) Reserved Rev. 3.00 Jan 25, 2006 page 703 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.4 DTC Comparator Scan The DTC should be set as shown in table 22.3 to scan CIN7 to CIN0 using the DTC comparator scan function. Table 22.3 CIN7 to CIN0 Scan by DTC Comparator Scan Function Register MRA Bit 7, 6 5, 4 3, 2 1 0 MRB 7 6 SAR DAR 23 to 0 23 to 0 Bit Name SM1, SM0 DM1, DM0 MD1, MD0 DTS Sz CHNE DISEL -- -- Description 00: SAR is fixed 00: DAR is fixed 01: Repeat mode 0: Destination area is repeat area 1: Word-size transfer 0: Chain transfer is not performed 0: An interrupt request is generated when the specified number of data transfers are performed H'(FF)FFE0: ADDRA Optional RAM address. Lower four bits should be 0. Conversion results of CIN0 to CIN7 are written to eight words leading from this address. H'FF H'FF 1: Enables DTC activation by the A/D converter 1: Enables comparator scan function 1: Sets CIN7 to CIN0 as A/D converter input channel 0 1: Enables an interrupt request generated by A/D conversion end 1: Selects scan mode 000: Selects input channel 0 00: Disables A/D conversion start according to an external trigger (DAR): CIN0 conversion result (DAR) + 2: CIN1 conversion result (DAR) + 4: CIN2 conversion result (DAR) + 6: CIN3 conversion result (DAR) + 8: CIN4 conversion result (DAR) + 10: CIN5 conversion result (DAR) + 12: CIN6 conversion result (DAR) + 14: CIN7 conversion result CRAH CRAL DTCERA KBCOMP ADCSR 7 to 0 7 to 0 3 4 3 6 4 2 to 0 -- -- DTCEA3 SCANE KBADE ADIE SCAN CH2 to CH0 TRGS1, TRGS0 -- ADCR RAM 7, 6 -- Rev. 3.00 Jan 25, 2006 page 704 of 872 REJ09B0286-0300 Section 22 A/D Converter The A/D converter repeats A/D conversion of input channel 0 according to the settings of ADCSR and ADCR. Input channel 0 is connected to CIN7 to CIN0. The KBCH2 to KBCH0 bits in KBCOMP select one channel among CIN7 to CIN0. The KBCH2 to KBCH0 bits are automatically incremented by the DTC when the SCANE bit is set to 1. When one A/D conversion is completed, the ADF flag in ADSCR is set to 1, and an ADI interrupt request is generated. The DTC is activated according to the ADI interrupt request, and data is transferred from ADDRA to on-chip RAM. At this time, the lower four bits of DAR are ignored, and replaced with the previous contents of bits KBCH2 to KBCH0 x 2. 22.5 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 22.5.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1, by software or an external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters wait state. Rev. 3.00 Jan 25, 2006 page 705 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.5.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels max.). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts on the first channel in the group (CIN0 when the CH2 bit in ADCSR is 0 while the SCANE and KBADE bits in KBCOMP are B'11, or AN4 when the CH2 bit in ADCSR is 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. The ADST bit is not automatically cleared to 0 so steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. 22.5.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 22.2 shows the A/D conversion timing. Table 22.4 indicates the A/D conversion time. As indicated in figure 22.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 22.4. In scan mode, the values given in table 22.4 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states (fixed) when CKS = 1. Rev. 3.00 Jan 25, 2006 page 706 of 872 REJ09B0286-0300 Section 22 A/D Converter (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay tSPL : Input sampling time tCONV : A/D conversion time Figure 22.2 A/D Conversion Timing Table 22.4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV min 10 -- 259 typ -- 63 -- max 17 -- 266 min 6 -- 131 CKS = 1 typ -- 31 -- max 9 -- 134 Note: Values in the table indicate the number of states. Rev. 3.00 Jan 25, 2006 page 707 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 22.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 22.3 External Trigger Input Timing 22.6 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion ends. The ADI interrupt can be used as a DTC activation interrupt source. Table 22.5 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF DTC Activation Possible Rev. 3.00 Jan 25, 2006 page 708 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.7 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 22.4). Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'00_0000_0000 (H'000) to B'00_0000_0001 (H'001) (see figure 22.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'11_1111_1110 (H'3FE) to B'11_1111_1111 (H'3FF) (see figure 22.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 22.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 3.00 Jan 25, 2006 page 709 of 872 REJ09B0286-0300 Section 22 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 22.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 22.5 A/D Conversion Accuracy Definitions Rev. 3.00 Jan 25, 2006 page 710 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.8 22.8.1 Usage Notes Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 22.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 22.8.2 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C Up to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 22.6 Example of Analog Input Circuit Rev. 3.00 Jan 25, 2006 page 711 of 872 REJ09B0286-0300 Section 22 A/D Converter 22.8.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ANn AVref (n = 2 to 7). * Digital input voltage range The voltage applied to digital input pin CINn should be in the range AVSS CINn AVref and VSS CINn VCC (n = 0 to 7). * Relation between AVCC, AVSS and VCC, VSS For the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. * AVref pin reference voltage specification range The reference voltage of the AVref pin should be in the range AVref AVCC. * It is not recommended to use the D/A converter or A/D converter simultaneously with the USB because the bus driver/receiver power supply pin DrVCC/DrVSS is shared with the analog power supply pin AVCC/AVSS. 22.8.4 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN2 to AN7), analog reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. 22.8.5 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN2 to AN7) and analog reference voltage (AVref) should be connected between AVCC and AVSS as shown in figure 22.7. Also, the bypass capacitors connected to AVCC and AVref, and the filter capacitors connected to AN7 to AN2 must be connected to AVSS. Rev. 3.00 Jan 25, 2006 page 712 of 872 REJ09B0286-0300 Section 22 A/D Converter If a filter capacitor is connected, the input currents at the analog input pins (AN2 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref *1 *1 Rin *2 100 AN2 to AN7 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 22.7 Example of Analog Input Protection Circuit 10 k AN7 to AN2 20 pF To A/D converter Note: Values are reference values. Figure 22.8 Analog Input Pin Equivalent Circuit Rev. 3.00 Jan 25, 2006 page 713 of 872 REJ09B0286-0300 Section 22 A/D Converter Rev. 3.00 Jan 25, 2006 page 714 of 872 REJ09B0286-0300 Section 23 RAM Section 23 RAM This LSI has 10 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). RAM10K0A_000020020300 Rev. 3.00 Jan 25, 2006 page 715 of 872 REJ09B0286-0300 Section 23 RAM Rev. 3.00 Jan 25, 2006 page 716 of 872 REJ09B0286-0300 Section 24 ROM Section 24 ROM This LSI has an on-chip flash memory. The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 24.1. 24.1 Features * Size: 256 kbytes * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 64 kbytes x 3 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Programming/erase time It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 s (typ.) per 1 byte. Erasing one block takes 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Two flash memory on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer. ROMF250A_000020020300 Rev. 3.00 Jan 25, 2006 page 717 of 872 REJ09B0286-0300 Section 24 ROM Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Module bus EBR1 EBR2 Bus interface/controller Operating mode Mode pin Flash memory (256 kbytes) Legend: FLMCR1 FLMCR2 EBR1 EBR2 : Flash memory control register 1 : Flash memory control register 2 : Erase block register 1 : Erase block register 2 Figure 24.1 Block Diagram of Flash Memory 24.2 Mode Transition Diagrams When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 24.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 24.1. Figure 24.3 shows the boot mode and figure 24.4 shows the user program mode. Rev. 3.00 Jan 25, 2006 page 718 of 872 REJ09B0286-0300 Section 24 ROM User mode (on-chip ROM enabled) =0 1=1 FWE = MD M D2 0 S= Reset state RE RES = 0 *2 *1 = RES = 0 FLSHE = 0 FWE = 1 FWE = 0 FLSHE = 1 User program mode RE S 0 Programmer mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. FEW = 1, MD2 = MD1 = MD0 = 0 2. FEW = 1, MD2 = 1, MD1 = MD0 = 0, P92 = 0, P91 = P90 = 1 Figure 24.2 Flash Memory State Transitions Table 24.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Note: * Yes No Program/program-verify User Program Mode Yes Yes Program/program-verify Erase/erase-verify Should be provided by the user, in accordance with the recommended algorithm. Rev. 3.00 Jan 25, 2006 page 719 of 872 REJ09B0286-0300 Section 24 ROM 1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Programming control program New application program Boot program SCI 2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked. Then the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. New application program Boot program SCI Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM via SCI communication is executed, and the new application program in the host is written into the flash memory. New application program Boot program SCI Boot program SCI Boot program area Flash memory erase Programming control program New application program Boot program area Programming control program Program execution state Figure 24.3 Boot Mode Rev. 3.00 Jan 25, 2006 page 720 of 872 REJ09B0286-0300 Section 24 ROM 1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Programming/ erase control program New application program Boot program Transfer program SCI 2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM. New application program Boot program Transfer program Programming/ erase control program SCI Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. New application program Boot program Transfer program Programming/ erase control program Flash memory erase New application program SCI Boot program Transfer program Programming/ erase control program SCI Program execution state Figure 24.4 User Program Mode (Example) Rev. 3.00 Jan 25, 2006 page 721 of 872 REJ09B0286-0300 Section 24 ROM 24.3 Block Configuration Figure 24.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80. EB0 Erase unit: 4 kbytes H'000F80 EB1 Erase unit: 4 kbytes H'001000 H'000F81 H'001001 H'000F82 H'001002 -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- H'000FFF H'00107F H'001FFF H'00207F Programming unit: 128 bytes H'000000 H'000001 H'000002 H'00007F H'001F80 EB2 Erase unit: 4 kbytes H'002000 H'001F81 H'002001 H'001F82 H'002002 H'002F80 EB3 Erase unit: 4 kbytes H'003F80 EB4 Erase unit: 32 kbytes H'00BF80 EB5 Erase unit: 4 kbytes H'00CF80 EB6 Erase unit: 4 kbytes H'00DF80 EB7 Erase unit: 4 kbytes H'00EF80 EB8 Erase unit: 4 kbytes H'00FF80 EB9 Erase unit: 64 kbytes H'01FF80 EB10 Erase unit: 64 kbytes H'02FF80 EB11 Erase unit: 64 kbytes H'03FF80 H'030000 H'020000 H'010000 H'00F000 H'00E000 H'00D000 H'00C000 H'004000 H'003000 H'002F81 H'003001 H'002F82 H'003002 H'002FFF H'00307F H'003FFF H'00407F H'00BFFF H'00C07F H'00CFFF H'00D07F H'00DFFF H'00E07F H'003F81 H'004001 H'00BF81 H'00C001 H'00CF81 H'00D001 H'00DF81 H'00E001 H'00EF81 H'00F001 H'003F82 H'004002 H'00BF82 H'00C002 H'00CF82 H'00D002 H'00DF82 H'00E002 H'00EF82 H'00F002 H'00EFFF H'00F07F H'00FFFF H'01007F H'00FF81 H'010001 H'01FF81 H'020001 H'00FF82 H'010002 H'01FF82 H'020002 H'01FFFF H'02007F H'02FFFF H'03007F H'02FF81 H'030001 H'03FF81 H'02FF82 H'030002 H'03FF82 H'03FFFF Figure 24.5 Flash Memory Block Configuration Rev. 3.00 Jan 25, 2006 page 722 of 872 REJ09B0286-0300 Section 24 ROM 24.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 24.2. Table 24.2 Pin Configuration Pin Name RES MD2 MD1 MD0 FWE TxD1 RxD1 I/O Input Input Input Input Input Output Input Function Reset Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Flash memory pin Serial transmit data output Serial receive data input 24.5 Register Descriptions The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2, the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the serial/timer control register, see section 3.2.3, Serial Timer Control Register (STCR). * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) 24.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, see section 24.8, Flash Memory Programming/Erasing. FLMCR1 is initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode. Rev. 3.00 Jan 25, 2006 page 723 of 872 REJ09B0286-0300 Section 24 ROM Bit 7 Bit Name FWE Initial Value 0 R/W R Description Flash Write Enable Used to monitor the FWE pin state. When this bit is cleared to 0, flash memory write or erasure is protected by hardware. When this bit is set to 1, hardware protect is cancelled and the SWE bit can be read from or written to. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, the EV, PV, E, and P bits in this register, the ESU and PSU bits in FLMCR2, and all EBR2 bits cannot be set. Do not clear these bits and SWE to 0 simultaneously. 5, 4 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 EV 0 R/W Erase-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. Rev. 3.00 Jan 25, 2006 page 724 of 872 REJ09B0286-0300 Section 24 ROM 24.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Indicates that an error has occurred during flash memory programming/erasing. When this bit is set to 1, flash memory goes to the error-protection state. For details, see section 24.9.3, Error Protection. 6 to 2 -- 1 ESU All 0 0 R/(W) R/W Reserved The initial value should not be changed. Erase Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit in FLMCR1 to 1. 0 PSU 0 R/W Program Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1 to 1. 24.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, or sub-sleep mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0. Rev. 3.00 Jan 25, 2006 page 725 of 872 REJ09B0286-0300 Section 24 ROM EBR1 Bit 7 to 4 3 2 1 0 Note: * Bit Name -- EB11 EB10 EB9 EB8 Initial Value All 0 0 0 0 0 R/W R/(W) R/W * R/W * R/W * R/W * Description Reserved The initial value should not be changed. When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB8 (H'00F000 to H'00FFFF) are to be erased. In normal mode, this bit is always read as 0 and cannot be modified. EBR2 Bit 7 6 5 4 3 2 1 0 Note: * Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W * R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 4 kbytes of EB7 (H'00E000 to H'00EFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB6 (H'00D000 to H'00DFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB5 (H'00C000 to H'00CFFF) are to be erased. When this bit is set to 1, 32 kbytes of EB4 (H'004000 to H'00BFFF) are to be erased. When this bit is set to 1, 4 kbytes of EB3 (H'003000 to H'003FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB2 (H'002000 to H'002FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB1 (H'001000 to H'001FFF) is to be erased. When this bit is set to 1, 4 kbytes of EB0 (H'000000 to H'000FFF) is to be erased. In normal mode, this bit is always read as 0 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 726 of 872 REJ09B0286-0300 Section 24 ROM 24.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. On-chip ROM is enabled or disabled by the mode select pins (MD2, MD1, and MD0) and the EXPE bit in MDCR, as summarized in table 24.3. In normal mode, up to 56 kbytes of ROM can be used. Table 24.3 Operating Modes and ROM Operating Modes MCU Operating Mode Mode 2 CPU Operating Mode Advanced Advanced Mode 3 Normal Normal Mode Pins MDCR On-Chip ROM Enabled (256 kbytes) Enabled (56 kbytes) Mode Single-chip mode Extended mode with on-chip ROM Single-chip mode Extended mode without on-chip ROM MD2 1 1 1 1 MD1 1 1 1 1 MD0 0 0 1 1 EXPE 0 1 0 1 24.7 On-Board Programming Modes An on-board programming mode is used to perform on-chip flash memory programming, erasing, and verification. This LSI has two on-board programming modes: boot mode and user program mode. Table 24.4 shows pin settings for boot mode. In user program mode, operation by software is enabled by setting control bits. For details on flash memory mode transitions, see figure 24.2. Table 24.4 On-Board Programming Mode Settings Mode Setting Boot mode User program mode Mode 2 (advanced mode) Mode 3 (normal mode) FWE 1 1 1 MD2 0 1 1 MD1 0 1 1 MD0 0 0 1 Rev. 3.00 Jan 25, 2006 page 727 of 872 REJ09B0286-0300 Section 24 ROM 24.7.1 Boot Mode Table 24.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 24.8, Flash Memory Programming/Erasing. In boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery when user program mode cannot be executed because the program to be initiated in user program mode was mistakenly erased. 2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, this LSI measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins should be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states before this LSI is ready to measure the low-level period. 4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to this LSI. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 24.6. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses H'FF0800 to H'FF1FFF is the area to which the programming control program is transferred from the host. Note, however, that ID codes are assigned to addresses H'FF0800 to H'FF0807. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. Figure 24.6 shows the on-chip RAM area in boot mode. 6. Before branching to the programming control program (H'FF0808 in the RAM area), this LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD1 pin is in highlevel output state. The contents of the CPU general registers are undefined immediately after Rev. 3.00 Jan 25, 2006 page 728 of 872 REJ09B0286-0300 Section 24 ROM branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. Cancel the reset*1 after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. If mode pin input levels are changed from low to high during reset, operating modes are switched and the state of ports that are also used for address output and bus control output signals (AS, RD, and HWR) are changed.*2 Therefore, set these pins carefully not to be output signals during reset or not to conflict with LSI external signals. 9. All interrupts are disabled during programming or erasing of the flash memory. Notes: 1. After reset is cancelled, mode pin input settings must satisfy the mode programming setup time (tMDS = 4 states). 2. The ports that also have address output functions output low as address output when the MD1 pin is set to 0 during a reset. In other cases, it enters the high impedance state. Bus control output signals output high when the MD1 pin is set to 0 during a reset. In other cases, it enters the high impedance state. Rev. 3.00 Jan 25, 2006 page 729 of 872 REJ09B0286-0300 Section 24 ROM Table 24.5 Boot Mode Operation Item Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot mode start Boot program start Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. Receives data H'AA. H'00 H'55 H'AA * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_1. * Transmits data H'00 to host as adjustment end indication. After receiving data H'55, transmits data H'AA to host. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte). High-order byte and low-order byte Echoback H'XX Echobacks the 2-byte data received to host. Transmits 1 byte of programming control program (repeated for N times). Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times). Flash memory erase Boot program erase error H'FF Receives data H'AA. H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 3.00 Jan 25, 2006 page 730 of 872 REJ09B0286-0300 Section 24 ROM Table 24.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 19200 bps 9600 bps 4800 bps System Clock Frequency Range of LSI 8 to 25 MHz 5 to 25 MHz 5 to 25 MHz H'FF0800 H'FF0808 ID code area Programming control program area (6136 bytes) H'FF1FFF H'FFE080 H'FFE880 H'FFEFFF H'FFFF00 H'FFFF7F Note: * The boot programming area cannot be used until the programming control program transferred to RAM enters execution state. Note that the boot program area in the RAM retains the boot program after branching to the programming control program. Boot program area* (128 bytes) Reserved area* (2048 bytes) Boot program area* (1920 bytes) Figure 24.6 On-Chip RAM Area in Boot Mode In boot mode, this LSI checks the contents of the 8-byte ID code area as shown below to confirm that the programming control program corresponds with this LSI. To originally write a programming control program to be used in boot mode, the above 8-byte ID code must be added at the beginning of the program. H'FF0800 40 FE 64 66 32 31 35 38 (Product ID) Instruction codes of the programming control program H'FF0808 Figure 24.7 ID Code Area Rev. 3.00 Jan 25, 2006 page 731 of 872 REJ09B0286-0300 Section 24 ROM 24.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory. Because the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as like in boot mode. Figure 24.8 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 24.8, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/ erase control program to RAM Branch to flash memory application program Branch to user program/ erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 24.8 Programming/Erasing Flowchart Example in User Program Mode 24.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in Rev. 3.00 Jan 25, 2006 page 732 of 872 REJ09B0286-0300 Section 24 ROM accordance with the descriptions in section 24.8.1, Program/Program-Verify and section 24.8.2, Erase/Erase-Verify, respectively. 24.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 24.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 24.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 24.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. The overflow cycle should be longer than (y + z2 + + ) s. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence to the same bit is (N). Rev. 3.00 Jan 25, 2006 page 733 of 872 REJ09B0286-0300 Section 24 ROM Write pulse application subroutine Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait () s Set P bit in FLMCR1 Wait (z1) s, (z2) s or (z3) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT End Sub Note 7: Write Pulse Width* Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 6 Increment address z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 Start of programming START Set SWE bit in FLMCR1 Wait (x) s Store 128-byte program data in program data area and reprogram data area n=1 m=0 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *6 *4 *6 *5 *6 Write 128-byte data in RAM reprogram data area consecutively to flash memory Sub-Routine-Call Apply write pulse z1 s or z2 s Set PV bit in FLMCR1 Wait () s H'FF dummy write to verify address Wait () s Read verify data *1 *6 *6 See Note 7 for pulse width *6 *6 nn+1 *6 *2 NG m=1 NG Write Time (z) s Write data = verify data? OK 6n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait () s 6 n? NG *4 *3 *4 998 999 1000 z2 z2 z2 NG Note: Use a z3 s write pulse for additional programming. RAM Program data storage area (128 bytes) *6 OK Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Apply write pulse (Additional programming) z3 s NG *1 *3 s Reprogram data storage area (128 bytes) Additional-programming data storage area (128 bytes) *6 n (N)? m=0? OK Clear SWE bit in FLMCR1 NG Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing Wait () s Wait () s *6 fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. End of programming Programming failure 3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in section 29.6, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Comments (D) (V) (X) 0 0 1 Programming completed 0 1 0 Programming incomplete; reprogram 1 0 1 1 1 1 Still in erased state; no action OK Clear SWE bit in FLMCR1 *6 Additional-Programming Data Computation Table Reprogram Data Verify Data AdditionalComments (X') (V) Programming Data (Y) 0 0 0 Additional programming to be executed 0 1 1 Additional programming not to be executed 1 0 1 1 1 1 Additional programming not to be executed Figure 24.9 Program/Program-Verify Flowchart Rev. 3.00 Jan 25, 2006 page 734 of 872 REJ09B0286-0300 Section 24 ROM 24.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 24.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately (y + z + + ) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is N. Rev. 3.00 Jan 25, 2006 page 735 of 872 REJ09B0286-0300 Section 24 ROM START *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1 and EBR2 *2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) s Set E bit in FLMCR1 *2 Start of erasing Wait (z) ms Clear E bit in FLMCR1 *2 End of erasing Wait () s Clear ESU bit in FLMCR2 *2 Wait () s Disable WDT Set EV bit in FLMCR1 *2 Wait () s Set block start address as verify address H'FF dummy write to verify address *2 nn + 1 Wait () s Read verify data Increment address Verify data = all "1"? *2 *3 NG OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait () s Clear EV bit in FLMCR1 Wait () s *2 NG *2 n (N) ? *5 All erase blocks erased? *2 NG OK Clear SWE bit in FLMCR1 OK Clear SWE bit in FLMCR1 Wait () s Erase failure Wait () s End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (writing 0 to all data in erased block) is not necessary. The values of x, y, z, , , , , , , and N are shown in section 29.6, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only a single bit in EBR1 and EBR2. Do not set more than one bit. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 24.10 Erase/Erase-Verify Flowchart Rev. 3.00 Jan 25, 2006 page 736 of 872 REJ09B0286-0300 Section 24 ROM 24.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a low level input to the FEW pin, by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, subsleep mode, or watch mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block registers 1 and 2 (EBR1 and EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 24.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 24.9.3 Error Protection In error protection, an error is detected when the CPU's runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed (transits to software standby mode, sleep mode, subactive mode, sub-sleep mode, or watch mode) during programming/erasing * CPU loses bus mastership during programming/erasing Rev. 3.00 Jan 25, 2006 page 737 of 872 REJ09B0286-0300 Section 24 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode. 24.10 Interrupts during Flash Memory Programming/Erasing In order to give the highest priority to programming/erasing operations, disable all interrupts including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set to 1) or boot program execution*1. 1. If an interrupt is generated during programming/erasing, operation in accordance with the program/erase algorithm is not guaranteed. 2. CPU runaway may occur because normal vector reading cannot be performed in interrupt exception handling during programming/erasing*2. 3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot be executed. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit in FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 24.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device. Figure 24.11 shows a memory map in programmer mode. Note: * For this LSI, set the programming voltage of the PROM programmer to 3.3V. Rev. 3.00 Jan 25, 2006 page 738 of 872 REJ09B0286-0300 Section 24 ROM MCU mode H'000000 This LSI Programmer mode H'00000 On-chip ROM area H'03FFFF H'3FFFF Figure 24.11 Memory Map in Programmer Mode 24.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. Use only the specified socket adapter. If other adapters are used, the product may be damaged. 2. Notes on power on/off At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 3. Perform flash memory programming/erasing in accordance with the recommended algorithm In the recommended algorithm, flash memory programming/erasing can be performed without subjecting this LSI to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1 to 1, set the watchdog timer against program runaway. 4. Do not set/clear the SWE bit during program execution in the flash memory. Do not set/clear the SWE bit during program execution in the flash memory. An interval of at least 100 s is necessary between program execution or data reading in flash memory and SWE bit clearing. When the SWE bit is set to 1, flash memory data can be modified, however, flash memory data can be read only in program-verify or erase-verify mode. Do not access the flash memory for a purpose other than verification during programming/erasing. Do not clear the SWE bit during programming, erasing, or verifying. 5. Do not use interrupts during flash memory programming/erasing In order to give the highest priority to programming/erasing operation, disable all interrupts including NMI input when the flash memory is programmed or erased. Rev. 3.00 Jan 25, 2006 page 739 of 872 REJ09B0286-0300 Section 24 ROM 6. Do not perform additional programming. Programming must be performed in the erased state. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 7. Ensure that the PROM programmer is correctly attached before programming. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 8. Do not touch the socket adapter or LSI while programming. Touching either of these can cause contact faults and write errors. 9. Allocate data or programs to be written to the flash memory to addresses higher than that of the external interrupt vector table. To write data or programs to the flash memory, data or programs must be allocated to addresses higher than that of the external interrupt vector table (H'00040 in advanced mode and H'0020 in normal mode) and H'FF must be written to the areas that are reserved for the system in the exception handling vector table. 10. Write H'FF to the entire key code area for reading in programmer mode. If data other than H'FF is written to the key code area (advanced mode: H'00003C to H'00003F, normal mode: H'001E to H'001F) of flash memory, reading cannot be performed in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FF to the entire key code area. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure has been taken for the PROM programmer. Rev. 3.00 Jan 25, 2006 page 740 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Section 25 User Debug Interface (H-UDI) The user debug interface (H-UDI) provides a boundary scan function using the JTAG (Joint Test Action Group, IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture) and a pin-compatible serial interface. The H-UDI performs serial transfer by means of external signal control. 25.1 Features The H-UDI has the following features conforming to the IEEE1149.1 standard. * Five test pins (ETCK, ETDI, ETDO, ETMS, and ETRST) * TAP controller * Six instructions BYPASS mode EXTEST mode SAMPLE/PRELOAD mode CLAMP mode HIGHZ mode IDCODE mode (These instructions are test modes corresponding to IEEE 1149.1.) HUDS000A_000020020300 Rev. 3.00 Jan 25, 2006 page 741 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) ETCK ETMS TAP controller ETRST Decoder ETDI SDIR Shift register SDBPR SDBSR SDIDR ETDO Mux Legend: SDIR: SDBPR: SDBSR: SDIDR: Instruction register Bypass register Boundary scan register ID code register Figure 25.1 Block Diagram of H-UDI Rev. 3.00 Jan 25, 2006 page 742 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.2 Input/Output Pins Table 25.1 shows the H-UDI pin configuration. Table 25.1 Pin Configuration Pin Name Test clock Abbreviation ETCK I/O Input Function Test clock input Provides an independent clock supply to the HUDI. As the clock input to the ETCK pin is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should be input. For details, see section 29, Electrical Characteristics. If there is no input, the ETCK pin is fixed to 1 by an internal pull-up. Test mode select ETMS Input Test mode select input Sampled on the rise of the ETCK pin. The ETMS pin controls the internal state of the TAP controller. If there is no input, the ETMS pin is fixed to 1 by an internal pull-up. Test data input ETDI Input Serial data input Performs serial input of instructions and data for H-UDI registers. ETDI is sampled on the rise of the ETCK pin. If there is no input, the ETDI pin is fixed to 1 by an internal pull-up. Test data output ETDO Output Serial data output Performs serial output of instructions and data from H-UDI registers. Transfer is performed in synchronization with the ETCK pin. If there is no output, the ETDO pin goes to the highimpedance state. Test reset ETRST Input Test reset input signal Initializes the H-UDI asynchronously. If there is no input, the ETRST pin is fixed to 1 by an internal pull-up. Rev. 3.00 Jan 25, 2006 page 743 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.3 Register Descriptions The H-UDI has the following registers. * Instruction register (SDIR) * Bypass register (SDBPR) * Boundary scan register (SDBSR) * ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS, CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 215-bit register to which the ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE mode. All registers cannot be accessed directly by the CPU. Table 25.2 shows the kinds of serial transfer possible with each H-UDI register. Table 25.2 H-UDI Register Serial Transfer Register SDIR SDBPR SDBSR SDIDR Serial Input Possible Possible Possible Impossible Serial Output Possible Possible Possible Possible 25.3.1 Instruction Register (SDIR) SDIR is a 32-bit read-only register. H-UDI instructions can be transferred to SDIR by serial input from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode. Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR. Rev. 3.00 Jan 25, 2006 page 744 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Bit 31 30 29 28 Bit Name TS3 TS2 TS1 TS0 Initial Value 1 1 1 0 R/W R R R R Description Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited : : 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode 27 to 14 All 0 R Reserved These bits are always read as 0 and cannot be modified. 13 12 to 10 1 All 0 R R Reserved This bit is always read as 1 and cannot be modified. Reserved These bits are always read as 0 and cannot be modified. 9 8 to 1 1 All 0 R R Reserved This bit is always read as 1 and cannot be modified. Reserved These bits are always read as 0 and cannot be modified. 0 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00 Jan 25, 2006 page 745 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.3.2 Bypass Register (SDBPR) SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 25.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. Table 25.3 shows the relationship between the terminals of this LSI and the boundary scan register. Rev. 3.00 Jan 25, 2006 page 746 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Table 25.3 Correspondence between Pins and Boundary Scan Register Pin No. 4 5 6 7 13 Pin Name MD2 MD1 MD0 NMI P51 Input/Output from ETDI Input Input Input Input Input Enable Output 14 P50 Input Enable Output 16 P97 Input Enable Output 17 P96 Input Enable Output 18 P95 Input Enable Output 19 P94 Input Enable Output 20 P56 Input Enable Output 21 P57 Input Enable Output 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 Bit No. Rev. 3.00 Jan 25, 2006 page 747 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 22 Pin Name P93 Input/Output Input Enable Output 23 P92 Input Enable Output 24 P91 Input Enable Output 25 P90 Input Enable Output 26 P60 Input Enable Output 27 P61 Input Enable Output 28 P62 Input Enable Output 29 P63 Input Enable Output 32 P64 Input Enable Output 33 P65 Input Enable Output Bit No. 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 Rev. 3.00 Jan 25, 2006 page 748 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 34 Pin Name P66 Input/Output Input Enable Output 35 P67 Input Enable Output 38 USDP Input Enable* Output 39 USDM Input Enable* Output 40 41 42 43 44 45 47 P72 P73 P74 P75 P76 P77 PA1 Input Input Input Input Input Input Input Enable Output 48 PA0 Input Enable Output 49 P54 Input Enable Output 50 P55 Input Enable Output Bit No. 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 Rev. 3.00 Jan 25, 2006 page 749 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 51 Pin Name P40 Input/Output Input Enable Output 52 P41 Input Enable Output 53 P42 Input Enable Output 54 P43 Input Enable Output 55 P44 Input Enable Output 56 P45 Input Enable Output 57 P46 Input Enable Output 58 P47 Input Enable Output 60 P27 Input Enable Output 61 P26 Input Enable Output Bit No. 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 Rev. 3.00 Jan 25, 2006 page 750 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 62 Pin Name P25 Input/Output Input Enable Output 63 P24 Input Enable Output 64 P23 Input Enable Output 65 P22 Input Enable Output 66 P21 Input Enable Output 67 P20 Input Enable Output 72 P17 Input Enable Output 73 P16 Input Enable Output 74 P15 Input Enable Output 75 P14 Input Enable Output Bit No. 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 Rev. 3.00 Jan 25, 2006 page 751 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 76 Pin Name P13 Input/Output Input Enable Output 77 P12 Input Enable Output 78 P11 Input Enable Output 79 P10 Input Enable Output 80 P87 Input Enable Output 81 P86 Input Enable Output 82 P30 Input Enable Output 83 P31 Input Enable Output 84 P32 Input Enable Output 85 P33 Input Enable Output Bit No. 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Rev. 3.00 Jan 25, 2006 page 752 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 86 Pin Name P34 Input/Output Input Enable Output 87 P35 Input Enable Output 88 P36 Input Enable Output 89 P37 Input Enable Output 90 P85 Input Enable Output 91 P84 Input Enable Output 93 P80 Input Enable Output 94 P81 Input Enable Output 95 P82 Input Enable Output 96 P83 Input Enable Output Bit No. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Rev. 3.00 Jan 25, 2006 page 753 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Pin No. 97 Pin Name P52 Input/Output Input Enable Output 98 P53 Input Enable Output 99 FWE Input to ETDO Notes: The enable signals are active-high. When an enable signal is driven high, the corresponding pin is driven with the output value. * If either the enable signal for the USDP pin or that for the USDM pin is driven high, both pins are driven by the output values. Bit No. 6 5 4 3 2 1 0 25.3.4 ID Code Register (SDIDR) SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output H'0018200F, which is a fixed code, from ETDO. However, no serial data can be written to SDIDR via ETDI. 31 28 27 0000 0001 1000 Part Number (16 bits) 12 0010 11 0000 0000 1 111 0 1 Fixed Code (1 bit) 0000 Version (4 bits) Manufacture Identify (11 bits) Rev. 3.00 Jan 25, 2006 page 754 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.4 25.4.1 Operation TAP Controller State Transitions Figure 25.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard. 1 Tset -Logic-Reset 0 1 1 Select-DR-Scan 0 Select-IR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 1 0 Capture-IR 0 Shift-IR 1 1 Exit1-IR 0 Pause-IR 1 0 0 1 0 Run-Test/Idle 1 Figure 25.2 TAP Controller State Transitions 25.4.2 H-UDI Reset The H-UDI can be reset in two ways. * The H-UDI is reset when the ETRST pin is held at 0. * When ETRST = 1, the H-UDI can be reset by inputting at least five ETCK clock cycles while ETMS = 1. Rev. 3.00 Jan 25, 2006 page 755 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.5 Boundary Scan The H-UDI pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 25.5.1 Supported Instructions This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). * BYPASS [Instruction code: B'1111] The BYPASS instruction is an instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is being executed, the test circuit has no effect on the system circuits. * SAMPLE/PRELOAD [Instruction code: B'0100] The SAMPLE/PRELOAD instruction inputs values from this LSI internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is being executed, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI system circuits are not affected by execution of this instruction. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). * EXTEST [Instruction code: B'0000] The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned in when test data (N-1) is scanned out. Rev. 3.00 Jan 25, 2006 page 756 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). * CLAMP [Instruction code: B'0010] When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been previously set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled. * HIGHZ [Instruction code: B'0011] When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled. * IDCODE [Instruction code: B'1110] When the IDCODE instruction is enabled, the value of the ID code register is output from the ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. 25.5.2 Notes 1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS, AVCC/DrVCC, AVSS/DrVSS, and AVref). 2. Boundary scan mode covers clock-related pins (EXTAL, XTAL, X1, and X2). 3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO). 4. Boundary scan mode does not cover H-UDI-related pins (ETCK, ETDI, ETDO, ETMS, and ETRST). 5. Fix the MD2 pin high. Rev. 3.00 Jan 25, 2006 page 757 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 25.6 Usage Notes 1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the H-UDI is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 29, Electrical Characteristics. To activate the H-UDI after a reset, drive the ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the H-UDI is not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the highimpedance state. These pins are internally pulled up and are noted in standby mode. 2. The following must be considered when the power-on reset signal is applied to the ETRST pin. The reset signal must be applied at power-on. To prevent the LSI system operation from being affected by the ETRST pin of the board tester, circuits must be separated . Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI system reset, circuits must be separated. Figure 25.3 shows a design example of the reset signal circuit wherein no reset signal interference occurs. Board edge pin System reset Power-on reset circuit ETRST ETRST This LSI RES Figure 25.3 Reset Signal Circuit Without Reset Signal Interference 3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode, IDCODE mode will be entered. 4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see section 29, Electrical Characteristics. 5. Data input/output in serial data transfer starts from the LSB. Figure 25.4 shows examples of serial data input/output. 6. When data that exceeds the number of bits of the register connected between the ETDI and ETDO pins is serially transferred, the serial data that exceeds the number of register bits and output from the ETDO pin is the same as that input from the ETDI pin. 7. If the H-UDI serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer should then be retried, regardless of the transfer operation. Rev. 3.00 Jan 25, 2006 page 758 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) 8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be detected at the corresponding input scan register. In this case, the corresponding enable scan register should be cleared to 0. 9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its corresponding output scan register is 1, 0 can be detected at the corresponding enable scan register. SDIR serial data input/output SDIR is captured into the shift register in Capture-IR, and bits 0 to 31 of SDIR are output in that order from the ETDO pin in Shift-IR. Data input from the ETDI pin is written to SDIR in Update-IR. ETDI Bit 31 . . . . . . . . . . . Shift register ETDI Bit 31 Shift register Bit 31 Bit 28 . . . Bit 31 Bit 28 SDIR SDIR Bit 0 ETDO Bit 0 ETDO Capture-IR Update-IR Figure 25.4 Serial Data Input/Output (1) Rev. 3.00 Jan 25, 2006 page 759 of 872 REJ09B0286-0300 Section 25 User Debug Interface (H-UDI) SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is written to any register in Update-DR. ETDI Bit 31 Bit 31 Shift register . . . . SDIDR Bit 0 Bit 0 ETDO Capture-DR Figure 25.4 Serial Data Input/Output (2) Rev. 3.00 Jan 25, 2006 page 760 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator Section 26 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (), internal clock, bus master clock, and subclock (SUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 26.1 shows a block diagram of the clock pulse generator. This LSI also incorporates a PLL (Phase Locked Loop) circuit that generates a 48-MHz clock (48) and a 24-MHz clock (24) as the USB operating clock. The 24-MHz clock can be used as the system clock () by inputting it to the duty correction circuit instead of the oscillator output to which the EXTAL and XTAL pins are input. The PLL circuit consists of a USB external clock input circuit, PLL input clock select circuit, division/multiplication circuit, and USB operating clock select circuit. EXTAL Oscillator XTAL Duty correction circuit 24 System clock select circuit Mediumspeed clock /2 divider to /32 USEXCL USB external clock input circuit PLL input clock select circuit 48 Division/ Multiplication circuit 24 SUB 48 Bus master clock select circuit USB operating clock select circuit PLL circuit USB operating clock To USB Waveform forming circuit WDT_1 count clock System clock To pin Internal clock To peripheral modules Bus master clock To CPU and DTC EXCL Subclock input circuit Figure 26.1 Block Diagram of Clock Pulse Generator The bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the SCK2 to SCK0 bits in the standby control register. Use of the medium-speed clock (/2 to /32) may be limited during CPU operation and when accessing the internal memory of the CPU. The operation speed of the DTC and RFU and the external space access cycle are thus stabilized regardless of the setting of medium-speed mode. For details on the standby control register, see section 27.1.1, Standby Control Register (SBYCR). CPG0500A_000020020300 Rev. 3.00 Jan 25, 2006 page 761 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, see section 27.1.2, Low-Power Control Register (LPWRCR). 26.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 26.1.1 Connecting a Crystal Oscillator Figure 26.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 26.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 26.3 shows the equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 26.2 should be used. A crystal resonator with frequency identical to that of the system clock () should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 26.2 Typical Connection to Crystal Resonator Table 26.1 Damping Resistance Values Frequency (MHz) Rd () 5 300 8 200 10 0 12 0 16 0 20 0 25 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator C0 Figure 26.3 Equivalent Circuit of Crystal Resonator Rev. 3.00 Jan 25, 2006 page 762 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator Table 26.2 Crystal Resonator Parameters Frequency(MHz) RS (max) () C0 (max) (pF) 5 100 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 25 30 7 26.1.2 External Clock Input Method Figure 26.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 26.3. The frequency of the external clock should be the same as that of the system clock (). EXTAL XTAL Open External clock input (a) Example of external clock input when XTAL pin left open EXTAL XTAL External clock input (b) Example of external clock input when an inverted clock is input to XTAL pin Figure 26.4 Example of External Clock Input Rev. 3.00 Jan 25, 2006 page 763 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator Table 26.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level Clock pulse width high level Symbol tEXL Min 15 Max -- VCC = 2.7 to 3.6 V Min 20 Max -- Unit ns Test Conditions Figure 26.5 tEXH 15 -- 20 -- ns tEXr tEXf tCL tCH -- -- 0.4 0.4 5 5 0.6 0.6 -- -- 0.4 0.4 5 5 0.6 0.6 ns ns tcyc tcyc Figure 29.4 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 26.5 External Clock Input Timing The oscillator and duty correction circuit have a function to adjust the waveform of the external clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to hold it in reset state. Table 26.4 shows the external clock output stabilization delay time. Figure 26.6 shows the timing of the external clock output stabilization delay time. Rev. 3.00 Jan 25, 2006 page 764 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator Table 26.4 External Clock Output Stabilization Delay Time Condition: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0 V Item External clock output stabilization delay time Note: * Symbol tDEXT* Min. 500 Max. -- Unit s Remarks Figure 26.6 tDEXT includes a RES pulse width (tRESW). VCC 2.7 V STBY VIH EXTAL (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 26.6 Timing of External Clock Output Stabilization Delay Time 26.2 Duty Correction Circuit The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock (). Rev. 3.00 Jan 25, 2006 page 765 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator 26.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks. 26.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR. 26.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 26.5. When the subclock is not used, subclock input should not be enabled. Table 26.5 Subclock Input Conditions VCC = 2.7 to 3.6 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min -- -- -- -- Typ 15.26 15.26 -- -- Max -- -- 10 10 Unit s s ns ns Measurement Condition Figure 26.7 Rev. 3.00 Jan 25, 2006 page 766 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator tEXCLH tEXCLL EXCL VCC x 0.5 tEXCLr tEXCLf Figure 26.7 Subclock Input Timing 26.6 Waveform Forming Circuit To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode. 26.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. Either a clock generated by an oscillator to which the EXTAL and XTAL pins are input or a 24MHz clock generated by multiplication in the PLL circuit is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, or software standby mode. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from the reset state or hardware standby mode. A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, ports, and interrupt controller and their functions operate depending on the SUB. The count clock and sampling clock for each timer are divided SUB clocks. 26.8 PLL Circuit This LSI incorporates a PLL circuit which generates a 48-MHz clock (48) or a 24-MHz clock (24) obtained by dividing the 48-MHz clock by two as the USB operating clock. The clock source is the clock input from the USEXCL pin or the clock generated by an oscillator to which the EXTAL and XTAL pins are input. The PLL input clock must be 8, 12, 16, 20, or 24 MHz. The 48-MHz clock input to the USEXCL pin can be directly used as the USB operating clock instead Rev. 3.00 Jan 25, 2006 page 767 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator of the PLL circuit output clock. For details, see section 18.3.17, USB PLL Control Register (UPLLCR). The 24-MHz clock generated by the PLL circuit can also be used as the system clock. For details, see section 27.1.3, System Control Register 2 (SYSCR2). To activate the PLL circuit, first clear the SMSTPB1 bit in SUBMSTPBL to 0, then after clearing the USB module stop mode, make settings for UPLLCR. If the USB module is not used, after activating the PLL circuit, set the SMSTPB1 bit in SUBMSTPBL to 1 to make the USB module enter module stop mode. 26.9 26.9.1 Usage Notes Note on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not exceed the maximum rating. 26.9.2 Notes on Board Design When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the EXTAL and XTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent inductive interference with the correct oscillation as shown in figure 26.8. Prohibited CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 26.8 Note on Board Design of Oscillation Circuit Section Rev. 3.00 Jan 25, 2006 page 768 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator 26.9.3 Processing for X1 and X2 Pins The X1 and X2 pins should be left open as shown in figure 26.9. X1 Open X2 Open Figure 26.9 Processing for X1 and X2 Pins Rev. 3.00 Jan 25, 2006 page 769 of 872 REJ09B0286-0300 Section 26 Clock Pulse Generator Rev. 3.00 Jan 25, 2006 page 770 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Section 27 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32. * Subactive mode The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Subsleep mode The CPU and on-chip peripheral modules other than TMR_0 , TMR_1, WDT_0, and WDT_1 stop operating. * Watch mode The CPU and on-chip peripheral modules other than WDT_1 stop operating. * Software standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. LPWS263A_000020020300 Rev. 3.00 Jan 25, 2006 page 771 of 872 REJ09B0286-0300 Section 27 Power-Down Modes 27.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * Standby control register (SBYCR) * Low power control register (LPWRCR) * System control register 2 (SYSCR2) * Module stop control register H (MSTPCRH) * Module stop control register L (MSTPCRL) * Sub-chip module stop control register BH (SUBMSTPBH) * Sub-chip module stop control register BL (SUBMSTPBL) 27.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit 7 Bit Name Initial Value R/W SSBY 0 R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt. Rev. 3.00 Jan 25, 2006 page 772 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Bit 6 5 4 Bit Name Initial Value R/W STS2 STS1 STS0 0 0 0 R/W R/W R/W Description Standby Timer Select 2 to 0 Select the wait time for clock stabilization from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 27.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, there are no specific wait requirements. Normally the minimum value is recommended. 3 DTSPEED 0 R/W DTC/RFU Speed Specifies the operating clock for the bus masters (DTC and RFU) other than the CPU in medium-speed mode. 0: All bus masters operate based on the medium-speed clock. 1: The DTC/RFU operates based on the system clock. The operating clock is changed when a DTC/RFU transfer is requested even if the CPU operates based on the medium-speed clock. Note however that medium-speed mode for the RFU is not supported in this LSI. This bit must be set to 1 when the RFU is used in medium-speed mode. If the RFU is activated while this bit is cleared to 0, the program may go wild. 2 1 0 SCK2 SCK1 SCK0 0 0 1 R/W R/W R/W System Clock Select 2 to 0 Select a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, the SCK2 to SCK0 bits must be cleared to B'000. 000: High-speed mode 001: Medium-speed clock: /2 (Initial value) 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: -- Legend: X: Don't care Rev. 3.00 Jan 25, 2006 page 773 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Table 27.1 Operating Frequency and Wait Time STS2 0 0 0 0 1 1 1 1 STS1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 Wait Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 24M Hz 20 MHz 10 MHz 8 MHz 0.3 0.7 1.3 2.7 5.5 10.9 0.7 0.4 0.8 2.0 4.1 8.2 16.4 0.8 0.8 1.6 3.3 6.6 13.1 26.2 1.6 1.0 2.0 4.1 8.2 16.4 32.8 2.0 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 2.7 s Unit ms Recommended specification Note: * This setting cannot be made in the flash-memory version of this LSI. 27.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 Bit Name Initial Value R/W DTON 0 R/W Description Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode Rev. 3.00 Jan 25, 2006 page 774 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Bit 6 Bit Name Initial Value R/W LSON 0 R/W Description Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is cancelled: 0: Shifts to high-speed mode 1: Shifts to subactive mode 5 NESEL 0 R/W Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL pin is sampled using the clock () generated by the system clock pulse generator. Clear this bit to 0 in this LSI. 0: Sampling using /32 clock 1: Sampling using /4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables/disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin 3 to 0 All 0 R/(W) Reserved The initial value should not be changed. 27.1.3 System Control Register 2 (SYSCR2) SYSCR2 controls switching of the system clock source. The system clock can be selected from the clock () input from the EXTAL and XTAL pins, the subclock (SUB) input from the EXCL pin, or the 24-MHz clock (24) generated by the PLL circuit. SYSCR2 selects between and 24. Rev. 3.00 Jan 25, 2006 page 775 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Before using this function to switch the clock, the PLL circuit must be started up to provide a stable 24-MHz clock. Bit 7 6 5 4, 3 2 Bit Name Initial Value KWUL1 KWUL0 P6PUE -- CKCHGE 0 0 0 All 0 0 R/W R/W R/W R/W R/(W) Reserved The initial value should not be changed. R/W Clock Change Enable Specifies the next operating mode and system clock source ( or 24) when the SLEEP instruction is executed while the SSBY bit is set to 1 in high-speed mode or medium-speed mode. If the SLEEP instruction is executed while the SSBY bit is cleared to 0, the system clock source is not switched and operation shifts to sleep mode. 0: Enters software standby mode or watch mode, and switches to the system clock source specified by the PLCKS bit. 1: Directly switches to the system clock source specified by the PLCKS bit. 1 0 -- PLCKS 0 0 R/(W) Reserved The initial value should not be changed. R/W PLL Clock Select Specifies or 24 as the system clock source in highspeed mode or medium-speed mode. If the LSON bit in LPWCR and this bit are both set to 1 simultaneously, the subclock selection by the LSON bit has higher priority than clock selection by this bit. 0: Specifies as the system clock source. Executing the SLEEP instruction while PLCKS = 0 and SSBY = 1 can switch the clock source to . Executing the SLEEP instruction while LSON = 1 and SSBY = 1 can switch the clock source to 32-kHz SUB. 1: Specifies 24 as the system clock source. Executing the SLEEP instruction while PLCKS = 1 and SSBY = 1 can switch the clock source to 24. Description For details on bits 7 to 5, see section 9.6.4, System Control Register 2 (SYSCR2). Rev. 3.00 Jan 25, 2006 page 776 of 872 REJ09B0286-0300 Section 27 Power-Down Modes 27.1.4 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) Sub-Chip Module Stop Control Registers BH and BL (SUBMSTPBH, SUBMSTPBL) MSTPCR and SUBMSTPB specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 * 0* 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR_0, TMR_1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) D/A converter A/D converter 8-bit timers (TMR_X, TMR_Y), timer connection Corresponding Module Do not set this bit to 1. * MSTPCRL Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 * 1 1 1 1 1 1* 1 1* R/W R/W R/W R/W R/W R/W R/W R/W CRC operator Corresponding Module Serial communication interface 0 (SCI_0) Serial communication interface 1 (SCI_1) Serial communication interface 2 (SCI_2) I C bus interface channel 0 (IIC_0) I C bus interface channel 1 (IIC_1) 2 2 Do not clear this bit to 0. Rev. 3.00 Jan 25, 2006 page 777 of 872 REJ09B0286-0300 Section 27 Power-Down Modes * SUBMSTPBH Bit 7 6 5 4 3 2 1 0 Note: Bit Name SMSTPB15 SMSTPB14 SMSTPB13 SMSTPB12 SMSTPB11 SMSTPB10 SMSTPB9 SMSTPB8 * Initial Value R/W 1* 1* 1* 1* 1* 1* 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Encryption operation circuit (GF) Encryption operation circuit (DES) Corresponding Module Do not clear this bit to 0. * SUBMSTPBL Bit 7 6 5 4 3 2 1 0 Note: Bit Name SMSTPB7 SMSTPB6 SMSTPB5 SMSTPB4 SMSTPB3 SMSTPB2 SMSTPB1 SMSTPB0 * Initial Value R/W 1* 1 1* 1* 1* 1* 1 1* R/W R/W R/W R/W R/W R/W R/W R/W Universal serial bus interface (USB) Multimedia card interface (MCIF) Corresponding Module Do not clear this bit to 0. 27.2 Mode Transitions and LSI States Figure 27.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 27.2 shows the LSI internal states in each operating mode. Rev. 3.00 Jan 25, 2006 page 778 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0, LSON = 0 SLEEP instruction High-speed mode (main clock) Any interrupt SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 SLEEP instruction External interrupt*3 SLEEP instruction Interrupt*1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception processing SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception processing SSBY = 1, PSS = 1, DTON = 0 Watch mode (sub-clock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode Sleep mode (main clock) Hardware standby mode Medium-speed mode (main clock) SLEEP instruction Interrupt*1 LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0, PSS = 1, LSON = 1 Sub-sleep mode (sub-clock) Sub-active mode (sub-clock) : Transition after exception processing : Power-down mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. Always select high-speed mode before making a transition to watch mode or sub-active mode. 1. NMI, IRQ15 to IRQ0, KIN9 to KIN0, WUE15 to WUE8, and WDT1 interrupts 2. NMI, IRQ15 to IRQ0, KIN9 to KIN0, WUE15 to WUE8, WDT0, WDT1, TMR0, and TMR1 interrupts 3. NMI, IRQ15 to IRQ0, KIN9 to KIN0, and WUE15 to WUE8 interrupts Figure 27.1 Mode Transition Diagram Rev. 3.00 Jan 25, 2006 page 779 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Table 27.2 LSI Internal States in Each Operating Mode Function System clock pulse generator Subclock pulse generator CPU Instruction execution Registers External interrupts NMI IRQ15 to IRQ0 KIN9 to KIN0 WUE15 to WUE8 Peripheral RFU modules DTC HighSpeed Functioning Functioning Functioning MediumSpeed Functioning Functioning Functioning in mediumspeed mode Functioning Sleep Functioning Functioning Halted Retained Functioning Functioning Module Stop Functioning Functioning Functioning Watch Halted Functioning Halted Retained Functioning Functioning SubActive Halted Functioning Subclock operation SubSleep Halted Functioning Halted Retained Functioning Software Standby Halted Halted Halted Retained Functioning Hardware Standby Halted Halted Halted Undefined Halted Functioning Functioning WDT_1 WDT_0 TMR_0, TMR_1 FRT TMR_X, TMR_Y Timer connection IIC_0 IIC_1 CRC USB DES, GF MCIF SCI_0 SCI_1 SCI_2 PWM PWMX D/A converter A/D converter RAM I/O Functioning Functioning Functioning in mediumspeed mode/ Functioning Functioning Functioning Function- Halted ing (retained) Functioning/Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Functioning Functioning Subclock operation Halted (retained) Subclock operation Subclock operation Halted (retained) Halted (reset) Functioning Functioning Functioning Functioning/Halted (retained) Halted (retained) Halted (retained) Functioning Functioning Functioning Function- Halted ing/Halted (retained) (reset) Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted (reset) Halted (retained) Halted (reset) Halted (reset) Functioning (DTC) Functioning Functioning Retained Functioning Retained Functioning Retained Retained High impedance Note: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 3.00 Jan 25, 2006 page 780 of 872 REJ09B0286-0300 Section 27 Power-Down Modes 27.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC or RFU) also operate in medium-speed mode when the DTSPEED bit in SBYCR is cleared to 0. Note however that the DTSPEED bit must be set to 1 when the RFU is used in medium-speed mode. On-chip peripheral modules other than the bus masters always operate on the system clock (). When the DTSPEED bit in SBYCR or the EXCKS bit in BCSR2 is set to 1, the clock can be used as the DTC/RFU operating clock or external extended area bus cycle clock. In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, operation shifts to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 27.2 shows an example of medium-speed mode timing. Rev. 3.00 Jan 25, 2006 page 781 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Medium-speed mode , peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 27.2 Medium-Speed Mode Timing 27.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU's internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation stabilization time has passed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin level is driven low, a transition is made to hardware standby mode. 27.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT_1) is cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, I/O ports, and the Rev. 3.00 Jan 25, 2006 page 782 of 872 REJ09B0286-0300 Section 27 Power-Down Modes states of on-chip peripheral modules other than the SCI, PWM, and PWMX, are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ15 to IRQ0, KIN9 to KIN0, or WUE15 to WUE8), the RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When exiting software standby mode with an IRQ15 to IRQ0 interrupt, set the corresponding enable bit to 1. When exiting software standby mode with a KIN9 to KIN0 or WUE15 to WUE8 interrupt, enable the input. In these cases, ensure that no interrupt with a higher priority than interrupts IRQ15 to IRQ0 is generated. In the case of an IRQ15 to IRQ0 interrupt, software standby mode is not exited if the corresponding enable bit is cleared to 0 or if the interrupt has been masked by the CPU. In the case of a KIN9 to KIN0 or WUE15 to WUE8 interrupt, software standby mode is not exited if input is disabled or if the interrupt has been masked by the CPU. When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. Figure 27.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin. Rev. 3.00 Jan 25, 2006 page 783 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Oscillator NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 27.3 Software Standby Mode Application Example 27.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2, MD1, and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has passed, reset exception handling starts. Rev. 3.00 Jan 25, 2006 page 784 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Figure 27.4 shows an example of hardware standby mode timing. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 27.4 Hardware Standby Mode Timing 27.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and onchip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is exited by an interrupt (WOVI1, NMI, IRQ15 to IRQ0, KIN9 to KIN0, or WUE15 to WUE8), RES pin input, or STBY pin input. When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ15 to IRQ0 interrupt, watch mode is not exited if the corresponding enable bit has been cleared to 0 or the interrupt is masked by the CPU. In the case of a KIN9 to KIN0 or WUE15 to WUE8 interrupt, watch mode is not exited if input is disabled or the interrupt is Rev. 3.00 Jan 25, 2006 page 785 of 872 REJ09B0286-0300 Section 27 Power-Down Modes masked by the CPU. In the case of an interrupt from the on-chip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. 27.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ15 to IRQ0, KIN9 to KIN0, or WUE15 to WUE8), the RES pin input, or the STBY pin input. When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts. In the case of an IRQ15 to IRQ0 interrupt, subsleep mode is not exited if the corresponding enable bit has been cleared to 0 or the interrupt is masked by the CPU. In the case of a KIN9 to KIN0 or WUE15 to WUE8 interrupt, subsleep mode is not exited if input is disabled or the interrupt is masked by the CPU. In the case of an interrupt from the on-chip peripheral modules, subsleep mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. Rev. 3.00 Jan 25, 2006 page 786 of 872 REJ09B0286-0300 Section 27 Power-Down Modes 27.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to 0. Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details of direct transitions, see section 27.11, Direct Transitions. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. 27.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR and SUBMSTPB is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation Rev. 3.00 Jan 25, 2006 page 787 of 872 REJ09B0286-0300 Section 27 Power-Down Modes resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the MCIF, SCI, D/A converter, A/D converter, PWM, and PWMX are retained. After the reset state is cancelled, all modules other than DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. 27.11 Direct Transitions The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode, there is no interruption of program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and then executing the SLEEP instruction. After a transition, direct transition exception handling starts. The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 11, and the PSS bit in TSCR (WDT_1) set to 1. To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR (WDT_1) set to 1. In high-speed mode or medium-speed mode, the system clock source ( or 24) can be switched by using one of the following two methods according to the CKCHGE bit in SYSCR2. When the CKCHGE bit is cleared to 0, after a transition to software standby mode or watch mode is made, the system clock source is switched by a wakeup via an interrupt. When the CKCHGE bit is set to 1, a transition similar to active-subactive direct transition is made, and direct transition exception handling is executed after a direct transition. In high-speed mode or medium-speed mode, do not execute a SLEEP instruction when a setting for making a direct transition to subactive mode and a setting for switching the system clock source at a direct transition are made. When the system clock source is to be switched at a direct transition, make sure the SLEEP instruction does not conflict with other interrupt sources. Rev. 3.00 Jan 25, 2006 page 788 of 872 REJ09B0286-0300 Section 27 Power-Down Modes 27.12 Usage Notes 27.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 27.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. 27.12.3 DTC Module Stop Mode If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set the MSTP bit to 1 again. Rev. 3.00 Jan 25, 2006 page 789 of 872 REJ09B0286-0300 Section 27 Power-Down Modes Rev. 3.00 Jan 25, 2006 page 790 of 872 REJ09B0286-0300 Section 28 List of Registers Section 28 List of Registers The register list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) * Registers are listed from the lower allocation addresses. * The MSB-side address is indicated for 16-bit addresses. * Registers are classified by functional modules. * The access size is indicated. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (address order) above. * Reserved bits are indicated by in the bit name column. * The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * 16-bit registers are indicated from the bit on the MSB side. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (address order) above. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 28.1 Register Addresses (Address Order) The access size indicates the numbers of bits. The number of access states indicates the number of states based on the specified reference clock. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Rev. 3.00 Jan 25, 2006 page 791 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Command start register Operation control register Card status register Interrupt control register 0 Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register Command timeout control register Pin mode control register Transfer byte number count register Mode register Command type register Response type register Transfer block number counter H Transfer block number counter L Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 Response register 8 Abbreviation CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR IOMCR TBCR MODER CMDTYR RSPTYR TBNCRH TBNCRL RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FBC0 H'FBC1 H'FBC2 H'FBC3 H'FBC4 H'FBC5 H'FBC6 H'FBCA H'FBCB H'FBCC H'FBCD H'FBCE H'FBCF H'FBD0 H'FBD1 H'FBD3 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FBDB H'FBE0 H'FBE1 H'FBE2 H'FBE3 H'FBE4 H'FBE5 H'FBE6 H'FBE7 H'FBE8 Module MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 792 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name Response register 9 Response register 10 Response register 11 Response register 12 Response register 13 Response register 14 Response register 15 Response register 16 Response register D Data timeout register H Data timeout register L Endpoint 4 packet size register Endpoint data register 0S FIFO valid size register 0SH FIFO valid size register 0SL USB interrupt enable register 1 USB interrupt flag register 1 USB mode control register USB control register 1 Configuration value register RFU/FIFO read request flag register USB port control register USB test register 0 USB test register 1 Endpoint data register 3 FIFO valid size register 3H FIFO valid size register 3L Endpoint data register 2 FIFO valid size register 2H FIFO valid size register 2L Abbreviation RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 RSPRD DTOUTRH DTOUTRL EP4PKTSZR EPDR0S FVSR0SH FVSR0SL USBIER1 USBIFR1 USBMDCR USBCR1 CONFV UDTRFR UPRTCR UTESTR0 UTESTR1 EPDR3 FVSR3H FVSR3L EPDR2 FVSR2H FVSR2L Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FBE9 H'FBEA H'FBEB H'FBEC H'FBED H'FBEE H'FBEF H'FBF0 H'FBF1 H'FBF2 H'FBF3 H'FD81 H'FDAD H'FDAE H'FDAF H'FDB1 H'FDB2 H'FDBC H'FDBD H'FDBE H'FDBF H'FDC0 H'FDC1 H'FDC2 H'FDDD H'FDDE H'FDDF H'FDE1 H'FDE2 H'FDE3 Module MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF MCIF USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 793 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name Endpoint size register 1 Endpoint data register 1 FIFO valid size register 1H FIFO valid size register 1L Endpoint data register 0O FIFO valid size register 0OH FIFO valid size register 0OL Endpoint data register 0I FIFO valid size register 0IH FIFO valid size register 0IL Packet transmission enable register 0 USB interrupt enable register 0 USB interrupt flag register 0 Transfer normal completion interrupt flag register 0 Transfer abnormal completion interrupt flag register 0 USB control/status register 0 Endpoint stall register 0 Endpoint direction register 0 Endpoint reset register 0 Device resume register Interrupt source select register 0 USB control register 0 USB PLL control register 0 Sub-chip module stop control register BH Sub-chip module stop control register BL FIFO status/register/pointer 0 FIFO status/register/pointer 1 Abbreviation EPSZR1 EPDR1 FVSR1H FVSR1L EPDR0O FVSR0OH FVSR0OL EPDR0I FVSR0IH FVSR0IL PTTER0 USBIER0 USBIFR0 TSFR0 TFFR0 USBCSR0 EPSTLR0 EPDIR0 EPRSTR0 DEVRSMR INTSELR0 USBCR0 UPLLCR SUBMSTPBH SUBMSTPBL FSTR0 FSTR1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FDE4 H'FDE5 H'FDE6 H'FDE7 H'FDE9 H'FDEA H'FDEB H'FDED H'FDEE H'FDEF H'FDF0 H'FDF1 H'FDF2 H'FDF3 H'FDF4 H'FDF5 H'FDF6 H'FDF7 H'FDF8 H'FDF9 H'FDFA H'FDFD H'FDFE H'FE3E H'FE3F H'FEA0 H'FEA1 Module USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB SYSTEM SYSTEM RFU RFU Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 794 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 Register Name FIFO status/register/pointer 2 FIFO status/register/pointer 3 Data transfer control register A Data transfer control register B Data transfer ID register Data transfer status register C Data transfer ID read/write select register A Data transfer ID read/write select register B Data transfer status register A Data transfer status register B Data transfer control register D Data transfer interrupt enable register Data transfer register select register IIC operation reservation adapter control register_0 IIC operation reservation adapter status register A_0 IIC operation reservation adapter status register B_0 IIC operation reservation adapter status register C_0 IIC operation reservation adapter data register_0 IIC operation reservation adapter command register_0 I2C data shift register_0 IIC operation reservation adapter count register_0 IIC operation reservation adapter control register_1 Abbreviation FSTR2 FSTR3 DTCRA DTCRB DTIDR DTSTRC DTIDSRA DTIDSRB DTSTRA DTSTRB DTCRD DTIER DTRSR ICCRX_0 ICSRA_0 ICSRB_0 ICSRC_0 ICDRX_0 ICCMD_0 ICDRS_0 ICCNT_0 ICCRX_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FEA2 H'FEA3 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEAC H'FEAD H'FEAE H'FEB0 H'FEB1 H'FEB2 H'FEB3 H'FEB4 H'FEB5 H'FEB6 H'FEB7 H'FEB8 Module RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_1 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 Rev. 3.00 Jan 25, 2006 page 795 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name IIC operation reservation adapter status register A_1 IIC operation reservation adapter status register B_1 IIC operation reservation adapter status register C_1 IIC operation reservation adapter data register_1 IIC operation reservation adapter command register_1 I2C data shift register_1 IIC operation reservation adapter count register_1 Serial enhanced mode register_0 Serial RFU enable register 0 Serial enhanced mode register_2 Serial RFU enable register 2 CRC control register CRC data input register CRC data output register H CRC data output register L Keyboard comparator control register Serial interface control register Interrupt control register D Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L Abbreviation ICSRA_1 ICSRB_1 ICSRC_1 ICDRX_1 ICCMD_1 ICDRS_1 ICCNT_1 SEMR_0 SCIDTER_0 SEMR_2 SCIDTER_2 CRCCR CRCDIR CRCDORH CRCDORL KBCOMP SCICR ICRD ICRA ICRB ICRC ISR ISCRH ISCRL Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FEE4 H'FEE5 H'FEE7 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED Module IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 SCI_0 SCI_0 SCI_2 SCI_2 CRC CRC CRC CRC A/D converter SCI_1 INT INT INT INT INT INT INT Data Bus Width 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 796 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC vector register Address break control register Break address register A Break address register B Break address register C IRQ enable register 16 IRQ status register 16 IRQ sense control register 16H IRQ sense control register 16L IRQ sense port select register 16 IRQ sense port select register Port control register 0 Bus control register 2 Wait state control register 2 Peripheral clock select register System control register 2 Standby control register Low power control register Module stop control register H Module stop control register L Flash memory control register 1 Flash memory control register 2 Erase block setting register 1 Erase block setting register 2 Serial mode register_1 Abbreviation DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 BCR2 WSCR2 PCSR SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL FLMCR1 FLMCR2 EBR1 EBR2 SMR_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FEFE H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF80 H'FF81 H'FF82 H'FF83 H'FF88 Module DTC DTC DTC DTC DTC DTC INT INT INT INT INT INT INT INT INT INT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 BSC BSC PWM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM FLASH FLASH FLASH FLASH SCI_1 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 797 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name I C bus control register_1 Bit rate register_1 I2C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 I2C bus data register_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 Timer interrupt enable register Timer control/status register Free-running counter H Free-running counter L Output control register AH Output control register BH Output control register AL Output control register BL Timer control register Timer output compare control register Input capture register AH Output control register ARH Input capture register AL Output control register ARL Input capture register BH Output control register AFH Input capture register BL Output control register AFL 2 2 Abbreviation ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF88 H'FF89 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF8E H'FF8E H'FF8F H'FF8F H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF94 H'FF95 H'FF95 H'FF96 H'FF97 H'FF98 H'FF98 H'FF99 H'FF99 H'FF9A H'FF9A H'FF9B H'FF9B Module IIC_1 SCI_1 IIC_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 IIC_1 IIC_1 IIC_1 IIC_1 FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 798 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Input capture register CH Output compare register DMH Input capture register CL Output compare register DML Input capture register DH Input capture register DL Serial mode register_2 PWMX (D/A) control register PWMX (D/A) data register AH PWMX (D/A) data register AL Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 PWMX (D/A) data register BH PWMX (D/A) counter H PWMX (D/A) data register BL PWMX (D/A) counter L Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Abbreviation ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADRBH DACNTH DADRBL DACNTL TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF9C H'FF9C H'FF9D H'FF9D H'FF9E H'FF9F H'FFA0 H'FFA0 H'FFA0 H'FFA1 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA6 H'FFA6 H'FFA7 H'FFA7 H'FFA8 H'FFA8 (write) H'FFA9 (read) H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD Module FRT FRT FRT FRT FRT FRT SCI_2 PWMX PWMX PWMX SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 PWMX PWMX PWMX PWMX WDT WDT WDT PORT PORT PORT PORT PORT Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 799 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port 8 data direction register Port 7 input data register Port 8 data register Port 9 data direction register Port 9 data register IRQ enable register Serial timer control register System control register Mode control register Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Abbreviation P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P8DDR P7PIN P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBD H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM SYSTEM SYSTEM BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 Rev. 3.00 Jan 25, 2006 page 800 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 PWM output enable register B PWM output enable register A PWM data polarity register B PWM data polarity register A PWM register select PWM data registers 0-15 Serial mode register_0 I C bus control register_0 Bit rate register_0 I2C bus status register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 I2C bus data register_0 Second slave address register_0 I C bus mode register_0 Slave address register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL 2 2 Abbreviation TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0 to 15 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD8 H'FFD9 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 Module TMR_0 TMR_1 TMR_0 TMR_1 PWM PWM PWM PWM PWM PWM SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 IIC_0 IIC_0 IIC_0 IIC_0 A/D converter A/D converter A/D converter A/D converter Data Bus Width 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 801 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1 Timer counter_1 Timer counter_1 Keyboard matrix interrupt mask register 6 Port 6 pull-up MOS control register Keyboard matrix interrupt mask register A Wakeup event interrupt mask register 3 Timer control register_X Timer control register_Y Timer control/status register_X Timer control/status register_Y Input capture register R Time constant register A_Y Input capture register F Time constant register B_Y Abbreviation ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCNT_1 KMIMR6 KMPCR6 KMIMRA WUEMR3 TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEA (write) H'FFEB (read) H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF0 H'FFF0 H'FFF1 H'FFF1 H'FFF2 H'FFF2 H'FFF3 H'FFF3 Module A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter WDT_1 WDT_1 WDT_1 INT PORT INT INT TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 Rev. 3.00 Jan 25, 2006 page 802 of 872 REJ09B0286-0300 Section 28 List of Registers Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Timer counter_X Timer counter_Y Time constant register Timer input select register Time constant register A_X Time constant register B_X D/A data register 0 D/A data register 1 D/A control register Timer connection register I Timer connection register O Timer connection register S Edge sense register Abbreviation TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X DADR0 DADR1 DACR TCONRI TCONRO TCONRS SEDGR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFF4 H'FFF4 H'FFF5 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFC H'FFFD H'FFFE H'FFFF Module TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_X D/A converter D/A converter D/A converter Timer connection Timer connection Timer connection Timer connection Data Bus Width 16 16 16 16 16 16 8 8 8 8 8 8 8 Rev. 3.00 Jan 25, 2006 page 803 of 872 REJ09B0286-0300 Section 28 List of Registers 28.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 64-bit registers are shown as 8 lines and 16-bit registers as 2 lines. Register Abbreviation Bit 7 CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR IOMCR TBCR MODER CMDTYR RSPTYR TBNCRH TBNCRL RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 Start Bit 31 Bit 23 Bit 15 Bit 7 CRC -- CMDOFF BUSY FEIE INTRQ2E FEI -- CLKON -- SPCNUM -- -- -- -- Bit 15 Bit 7 Bit 135 Bit 127 Bit 119 Bit 111 Bit 103 Bit 95 Bit 87 Bit 79 Bit 6 Host Bit 30 Bit 22 Bit 14 Bit 6 CRC -- -- FIFO_FULL Bit 5 Bit 5 Bit 29 Bit 21 Bit 13 Bit 5 CRC -- Bit 4 Bit 4 Bit 28 Bit 20 Bit 12 Bit 4 CRC -- Bit 3 Bit 3 Bit 27 Bit 19 Bit 11 Bit 3 CRC -- -- DTBUSY CRPIE -- CRPI -- -- -- -- C3 -- TY3 -- Bit 11 Bit 3 Bit 131 Bit 123 Bit 115 Bit 107 Bit 99 Bit 91 Bit 83 Bit 75 Bit 2 Bit 2 Bit 26 Bit 18 Bit 10 Bit 2 CRC -- -- Bit 1 Bit 1 Bit 25 Bit 17 Bit 9 Bit 1 CRC -- -- Bit 0 Bit 0 Bit 24 Bit 16 Bit 8 Bit 0 End START -- REQ BTIE CTERIE BTI CTERI CSEL0 CTSEL0 MMCPE C0 SPI TY0 RTY0 Bit 8 Bit 0 Bit 128 Bit 120 Bit 112 Bit 104 Bit 96 Bit 88 Bit 80 Bit 72 Module MCIF RD_CONTI DATAEN FIFO_EMPTY CWRE DTIE -- DTI -- -- -- -- -- -- TY4 RTY4 Bit 12 Bit 4 Bit 132 Bit 124 Bit 116 Bit 108 Bit 100 Bit 92 Bit 84 Bit 76 DTBUSY_TU -- FFIE INTRQ1E FFI -- -- -- CHIPSA -- -- -- -- Bit 14 Bit 6 Bit 134 Bit 126 Bit 118 Bit 110 Bit 102 Bit 94 Bit 86 Bit 78 DRPIE INTRQ0E DRPI -- -- -- -- -- -- TY5 RTY5 Bit 13 Bit 5 Bit 133 Bit 125 Bit 117 Bit 109 Bit 101 Bit 93 Bit 85 Bit 77 CMDIE CRCERIE CMDI CRCERI CSEL2 -- -- C2 -- TY2 RTY2 Bit 10 Bit 2 Bit 130 Bit 122 Bit 114 Bit 106 Bit 98 Bit 90 Bit 82 Bit 74 DBSYIE DTERIE DBSYI DTERI CSEL1 -- DIRME C1 -- TY1 RTY1 Bit 9 Bit 1 Bit 129 Bit 121 Bit 113 Bit 105 Bit 97 Bit 89 Bit 81 Bit 73 Rev. 3.00 Jan 25, 2006 page 804 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 PSPRD DTOUTRH DTOUTRL EP4PKTSZR EPDR0S FVSR0SH FVSR0SL USBIER1 USBIFR1 USBMDCR USBCR1 CONFV UDTRFR UPRTCR UTESTR0 UTESTR1 EPDR3 FVSR3H FVSR3L EPDR2 FVSR2H FVSR2L Bit 71 Bit 63 Bit 55 Bit 47 Bit 39 Bit 31 Bit 23 Bit 15 Bit 7 Bit 7 DTOUT15 DTOUT7 PS7 D7 -- N7 -- -- -- -- -- -- -- TEST15 TEST7 D7 -- N7 D7 -- N7 Bit 6 Bit 70 Bit 62 Bit 54 Bit 46 Bit 38 Bit 30 Bit 22 Bit 14 Bit 6 Bit 6 DTOUT14 DTOUT6 PS6 D6 -- N6 -- -- -- -- -- -- -- TEST14 TEST6 D6 -- N6 D6 -- N6 Bit 5 Bit 69 Bit 61 Bit 53 Bit 45 Bit 37 Bit 29 Bit 21 Bit 13 Bit 5 Bit 5 DTOUT13 DTOUT5 PS5 D5 -- N5 -- -- -- -- CONFV0 -- -- TEST13 TEST5 D5 -- N5 D5 -- N5 Bit 4 Bit 68 Bit 60 Bit 52 Bit 44 Bit 36 Bit 28 Bit 20 Bit 12 Bit 4 Bit 4 DTOUT12 DTOUT4 PS4 D4 -- N4 -- -- -- -- INTV1 -- -- TEST12 TEST4 D4 -- N4 D4 -- N4 Bit 3 Bit 67 Bit 59 Bit 51 Bit 43 Bit 35 Bit 27 Bit 19 Bit 11 Bit 3 Bit 3 DTOUT11 DTOUT3 PS3 D3 -- N3 -- -- -- -- INTV0 -- -- TEST11 TEST3 D3 -- N3 D3 -- N3 Bit 2 Bit 66 Bit 58 Bit 50 Bit 42 Bit 34 Bit 26 Bit 18 Bit 10 Bit 2 Bit 2 DTOUT10 DTOUT2 PS2 D2 -- N2 -- -- -- -- ALTV2 -- PCNMD2 TEST10 TEST2 D2 -- N2 D2 -- N2 Bit 1 Bit 65 Bit 57 Bit 49 Bit 41 Bit 33 Bit 25 Bit 17 Bit 9 Bit 1 Bit 1 DTOUT9 DTOUT1 PS1 D1 N9 N1 SETCE SETC SCME VBUSS ALTV1 -- PCNMD1 TEST9 TEST1 D1 N9 N1 D1 N9 N1 Bit 0 Bit 64 Bit 56 Bit 48 Bit 40 Bit 32 Bit 24 Bit 16 Bit 8 Bit 0 Bit 0 DTOUT8 DTOUT0 PS0 D0 N8 N0 SETIE SETI SETICNT CK48READY Module MCIF USB ALTV0 EP5UDTR PCNMD0 TEST8 TEST0 D0 N8 N0 D0 N8 N0 Rev. 3.00 Jan 25, 2006 page 805 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 EPSZR1 EPDR1 FVSR1H FVSR1L EPDR0O FVSR0OH FVSR0OL EPDR0I FVSR0IH FVSR0IL PTTER0 USBIER0 USBIFR0 TSFR0 TFFR0 USBCSR0 EPSTLR0 EPDIR0 EPRSTR0 DEVRSMR INTSELR0 USBCR0 UPLLCR EP1SZ3 D7 -- N7 D7 -- N7 D7 -- N7 -- -- TS -- -- -- -- -- -- -- TSELB FADSEL -- Bit 6 EP1SZ2 D6 -- N6 D6 -- N6 D6 -- N6 -- UDTRE TF EP5TS EP5TF -- EP5STL EP5DIR EP5RST -- EPIBS2 -- -- Bit 5 EP1SZ1 D5 -- N5 D5 -- N5 D5 -- N5 EP4TE BRSTE UDTRF EP4TS EP4TF -- EP4STL EP4DIR EP4RST -- EPIBS1 -- PFSEL2 Bit 4 EP1SZ0 D4 -- N4 D4 -- N4 D4 -- N4 EP3TE SOFE BRSTF EP3TS EP3TF -- EP3STL EP3DIR EP3RST -- EPIBS0 UIFRST CKSEL2 Bit 3 EP2SZ3 D3 -- N3 D3 -- N3 D3 -- N3 EP2TE SPNDE SOFF EP2TS EP2TF Bit 2 EP2SZ2 D2 -- N2 D2 -- N2 D2 -- N2 EP1TE TFE SPNDOF EP1TS EP1TF Bit 1 EP2SZ1 D1 N9 N1 D1 N9 N1 D1 N9 N1 EP0ITE TSE SPNDIF EP0ITS EP0ITF EP0OTC -- -- EP0IRST RWUPS EPICS1 FPLLRST PFSEL1 Bit 0 EP2SZ0 D0 N8 N0 D0 N8 N0 D0 N8 N0 -- SETUPE SETUPF EP0OTS EP0OTF -- EP0STL -- EP0ORST DVR EPICS0 FSRST PFSEL0 Module USB EP0STOP EPIVLD EP2STL EP2DIR EP2RST -- TSELC -- CKSEL1 EP1STL EP1DIR EP1RST -- EPICS2 -- CKSEL0 SUBMSTPBH SMSTPB15 SMSTPB14 SMSTPB13 SMSTPB12 SMSTPB11 SMSTPB10 SMSTPB9 SMSTPB8 SYSTEM SUBMSTPBL SMSTPB7 SMSTPB6 SMSTPB5 SMSTPB4 SMSTPB3 SMSTPB2 SMSTPB1 SMSTPB0 FSTR0 FSTR1 FSTR2 FSTR3 Bit 31 Bit 23 Bit 15 Bit 7 Bit 30 Bit 22 Bit 14 Bit 6 Bit 29 Bit 21 Bit 13 Bit 5 Bit 28 Bit 20 Bit 12 Bit 4 Bit 27 Bit 19 Bit 11 Bit 3 Bit 26 Bit 18 Bit 10 Bit 2 Bit 25 Bit 17 Bit 9 Bit 1 Bit 24 Bit 16 Bit 8 Bit 0 RFU Rev. 3.00 Jan 25, 2006 page 806 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 DTCRA DTCRB DTIDR DTSTRC DTIDSRA DTIDSRB DTSTRA DTSTRB DTCRD DTIER DTRSR ICCRX_0 ICSRA_0 ICSRB_0 ICSRC_0 ICDRX_0 ICCMD_0 ICDRS_0 ICCNT_0 ICCRX_1 ICSRA_1 ICSRB_1 ICSRC_1 ICDRX_1 ICCMD_1 ICDRS_1 ICCNT_1 SEMR_0 SCIDTER_0 SEMR_2 SCIDTER_2 IDE-A Bit 6 IDE-B Bit 5 PMD1 Bit 4 PMD0 EMPTYE ID-A0 EMPTY IDRW12 IDRW4 -- -- -- -- RS SRIC SCLI ABRT SRREQ ICDR4 Bit 4 ICDR4 CNTS0 SRIC SCLI ABRT SRREQ ICDR4 Bit 4 ICDR4 CNTS0 ABCS -- ABCS -- Bit 3 Sz LOAD ID-B3 OVER_R IDRW11 IDRW3 DTF3 DTEF3 DTE3 DTIE3 POS1 BBSYX/ CLR3 MSTX ALST MASX ICDR3 Bit 3 ICDR3 BBC3 BBSYX/ CLR3 MSTX ALST MASX ICDR3 Bit 3 ICDR3 BBC3 ACS4 -- ACS4 -- Bit 2 BUD2 MARK ID-B2 OVER_W IDRW10 IDRW2 DTF2 DTEF2 DTE2 DTIE2 POS0 --/ CLR2 TRSX DERR TDRE ICDR2 Bit 2 ICDR2 BBC2 --/ CLR2 TRSX DERR TDRE ICDR2 Bit 2 ICDR2 BBC2 ACS2 -- ACS2 -- Bit 1 BUD1 REST ID-B1 -- IDRW9 IDRW1 DTF1 DTEF1 DTE1 DTIE1 STS1 AASHIT/ CLR1 WAITX TOVR SDRF ICDR1 Bit 1 ICDR1 BBC1 AASHIT/ CLR1 WAITX TOVR SDRF ICDR1 Bit 1 ICDR1 BBC1 ACS1 -- ACS1 -- Bit 0 BUD0 STCLR ID-B0 -- IDRW8 IDRW0 DTF0 DTEIE DTE0 DTIE0 STS0 ACKBX/ CLR0 ACKXE NACK RDRF ICDR0 Bit 0 ICDR0 BBC0 ACKBX/ CLR0 ACKXE NACK RDRF ICDR0 Bit 0 ICDR0 BBC0 ACS0 -- ACS0 -- Module RFU BOVF_RE BOVF_WE FULLE ID-A3 BOVF_R IDRW15 IDRW7 -- -- -- -- CHS2 ICXE SDAO CREQ MTREQ ICDR7 Bit 7 ICDR7 CNTE ICXE SDAO CREQ MTREQ ICDR7 Bit 7 ICDR7 CNTE SSE TDRE_DTE ID-A2 BOVF_W IDRW14 IDRW6 -- -- -- -- CHS1 CRIC SCLO CERR MRREQ ICDR6 Bit 6 ICDR6 STOPIMX CRIC SCLO CERR MRREQ ICDR6 Bit 6 ICDR6 STOPIMX -- RDRF_DTE ID-A1 FULL IDRW13 IDRW5 -- -- -- -- CHS0 MRIC SDAI STOP STREQ ICDR5 Bit 5 ICDR5 CNTS1 MRIC SDAI STOP STREQ ICDR5 Bit 5 ICDR5 CNTS1 -- -- -- -- IIC_0 IIC_1 SCI_0 SSE TDRE_DTE -- RDRF_DTE SCI_2 Rev. 3.00 Jan 25, 2006 page 807 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 CRCCR CRCDIR CRCDORH CRCDORL KBCOMP SCICR ICRD ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 DORCLR Bit 7 Bit 15 Bit 7 -- IrE IRQ8-11 IRQ0 A/D converter SCI_0 IRQ7F IRQ7SCB IRQ3SCB IRQ0 OCIB CMIB1 TXI1 USBI0 SWDTE CMF A23 A15 A7 IRQ15E IRQ15F Bit 6 -- Bit 6 Bit 14 Bit 6 -- IrCKS2 IRQ12-15 IRQ1 FRT SCI_1 IRQ6F IRQ7SCA IRQ3SCA IRQ1 IICM0 CMIAY RXI2 USBI1 DTVEC6 -- A22 A14 A6 IRQ14E IRQ14F Bit 5 -- Bit 5 Bit 13 Bit 5 -- IrCKS1 -- IRQ2-3 -- SCI_2 IRQ5F IRQ6SCB IRQ2SCB IRQ2 IICR0 CMIBY TXI2 USBI2 DTVEC5 -- A21 A13 A5 IRQ13E IRQ13F Bit 4 -- Bit 4 Bit 12 Bit 4 SCANE IrCKS0 -- IRQ4-5 TMR_X IIC_0 IRQ4F IRQ6SCA IRQ2SCA IRQ3 IICT0 -- IICM1 USBI3 DTVEC4 -- A20 A12 A4 IRQ12E IRQ12F Bit 3 -- Bit 3 Bit 11 Bit 3 KBADE -- -- IRQ6-7 TMR_0 IIC_1 IRQ3F IRQ5SCB IRQ1SCB ADI -- CMIAX IICR1 -- DTVEC3 -- A19 A11 A3 IRQ11E IRQ11F Bit 2 LMS Bit 2 Bit 10 Bit 2 KBCH2 -- -- DTC TMR_1 -- IRQ2F IRQ5SCA IRQ1SCA ICIA CMIA0 RXI0 IICT1 -- DTVEC2 -- A18 A10 A2 IRQ10E IRQ10F Bit 1 G1 Bit 1 Bit 9 Bit 1 KBCH1 -- -- WDT_0 TMR_Y -- IRQ1F IRQ4SCB IRQ0SCB ICIB CMIB0 TXI0 MMCIA -- DTVEC1 -- A17 A9 A1 IRQ9E IRQ9F Bit 0 G0 Bit 0 Bit 8 Bit 0 KBCH0 -- MCIF WDT_1 -- USB IRQ0F IRQ4SCA IRQ0SCA OCIA CMIA1 RXI1 CMIBX -- DTVEC0 BIE A16 A8 -- IRQ8E IRQ8F Module CRC A/D converter SCI_1 INT DTC INT IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB ISS15 ISS7 TMI0S ISS14 ISS6 TMI1S ISS13 ISS5 TMIXS ISS12 ISS4 TMIYS ISS11 ISS3 MMCS IRQ9SCA ISS10 ISS2 -- IRQ8SCB ISS9 ISSR1 -- IRQ8SCA ISS8 ISS0 -- PORT Rev. 3.00 Jan 25, 2006 page 808 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 BCR2 WSCR2 PCSR SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL FLMCR1 FLMCR2 EBR1 EBR2 SMR_1* ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1* RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OWEAC WMS10 -- KWUL1 SSBY DTON MSTP15 MSTP7 FWE FLER -- EB7 C/A (GM) ICE Bit 7 ESTP TIE Bit 7 TDRE (TDRE) Bit 7 -- ICDR7 SVAX6 MLS SVA6 ICIAE ICFA Bit 15 Bit 7 Bit 15 Bit 15 Bit 6 OWENC WC11 -- KWUL0 STS2 LSON MSTP14 MSTP6 SWE -- -- EB6 CHR/ (BLK) IEIC Bit 6 STOP RIE Bit 6 RDRF (RDRF) Bit 6 -- ICDR6 SVAX5 WAIT SVA5 ICIBE ICFB Bit 14 Bit 6 Bit 14 Bit 14 Bit 5 ABWCP WC10 PWCKXB P6PUE STS1 NESEL MSTP13 MSTP5 -- -- -- EB5 PE/ (PE) MST Bit 5 IRTR TE Bit 5 ORER (ORER) Bit 5 -- ICDR5 SVAX4 CKS2 SVA4 ICICE ICFC Bit 13 Bit 5 Bit 13 Bit 13 Bit 4 ASTCP WMS21 PWCKXA -- STS0 EXCLE MSTP12 MSTP4 -- -- -- EB4 O/E (O/E) TRS Bit 4 AASX RE Bit 4 FER (ERS) Bit 4 -- ICDR4 SVAX3 CKS1 SVA3 ICIDE ICFD Bit 12 Bit 4 Bit 12 Bit 12 Bit 3 ADFULLE WMS20 -- -- Bit 2 EXCKS WC22 PWCKB CKCHGE Bit 1 BUSDIVE WC21 PWCKA -- SCK1 -- MSTP9 MSTP1 E ESU EB9 EB1 CKS1 (CKS1) IRIC Bit 1 ADZ CKE1 Bit 1 MPB (MPB) Bit 1 -- ICDR1 SVAX0 BC1 SVA0 OVIE OVF Bit 9 Bit 1 Bit 9 Bit 9 Bit 0 CPCSE WC20 -- PLCKS SCK0 -- MSTP8 MSTP0 P PSU EB8 EB0 CKS0 (CKS0) SCP Bit 0 ACKB CKE0 Bit 0 MPBT (MPBT) Bit 0 SMIF ICDR0 FSX BC0 FS -- CCLRA Bit 8 Bit 0 Bit 8 Bit 8 Module BSC PWM SYSTEM DTSPEED SCK2 -- MSTP11 MSTP3 EV -- EB11 EB3 STOP (BCP1) ACKE Bit 3 AL MPIE Bit 3 PER (PER) Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 OCIAE OCFA Bit 11 Bit 3 Bit 11 Bit 11 -- MSTP10 MSTP2 PV -- EB10 EB2 MP/ (BCP0) BBSY Bit 2 AAS TEIE Bit 2 TEND (TEND) Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 OCIBE OCFB Bit 10 Bit 2 Bit 10 Bit 10 FLASH SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 FRT Rev. 3.00 Jan 25, 2006 page 809 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2* DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2* RDR_2 SCMR_2 DADRBH DACNTH DADRBL DACNTL Bit 7 Bit 7 IEDGA ICRDMS Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 7 C/A (GM) -- DA13 DA5 Bit 7 TIE Bit 7 TDRE (TDRE) Bit 7 -- DA13 UC7 DA5 UC8 Bit 6 Bit 6 Bit 6 IEDGB OCRAMS Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 6 Bit 5 Bit 5 Bit 5 IEDGC ICRS Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 5 Bit 4 Bit 4 Bit 4 IEDGD OCRS Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 4 O/E (O/E) -- DA10 DA2 Bit 4 RE Bit 4 FER (ERS) Bit 4 -- DA10 UC4 DA2 UC11 Bit 3 Bit 3 Bit 3 BUFEA OEA Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 3 STOP (BCP1) OEB DA9 DA1 Bit 3 MPIE Bit 3 PER (PER) Bit 3 SDIR DA9 UC3 DA1 UC12 Bit 2 Bit 2 Bit 2 BUFEB OEB Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 2 MP (BCP0) OEA DA8 DA0 Bit 2 TEIE Bit 2 TEND (TEND) Bit 2 SINV DA8 UC2 DA0 UC13 Bit 1 Bit 1 Bit 1 CKS1 OLVLA Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 1 CKS1 (CKS1) OS DA7 CFS Bit 1 CKE1 Bit 1 MPB (MPB) Bit 1 -- DA7 UC1 CFS -- Bit 0 Bit 0 Bit 0 CKS0 OLVLB Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 0 CKS0 (CKS0) CKS DA6 -- Bit 0 CKE0 Bit 0 MPBT (MPBT) Bit 0 SMIF DA6 UC0 REGS REGS Module FRT CHR (BLK) PE (PE) PWME DA12 DA4 Bit 6 RIE Bit 6 RDRF (RDRF) Bit 6 -- DA12 UC6 DA4 UC9 -- DA11 DA3 Bit 5 TE Bit 5 ORER (ORER) Bit 5 -- DA11 UC5 DA3 UC10 SCI_2 PWMX SCI_2 PWMX Rev. 3.00 Jan 25, 2006 page 810 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P8DDR P7PIN P8DR P9DDR P9DR IER STCR SYSCR MDCR OVF Bit 7 -- -- -- P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR P57DDR P67DDR P57DR P67DR P87DDR P77PIN P87DR P97DDR P97DR IRQ7E -- CS256E EXPE Bit 6 WT/IT Bit 6 -- -- -- P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR P56DDR P66DDR P56DR P66DR P86DDR P76PIN P86DR P96DDR P96DR IRQ6E IICX1 IOSE -- Bit 5 TME Bit 5 -- -- -- P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR P55DDR P65DDR P55DR P65DR P85DDR P75PIN P85DR P95DDR P95DR IRQ5E IICX0 INTM1 -- Bit 4 -- Bit 4 -- -- -- P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR P54DDR P64DDR P54DR P64DR P84DDR P74PIN P84DR P94DDR P94DR IRQ4E IICE INTM0 -- Bit 3 RST/NMI Bit 3 -- -- -- P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR P53DDR P63DDR P53DR P63DR P83DDR P73PIN P83DR P93DDR P93DR IRQ3E FLSHE XRST -- Bit 2 CKS2 Bit 2 -- -- -- P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR P82DDR P72PIN P82DR P92DDR P92DR IRQ2E -- NMIEG MDS2 Bit 1 CKS1 Bit 1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR P81DDR -- P81DR P91DDR P91DR IRQ1E ICKS1 KINWUE MDS1 Bit 0 CKS0 Bit 0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR P80DDR -- P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 Module WDT_0 PORT INT SYSTEM Rev. 3.00 Jan 25, 2006 page 811 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0-15 SMR_0* ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0* RDR_0 SCMR_0 ICDRS_0 SARX_0 ICMR_0 SAR_0 -- ABW256 CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 OE15 OE7 OS15 OS7 PWCKE Bit 7 C/A (GM) ICE Bit 7 ESTP TIE Bit 7 TDRE (TDRE) Bit 7 -- ICDR7 SVAX6 MLS SVA6 Bit 6 ICIS AST256 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 OE14 OE6 OS14 OS6 PWCKS Bit 6 Bit 5 BRSTRM ABW OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 OE13 OE5 OS13 OS5 -- Bit 5 Bit 4 BRSTS1 AST CCLR1 CCLR1 ADTE -- Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 OE12 OE4 OS12 OS4 -- Bit 4 O/E (O/E) TRS Bit 4 AASX RE Bit 4 FER (ERS) Bit 4 -- ICDR4 SVAX3 CKS1 SVA3 Bit 3 BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 OE11 OE3 OS11 OS3 RS3 Bit 3 STOP (BCP1) ACKE Bit 3 AL MPIE Bit 3 PER (PER) Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 Bit 2 CFE WMS0 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 OE10 OE2 OS10 OS2 RS2 Bit 2 MP (BCP0) BBSY Bit 2 AAS TEIE Bit 2 TEND (TEND) Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 Bit 1 IOS1 WC1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 OE9 OE1 OS9 OS1 RS1 Bit 1 CKS1 (CKS1) IRIC Bit 1 ADZ CKE1 Bit 1 MPB (MPB) Bit 1 -- ICDR1 SVAX0 BC1 SVA0 Bit 0 IOS0 WC0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 OE8 OE0 OS8 OS0 RS0 Bit 0 CKS0 (CKS0) SCP Bit 0 ACKB CKE0 Bit 0 MPBT (MPBT) Bit 0 SMIF ICDR0 FSX BC0 FS Module BSC TMR_0, TMR_1 PWM CHR (BLK) PE (PE) IEIC Bit 6 STOP RIE Bit 6 RDRF (RDRF) Bit 6 -- ICDR6 SVAX5 WAIT SVA5 MST Bit 5 IRTR TE Bit 5 ORER (ORER) Bit 5 -- ICDR5 SVAX4 CKS2 SVA4 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 IIC_0 Rev. 3.00 Jan 25, 2006 page 812 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 KMIMR6 KMPCR6 KMIMRA WUEMR3 TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit 7 KMIM7 KM7PCR -- WUEM15 CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 -- Bit 7 Bit 7 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 6 KMIM6 KM6PCR -- WUEM14 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 -- Bit 6 Bit 6 Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 5 KMIM5 KM5PCR -- WUEM13 OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 -- Bit 5 Bit 5 Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS Bit 4 KMIM4 KM4PCR -- WUEM12 CCLR1 CCLR1 ICF ICIE Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 -- Bit 4 Bit 4 Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- RST/NMI Bit 3 KMIM3 KM3PCR -- WUEM11 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 -- Bit 3 Bit 3 Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- CKS2 Bit 2 KMIM2 KM2PCR -- WUEM10 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 -- Bit 2 Bit 2 Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 1 KMIM1 KM1PCR KMIM9 WUEM9 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 -- Bit 1 Bit 1 Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Bit 0 KMIM0 KM0PCR KMIM8 WUEM8 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 IS Bit 0 Bit 0 Module A/D converter WDT_1 INT PORT INT TMR_Y, TMR_X Rev. 3.00 Jan 25, 2006 page 813 of 872 REJ09B0286-0300 Section 28 List of Registers Register Abbreviation Bit 7 DADR0 DADR1 DACR TCONRI TCONRO TCONRS SEDGR Bit 7 Bit 7 DAOE1 SIMOD1 HOE TMRX/Y VEDG Bit 6 Bit 6 Bit 6 DAOE0 SIMOD0 VOE ISGENE HEDG Bit 5 Bit 5 Bit 5 DAE SCONE CLOE HOMOD1 CEDG Bit 4 Bit 4 Bit 4 -- ICST CBOE HOMOD0 HFEDG Bit 3 Bit 3 Bit 3 -- HFINV HOINV VOMOD1 VFEDG Bit 2 Bit 2 Bit 2 -- VFINV VOINV VOMOD0 PREDG Bit 1 Bit 1 Bit 1 -- HIINV CLOINV CLMOD1 IHI Bit 0 Bit 0 Bit 0 -- VIINV CBOINV CLMOD0 IVI Module D/A converter Timer connection Note: * Some bits have different names in normal mode and smart card interface mode. The bit name in smart card interface mode is enclosed in parentheses. Rev. 3.00 Jan 25, 2006 page 814 of 872 REJ09B0286-0300 Section 28 List of Registers 28.3 Register States in Each Operating Mode Register Abbreviation CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR IOMCR TBCR MODER CMDTYR RSPTYR TBNCRH TBNCRL RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module MCIF Rev. 3.00 Jan 25, 2006 page 815 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- --*1 --*1 --*1 --*1 --*1 --*1 --*1 -- --*1 --*1 -- -- -- --*1 --*1 --*1 --*1 --*1 --*1 --*1 --*1 --*1 --* 1 Register Abbreviation RSPR13 RSPR14 RSPR15 RSPR16 PSPRD DTOUTRH DTOUTRL EP4PKTSZR EPDR0S FVSR0SH FVSR0SL USBIER1 USBIFR1 USBMDCR USBCR1 CONFV UDTRFR UPRTCR UTESTR0 UTESTR1 EPDR3 FVSR3H FVSR3L EPDR2 FVSR2H FVSR2L EPSZR1 EPDR1 FVSR1H FVSR1L EPDR0O FVSR0OH FVSR0OL EPDR0I FVSR0IH FVSR0IL PTTER0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module MCIF Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USB --*1 --*1 --*1 --*1 --*1 --*1 -- Rev. 3.00 Jan 25, 2006 page 816 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch --*1 --*1 --*1 --*1 --*1 --*1 --*1 -- --*1 --*1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Register Abbreviation USBIER0 USBIFR0 TSFR0 TFFR0 USBCSR0 EPSTLR0 EPDIR0 EPRSTR0 DEVRSMR INTSELR0 USBCR0 UPLLCR SUBMSTPBH SUBMSTPBL FSTR0 FSTR1 FSTR2 FSTR3 DTCRA DTCRB DTIDR DTSTRC DTIDSRA DTIDSRB DTSTRA DTSTRB DTCRD DTIER DTRSR ICCRX_0 ICSRA_0 ICSRB_0 ICSRC_0 ICDRX_0 ICCMD_0 ICDRS_0 ICCNT_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module USB SYSTEM RFU IIC_0 Rev. 3.00 Jan 25, 2006 page 817 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Register Abbreviation ICCRX_1 ICSRA_1 ICSRB_1 ICSRC_1 ICDRX_1 ICCMD_1 ICDRS_1 ICCNT_1 SEMR_0 SCIDTER_0 SEMR_2 SCIDTER_2 CRCCR CRCDIR CRCDORH CRCDORL KBCOMP SCICR ICRD ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module IIC_1 SCI_0 SCI_2 CRC A/D converter SCI_1 INT DTC INT Rev. 3.00 Jan 25, 2006 page 818 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- --*3 --*2 *3 --*3 --*3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Register Abbreviation ISR16 ISCR16H ISCR16L ISSR16 ISSR PTCNT0 BCR2 WSCR2 PCSR SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL FLMCR1 FLMCR2 EBR1 EBR2 SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module INT PORT BSC PWM SYSTEM FLASH Initialized*2 -- Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized*2 Initialized*2 -- Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- Initialized*2 Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized FRT IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 Rev. 3.00 Jan 25, 2006 page 819 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- Register Abbreviation OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADRBH DACNTH DADRBL DACNTL TCSR_0 TCNT_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized -- -- -- Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module FRT SCI_2 PWMX SCI_2 PWMX WDT_0 Rev. 3.00 Jan 25, 2006 page 820 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Register Abbreviation PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P8DDR P7PIN P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module PORT INT SYSTEM BSC TMR_0, TMR_1 Rev. 3.00 Jan 25, 2006 page 821 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Register Abbreviation TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR0-15 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TMR_0, TMR_1 PWM SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 IIC_0 A/D converter WDT_1 Rev. 3.00 Jan 25, 2006 page 822 of 872 REJ09B0286-0300 Section 28 List of Registers High-Speed/ MediumSpeed Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Register Abbreviation KMIMR6 KMPCR6 KMIMRA WUEMR3 TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X DADR0 DADR1 DACR TCONRI TCONRO TCONRS SEDGR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Sub-Active Sub-Sleep Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module INT PORT INT TMR_Y, TMR_X TMR_Y, TMR_X D/A converter Timer connection Notes: 1. 2. 3. Initialized by a function software reset. The FLER bit is not initialized. Initialized when the SWE bit in FLMCR1 is cleared to 0. Rev. 3.00 Jan 25, 2006 page 823 of 872 REJ09B0286-0300 Section 28 List of Registers Rev. 3.00 Jan 25, 2006 page 824 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Section 29 Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 lists the absolute maximum ratings. Table 29.1 Absolute Maximum Ratings Item Power supply voltage* Power supply voltage (VCL pin) Input voltage (except ports 6 and 7) Input voltage (CIN input not selected in port 6) Input voltage (CIN input selected in port 6) Input voltage (port 7) Reference power supply voltage Analog power supply voltage/Bus driver power supply voltage Analog input voltage Operating temperature Operating temperature (when flash memory is programmed or erased) Storage temperature Symbol VCC VCL Vin Vin Vin Vin AVref AVCC/DrVCC VAN Topr Topr Tstg Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 Lower of -0.3 to VCC +0.3 or -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 -20 to +75 -20 to +75 -55 to +125 C Unit V Caution: Permanent damage to this LSI may result if absolute maximum ratings are exceeded. Take care the applied power supply does not exceed 4.3 V. Note: * Voltage applied to the VCC pin. Both the VCC pin and VCL pin should be connected to the VCC power supply. Rev. 3.00 Jan 25, 2006 page 825 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.2 DC Characteristics Table 29.2 lists the DC characteristics. Table 29.3 lists the permissible output currents. Table 29.4 lists the I2C bus drive characteristics. Table 29.5 lists the USB pin characteristics. Table 29.6 lists the multimedia card interface pin characteristics. Table 29.2 DC Characteristics (1) Conditions: VCC = 2.7 V to 3.6 V*1, AVCC*2 = 2.7 V to 3.6 V, AVref*2 = 2.7 V to AVCC, VSS = AVSS*2 = 0 V Item Schmitt trigger input voltage P67 to P60 (KWUL = 00)*3 *4, IRQ7 to IRQ0*3, IRQ15 to IRQ8, KIN9, KIN8, WUE15 to WUE8 P67 to P60 (KWUL = 01) (1) Symbol VT- VT+ VT- - VT+ Min VCC x 0.2 -- VCC x 0.05 Typ -- -- -- Max -- VCC x 0.7 -- Unit V Test Conditions Schmitt trigger input voltage (at level switch)*4 VT- VT+ VT+ - VT- VT- VT+ VT+ - VT- VT - VCC x 0.3 -- VCC x 0.05 VCC x 0.4 -- VCC x 0.03 VCC x 0.45 -- - VT - -- -- -- -- -- -- -- -- -- -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 P67 to P60 (KWUL = 10) P67 to P60 (KWUL = 11) VT+ VT+ (2) VIH 0.05 VCC x 0.9 Input high RES, STBY, NMI, voltage MD1, MD0, MD2, FWE EXTAL Port 7 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- VCC + 0.3 AVCC + 0.3 VCC + 0.3 Input pins other than (1) and (2) above, and input pins other than applicable pins when IIC, USB, and MCIF are used Rev. 3.00 Jan 25, 2006 page 826 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Test Conditions Item Input low voltage RES, STBY, MD1, MD0, MD2, FWE (3) Symbol VIL Min -0.3 -0.3 Typ -- -- Max VCC x 0.1 VCC x 0.2 Unit V NMI, EXTAL, input pins other than (1) and (3) above, and input pins other than applicable pins when IIC, USB, and MCIF are used Output high voltage All output pins (except for port 8 and applicable output pins when USB and MCIF are used*5)*6 Port 8*5 Output low voltage All output pins (except for RESO and applicable output pins when IIC, USB, and MCIF are used)*6 Ports 1 to 3 RESO VOL VOH VCC- 0.5 VCC- 1.0 -- -- -- -- IOH = -200 A IOH = -1 mA 0.5 -- -- -- -- 0.4 IOH = -200 A IOL = 1.6 mA -- -- -- -- 1.0 0.4 IOL = 5 mA IOL = 1.6 mA Rev. 3.00 Jan 25, 2006 page 827 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.2 DC Characteristics (2) Conditions: VCC = 2.7 V to 3.6 V*1, AVCC*2 = 2.7 V to 3.6 V, AVref*2 = 2.7 V to AVCC, VSS = AVSS*2 = 0 V Item Input leakage current RES STBY, NMI, MD1, MD0, MD2, FWE Port 7 Three-state leakage Ports 1 to 6, 8, 9, A current (off state) Input pull-up MOS current Ports 1 to 3 Ports 6 (P6PUE = 0), A Port 6 (P6PUE=1) Input capacitance RES NMI P80 to P83 Input pins other than above (4) Current consumption*7 Normal operation ICC (4) CIN ITSI -IP Symbol Iin Min -- -- -- -- 5 30 3 -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- 105 Max 10.0 1.0 1.0 1.0 150 300 100 80 50 20 15 135 mA VCC = 3.0 V to 3.6 V f = 25 MHz, All modules operating, high-speed mode VCC = 2.7 V to 3.6 V f = 20 MHz, All modules operating, high-speed mode VCC = 2.7 V to 3.6 V f = 12 MHz, All modules operating, high-speed mode VCC = 3.0 V to 3.6 V f = 25 MHz VCC = 2.7 V to 3.6 V f = 20 MHz VCC = 2.7 V to 3.6 V f = 12 MHz A Ta 50 C 50 C < Ta pF Vin = 0 V f = 1 MHz Ta = 25 C Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0 V Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V -- 80 115 -- 50 75 Sleep mode -- -- -- 75 60 35 0.1 -- 100 85 60 5.0 20.0 Standby mode*8 -- -- Rev. 3.00 Jan 25, 2006 page 828 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.2 DC Characteristics (3) Conditions: VCC = 2.7 V to 3.6 V*1, AVCC*2 = 2.7 V to 3.6 V, AVref*2 = 2.7 V to AVCC, VSS = AVSS*2 = 0 V Item Analog power supply current During A/D or D/A conversion Waiting for A/D or D/A conversion Reference power supply current During A/D conversion AIref During A/D or D/A conversion Waiting for A/D or D/A conversion Analog power supply voltage*1 AVCC Symbol AICC Min -- -- -- -- -- 2.7 2.0 RAM standby voltage Notes: VRAM 2.0 Typ 1.2 0.01 0.5 2.0 0.01 -- -- -- Max 2.0 5.0 1.0 5.0 5.0 3.6 3.6 -- A V AVref = 2.0 V to AVcc*2 Operating Idle/not used Unit mA A mA AVCC = 2.0 V to 3.6 V*2 Test Conditions 1. The flash memory must be programmed or erased within the conditions VCC = 3.0 V to 3.6 V. 2. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter or D/A converter is not used. Even if the A/D converter or D/A converter is not used, apply a value in the range from 2.0 V to 3.6 V to the AVCC and AVref pins by connection to the power supply (VCC). The relationship between these two pins should be AVref AVCC. 3. Includes peripheral module inputs multiplexed on the pin. 4. Maximum voltage applied to port 6 is VCC + 0.3 V when the CIN input is not selected, or the lower of VCC + 0.3 V or AVCC + 0.3 V when the CIN input is selected. If port 6 is in output mode, the output voltage is applied to port 6. 5. P80/ExIRQ8/SCL0, P81/ExIRQ9/SDA0, P82/ExIRQ10/SCL1, and P83/ExIRQ11/SDA1 are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0, SCL1, SDA0, and SDA1 (ICE in ICCR is 1). P80 to P83, P87, P84/SCK0, P85/SCK1, and P86/SCK2 (ICE in ICCR is 0) high levels are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output. 6. Indicates values when ICE in ICCR is 0. Low level output when the bus drive function is selected is rated separately. 7. Current consumption values are for VIH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 8. The values are for VRAM VCC < 2.7 V, VIH min = VCC - 0.2 V, and VIL max = 0.2 V. Rev. 3.00 Jan 25, 2006 page 829 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.3 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0 Ports 1 to 3 RESO Other output pins Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- Max 10 2 1 1 40 60 2 30 Unit mA Notes: 1. To protect LSI reliability, do not exceed the output current values in table 29.3. 2. When driving a Darlington transistor or LED, always insert a current-limiting resistor in the output line, as show in figures 29.1 and 29.2. Rev. 3.00 Jan 25, 2006 page 830 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.4 I2C Bus Drive Characteristics Conditions: VCC = 2.7 V to 3.6V, VSS = 0 V Applicable Pins: SCL1 and SCL0, SDA1 and SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT - + + - Min VCC x 0.3 -- VCC x 0.05 VCC x 0.7 - 0.5 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- Max -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.5 0.4 20 1.0 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage Input capacitance Three-state leakage current (off state) VIH VIL VOL Cin ITSI IOL = 8 mA IOL = 3 mA pF A Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V Rev. 3.00 Jan 25, 2006 page 831 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.5 USB Pin Characteristics Conditions: VCC = 3.3 V 0.3 V, DrVCC = 3.3 V 0.3 V, DrVSS = VSS = 0 V Applicable Pins: Driver/receiver input/output (USDP, USDM), USEXCL Item Differential input sensitivity Differential common mode range Input high voltage Input low voltage Output high voltage Output low voltage USEXCL Driver/ receiver USEXCL Driver/ receiver Driver/ receiver Driver/ receiver VOH VIL Symbol VDI VCM VIH Min 0.2 0.8 Typ -- -- Max -- 2.5 -- DrVCC + 0.3 VCC x 0.2 0.8 3.6 RL = 15 k is connected between the pin and GND RL = 1.5 k is connected between the pin and power supply pF A mA A Between the pin and GND 0.5 V < Vin < DrVCC -0.5 V Unit V Test Conditions (D +) - (D -) Including VDI VCC x 0.7 -- 2.0 -0.3 -0.3 2.8 -- -- -- -- VOL 0.0 -- 0.3 Output resistor I/O pin capacitance Three-state leakage current DrVCC current Normal consumption operation Standby mode ZDRV CIN ILO DIcc 28 -- -- -- -- -- -- -- 5 0.2 44 15 1.0 10 5.0 Rev. 3.00 Jan 25, 2006 page 832 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.6 Multimedia Card Interface Pin Characteristics Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Applicable Pins: MCCLK, MCCSA, MCCSB, MCCMD, MCDAT, MCTxD, MCRxD, MCCMDDIR, MCDATDIR, ExMCCLK, ExMCCSA, ExMCCSB, ExMCCMD, ExMCDAT, ExMCTxD, ExMCRxD, ExMCCMDDIR, ExMCDATDIR Item Input high voltage Input low voltage Output high voltage Output low voltage Symbol VIH VIL VOH VOL Min VCC x 0.625 -- VCC x 0.75 -- Typ -- -- -- -- Max -- VCC x 0.25 -- VCC x 0.125 Unit V This LSI 2 k Port Darlington transistor Figure 29.1 Darlington Transistor Drive Circuit (Example) This LSI 600 Ports 1 to 3 LED Figure 29.2 LED Drive Circuit (Example) Rev. 3.00 Jan 25, 2006 page 833 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.3 AC Characteristics Figure 29.3 shows the test conditions for the AC characteristics. 3V RL LSI output pin C RH C = 30pF : All ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level : 0.8 V * High level : 1.5 V Figure 29.3 Output Load Circuit Rev. 3.00 Jan 25, 2006 page 834 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.3.1 Clock Timing Table 29.7 shows the clock timing. The clock timing specified here covers clock output (), clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 26, Clock Pulse Generator. Table 29.7 Clock Timing Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Reset oscillation stabilization (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min 40 15 15 -- -- 10 8 Max 200 -- -- 5 5 -- -- Condition B Min 50 20 20 -- -- 10 8 Max 200 -- -- 5 5 -- -- ms Figure 29.5 Figure 29.6 Unit ns Reference Figure 29.4 tDEXT 500 -- 500 -- s Figure 29.5 The clock timing is shown below. tcyc tCH tCf tCL tCr Figure 29.4 System Clock Timing Rev. 3.00 Jan 25, 2006 page 835 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 29.5 Oscillation Stabilization Timing NMI IRQi ( i = 15 to 0) KINi ( i = 9 to 0) WUEi ( i = 15 to 8) tOSC2 Figure 29.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev. 3.00 Jan 25, 2006 page 836 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.3.2 Control Signal Timing Table 29.8 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN9, and WUE8 to WUE15 can be operated based on the subclock ( = 32.768 kHz). Table 29.8 Control Signal Timing Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Condition A Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time (IRQ15 to IRQ0, KIN9 to KIN0, WUE15 to WUE8) IRQ hold time (IRQ15 to IRQ0, KIN9 to KIN0, WUE15 to WUE8) IRQ pulse width (IRQ15 to IRQ0, KIN9 to KIN0, WUE15 to WUE8) (exiting software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW Min 200 20 150 10 200 Max -- -- -- -- -- Condition B Min 200 20 150 10 200 Max -- -- -- -- -- Unit ns tcyc ns Figure 29.8 Test Conditions Figure 29.7 tIRQS 150 -- 150 -- tIRQH 10 -- 10 -- tIRQW 200 -- 200 -- Rev. 3.00 Jan 25, 2006 page 837 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics tRESS RES tRESW tRESS Figure 29.7 Reset Input Timing tNMIS NMI tNMIW tNMIH IRQi (i = 15 to 0) tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input KINi (i = 9 to 0) WUEi (i = 15 to 8) tIRQW tIRQS tIRQH KIN, WUE edge input Figure 29.8 Interrupt Input Timing Rev. 3.00 Jan 25, 2006 page 838 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.3.3 Bus Timing Table 29.9 shows the bus timing. In subclock ( = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 29.9 Bus Timing (1) (Normal Mode and Advanced Mode) Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Condition A Item Address delay time Address setup time Address hold time CS delay time (IOS, CS256, CPCS1, CPCS2) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol tAD tAS tAH tCSD Min Max 20 Min Condition B Max 25 Unit ns Test Conditions Figures 29.9 to 29.14 -- -- 0.5 x tcyc -15 -- 0.5 x tcyc - 10 -- 0.5 x tcyc - 15 -- 0.5 x tcyc - 10 -- -- 15 -- 15 tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH -- -- -- 15 0 15 15 15 -- -- -- 15 0 15 15 15 -- -- 1.0 x tcyc - 30 1.5 x tcyc - 25 2.0 x tcyc - 30 2.5 x tcyc - 25 3.0 x tcyc - 30 15 15 -- -- 1.0 x tcyc - 35 1.5 x tcyc - 30 2.0 x tcyc - 35 2.5 x tcyc - 30 3.0 x tcyc - 35 15 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 x tcyc - 20 -- 1.5 x tcyc - 20 -- 1.0 x tcyc - 20 -- 1.5 x tcyc - 20 -- -- 0 10 25 5 30 -- 0 10 25 5 35 -- -- -- -- -- -- -- -- Rev. 3.00 Jan 25, 2006 page 839 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 tAD A17 to A0, IOS*, CS256, CPCS1 tCSD tAS tASD AS* tASD tAH tRSD1 RD (Read) tAS tACC2 tRSD2 tACC3 D15 to D0 (Read) tRDS tRDH tWRD2 HWR, LWR (Write) tAS tWDD D15 to D0 (Write) tWSW1 tWRD2 tAH tWDH tWSW1 Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.9 Basic Bus Timing/2-State Access Rev. 3.00 Jan 25, 2006 page 840 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 T3 tAD A17 to A0, IOS*, CS256, CPCS1 tCSD tAS tASD AS* tASD tAH tRSD1 RD (Read) tAS D15 to D0 (Read) tACC4 tRSD2 tACC5 tRDS tRDH tWRD1 HWR, LWR (Write) tWDD D15 to D0 (Write) tWDS tWSW2 tWRD2 tAH tWDH Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.10 Basic Bus Timing/3-State Access Rev. 3.00 Jan 25, 2006 page 841 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 Tw T3 A17 to A0, IOS*, CS256, CPCS1 AS* RD (Read) D15 to D0 (Read) HWR, LWR (Write) D15 to D0 (Write) tWTS WAIT tWTH tWTS tWTH Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.11 Basic Bus Timing/3-State Access with One Wait State Rev. 3.00 Jan 25, 2006 page 842 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 tAD CPA10 to CPA0 (A10 to A0) tAS CPCS1, CPCS2 (P92, P91) tCSD CPOE (P93) Read CPD15 to CPD0 (P37 to P30) tWRD1 CPWE (P94) Write CPD15 to CPD0 (P37 to P30) tWDD tAS tRSD1 T2 T3 tACC4 tRSD2 tRDS tACC5 tAH tRDH tWRD2 tAH tWSW2 tWDH Figure 29.12 CF Interface Basic Timing/3-State Access Rev. 3.00 Jan 25, 2006 page 843 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A17 to A0, IOS*, CS256, CPCS1 tAS tASD AS* tASD tAH tRSD2 RD (Read) tACC3 D15 to D0 (Read) tRDS tRDH Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.13 Burst ROM Access Timing/2-State Access Rev. 3.00 Jan 25, 2006 page 844 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 or T3 T1 tAD A17 to A0, IOS*, CS256, CPCS1 AS* tRSD2 RD (Read) tACC1 D15 to D0 (Read) tRDS tRDH Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 29.14 Burst ROM Access Timing/1-State Access 29.3.4 Timing of On-Chip Peripheral Modules Tables 29.10 to 29.14 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock ( = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ15 to IRQ0, KIN9 to KIN0, and WUE15 to WUE8), watchdog timer, and 8-bit timer (channels 0 and 1) only. Rev. 3.00 Jan 25, 2006 page 845 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.10 Timing of On-Chip Peripheral Modules (1) Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz*, 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 32.768 kHz*, 5 MHz to 20 MHz Condition A Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse Single edge width Both edges TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse Single edge width Both edges PWM, PWMX SCI Pulse output delay time Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter WDT RESO output delay time RESO output pulse width tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS tRESD tRESOW Symbol tPWD tPRS tPRH tFTOD tFTIS tFTCS tFTCWH tFTCWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tPWOD tScyc Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- 4 6 0.4 -- -- -- 30 30 30 -- 132 Max 40 -- -- 40 -- -- -- -- 40 -- -- -- -- 40 -- -- 0.6 1.5 1.5 40 -- -- -- 200 -- Condition B Min -- 40 40 -- 40 40 1.5 2.5 -- 40 40 1.5 2.5 -- 4 6 0.4 -- -- -- 40 40 40 -- 132 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- 200 -- ns ns tcyc Figure 29.24 Figure 29.25 ns Figure 29.23 tScyc tcyc ns tcyc Figure 29.21 Figure 29.22 tcyc ns Figure 29.18 Figure 29.20 Figure 29.19 tcyc Figure 29.17 ns Figure 29.16 Test Unit Conditions ns Figure 29.15 Note: * Only the on-chip peripheral modules that can be used in subclock operation. Rev. 3.00 Jan 25, 2006 page 846 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics T1 T2 tPRS Ports 1 to 9 and A (read) tPWD Ports 1 to 6, 8, 9, and A (write) tPRH Figure 29.15 I/O Port Input/Output Timing tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 29.16 FRT Input/Output Timing tFTCS FTCI tFTCWL tFTCWH Figure 29.17 FRT Clock Input Timing Rev. 3.00 Jan 25, 2006 page 847 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics tTMOD TMO0, TMO1 TMOX, TMOY Figure 29.18 8-Bit Timer Output Timing tTMCS TMI0, TMI1 TMIX, TMIY tTMCWL tTMCWH tTMCS Figure 29.19 8-Bit Timer Clock Input Timing tTMRS TMI0, TMI1 TMIX, TMIY Figure 29.20 8-Bit Timer Reset Input Timing tPWOD PW15 to PW0, PWX1, PWX0 Figure 29.21 PWM, PWMX Output Timing Rev. 3.00 Jan 25, 2006 page 848 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics tSCKW tSCKr tSCKf SCK2 to SCK0 tScyc Figure 29.22 SCK Clock Input Timing SCK2 to SCK0 tTXD TxD2 to TxD0 (transmit data) tRXS RxD2 to RxD0 (receive data) tRXH Figure 29.23 SCI Input/Output Timing (Clock Synchronous Mode) tTRGS ADTRG Figure 29.24 A/D Converter External Trigger Input Timing tRESD RESO tRESOW tRESD Figure 29.25 WDT Output Timing (RESO RESO) RESO Rev. 3.00 Jan 25, 2006 page 849 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.11 I2C Bus Timing Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA output fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: * Symbol tSCL tSCLH tSCLL tSr tSf tOf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min 12 3 5 -- -- 20 + 0.1 Cb -- 5 3 3 3 0.5 0 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 7.5* 300 250 1 -- -- -- -- -- -- 400 ns pF tcyc ns Unit tcyc Test Conditions Figure 29.26 17.5 tcyc can be set according to the clock selected for use by the IIC module. Rev. 3.00 Jan 25, 2006 page 850 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics VIH SDA0 and SDA1 tBUF tSTAH VIL tSCLH tSTAS tSP tSTOS SCL0 and SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 29.26 I2C Bus Interface Input/Output Timing Table 29.12 USB Timing Conditions: VCC = 3.3 V 0.3 V, DrVCC = 3.3 V 0.3 V, DrVSS = VSS = 0 V Pin Functions: Driver/receiver input/output (USDP, USDM), USEXCL Item Driver/receiver Rise time (full speed) Fall time Symbol tr tf Min 4 4 Max 20 20 Unit ns Test Conditions Remarks Figure 29.27 Low: 0.1 x DrVCC High: 0.9 x DrVCC % tr/tf Differential signal time difference Driver/receiver output signal crossover voltage USB clock oscillation stabilization time (crystal) tRFM 90.0 111.11 VCRS tOSCU 1.3 10 2.0 -- V ms Rev. 3.00 Jan 25, 2006 page 851 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics tr USDP, USDM tf Figure 29.27 USB Driver/Receiver Output Timing Table 29.13 Multimedia Card Interface Conditions: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz * MCIF: ExMCCLK/MCCLK timing CL 100 pF* Item MCCLK cycle time MCCLK high pulse width MCCLK low pulse width MCCLK rise time MCCLK fall time Note: * Symbol tPP tWH tWL tTLH tTHL Min 0 10 10 -- -- Max 20 -- -- 10 10 0 50 50 -- -- CL 250 pF* Min Max 5 -- -- 50 50 Unit MHz ns Test Conditions Figure 29.28 Total load capacitance of external signal lines connected to the ExMCCLK/MCCLK pin * MCIF: Card bus timing Item Output data delay time (based on MCCLK rising edge) Output data delay time (based on MCCLK falling edge) Input data hold time Input data setup time Symbol tHOD tLOD tLIH tLIS Min 5 -- 10 5 Max 15 10 -- -- Unit ns Test Conditions Figure 29.28 Rev. 3.00 Jan 25, 2006 page 852 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics tPP tWH tWL ExMCCLK/MCCLK tTLH tHOD ExMCCSA/MCCSA ExMCCSB/MCCSB tTHL tLOD ExMCCMD/MCCMD ExMCDAT/MCDAT ExMCTxD/MCTxD ExMCCMDDIR/MCCMDDIR ExMCDATDIR/MCDATDIR ExMCCLK/MCCLK tLIH ExMCCMD/MCCMD ExMCDAT/MCDAT ExMCRxD/MCRxD tLIS Figure 29.28 Multimedia Card Interface Timing Rev. 3.00 Jan 25, 2006 page 853 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.14 H-UDI Timing Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, VSS = 0 V, = 5 MHz to 20 MHz Item ETCK clock cycle time ETCK clock high pulse width ETCK clock low pulse width ETCK clock rise time ETCK clock fall time ETRST pulse width Reset hold transition pulse width ETMS setup time ETMS hold time ETDI setup time ETDI hold time ETDO data delay time Note: * tcyc tTCKcyc Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tRSTHW tTMSS tTMSH tTDIS tTDIH tTDOD Min 40* 15 15 -- -- 20 10 20 20 20 20 -- Max 500* -- -- 5 5 -- -- -- -- -- -- 20 ns Figure 29.31 tcyc Figure 29.30 Unit ns Test Conditions Figure 29.29 tTCKcyc tTCKH tTCKf ETCK tTCKL tTCKr Figure 29.29 H-UDI ETCK Timing Rev. 3.00 Jan 25, 2006 page 854 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics ETCK RES tRSTHW ETRST tTRSTW Figure 29.30 Reset Hold Timing ETCK tTMSS tTMSH ETMS tTDIS tTDIH ETDI tTDOD ETDO (Six instructions defined in IEEE1149.1) ETDO (Other instructions) tTDOD Figure 29.31 H-UDI Input/Output Timing Rev. 3.00 Jan 25, 2006 page 855 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.4 A/D Conversion Characteristics Tables 29.15 and 29.16 list the A/D conversion characteristics. Table 29.15 A/D Conversion Characteristics (AN7 to AN2 Input: 134/266-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 20 MHz Condition A Item Resolution Conversion time* Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 5.36 20 5 7.0 7.5 7.5 0.5 8.0 Min 10 -- -- -- -- -- -- -- -- Condition B Typ 10 -- -- -- -- -- -- -- -- Max 10 6.7 20 5 7.0 7.5 7.5 0.5 8.0 Unit Bits s pF k LSB Value when using the maximum operating frequency in single mode of 134 states. Rev. 3.00 Jan 25, 2006 page 856 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics Table 29.16 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 20 MHz Condition A Item Resolution Conversion time* Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * -- -- -- -- -- -- -- -- -- -- 11.0 11.5 11.5 0.5 12.0 -- -- -- -- -- -- -- -- -- -- 11.0 11.5 11.5 0.5 12.0 LSB Min 10 -- -- -- Typ 10 -- -- -- Max 10 5.36 20 5 Min 10 -- -- -- Condition B Typ 10 -- -- -- Max 10 6.7 20 5 Unit Bits s pF k Value when using the maximum operating frequency in single mode of 134 states. Rev. 3.00 Jan 25, 2006 page 857 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.5 D/A Conversion Characteristics Table 29.17 lists the D/A conversion characteristics. Table 29.17 D/A Conversion Characteristics Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 25 MHz Condition B: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, = 5 MHz to 20 MHz Item Resolution Conversion time Absolute accuracy Load capacitance 20 pF Load resistance 2 M Load resistance 4 M Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bits s LSB Rev. 3.00 Jan 25, 2006 page 858 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 29.6 Flash Memory Characteristics Table 29.18 lists the flash memory characteristics. Table 29.18 Flash Memory Characteristics Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V Item Programming time*1 *2 *4 Erase time*1 *3 *6 Reprogramming count Data retention time*10 Programming Wait time after SWE-bit setting*1 Wait time after PSU-bit setting*1 Wait time after P-bit setting*1 *4 Symbol tP tE NWEC tDRP x y z1 z2 z3 Wait time after P-bit clear*1 Wait time after PSU-bit clear*1 Wait time after PV-bit setting*1 Wait time after dummy write*1 Wait time after PV-bit clear*1 Wait time after SWE-bit clear*1 Maximum programming count*1 *4 *5 Erase Wait time after SWE-bit setting*1 Wait time after ESU-bit setting*1 Wait time after E-bit setting*1 *6 Wait time after E-bit clear*1 Wait time after ESU-bit clear*1 Wait time after EV-bit setting*1 Wait time after dummy write*1 Wait time after EV-bit clear*1 Wait time after SWE-bit clear*1 Maximum erase count*1 *6 *7 N x y z N Min -- -- 100*8 10 1 50 28 198 8 5 5 4 2 2 100 -- 1 100 10 10 10 20 2 4 100 -- Typ 10 10 Max 200 1200 Unit ms/ 128 bytes ms/ block Times Years s 1n6 7 n 1000 Additional programming Test Conditions 10,000*9 -- -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 32 202 12 -- -- -- -- -- -- 1000 -- -- 100 -- -- -- -- -- -- 120 Time s ms s Times Notes: 1. Make each time setting in accordance with the program/erase algorithm. Rev. 3.00 Jan 25, 2006 page 859 of 872 REJ09B0286-0300 Section 29 Electrical Characteristics 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the program verification time.) 3 Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP max) tP max = (wait time after P-bit setting (z1) + (z3)) x 6 + wait time after P-bit setting (z2) x ((N) - 6) 5. Set the maximum programming count (N) to a value less than the maximum programming time (tP max), with referencing the actual z1, z2, and z3 settings. The wait time after P-bit setting (z1, z2, and z3) should be changed depending on the programming count (n). Programming count(n) 1 n 6 z1 = 30 s, z3 = 10 s 7 n 1000 z2 = 200 s 6. Maximum erase time (tE max) tE max = wait time after E-bit setting (z) x maximum erase count (N) 7. Set the maximum erase count (N) to a value less than the maximum erase time (tE max), with referencing the actual (z) setting. 8. Minimum number of times for which all characteristics are guaranteed after rewriting. (Guarantee range is 1 to minimum value.) 9. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 10.Data retention characteristic when rewriting is performed within the specification range, including the minimum value. Rev. 3.00 Jan 25, 2006 page 860 of 872 REJ09B0286-0300 Appendix Appendix A. Port Name Pin Name Port 1 A7 to A0, CPA7 to CPA0 I/O Port States in Each Pin State MCU Operating Mode 2, 3 (EXPE = 1) Hardware Software Standby Standby Reset Mode Mode T T kept* Watch Mode kept* Sleep Mode kept* Subsleep Subactive Mode Mode kept* Address output/ CompactFlash Program Execution State Address output/ CompactFlash address output/ input port 2, 3 (EXPE = 0) I/O port T T kept* kept* kept* kept* Address output/ I/O port I/O port T T kept* kept* kept* kept* Address output/ CPREG/ I/O port I/O port T T kept* kept* kept* kept* Address output/ CompactFlash address output/ input port I/O port Address output/ I/O port I/O port Address output/ CPREG/ I/O port I/O port Address output/ CompactFlash Port 27 to 24 A15 to A12 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 23 2, 3 (EXPE = 1) A11, CPREG 2, 3 (EXPE = 0) Port 22 to 20 A10 to A8, CPA10 to CPA8 2, 3 (EXPE = 1) address output/ I/O port 2, 3 (EXPE = 0) I/O port T T T T T T D15 to D8/ CPD15 to CPD8 I/O port I/O port address output/ I/O port I/O port D15 to D8/ CPD15 to CPD8 I/O port I/O port Port 3 D15 to D8, CPD15 to CPD8 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 4 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 5 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 6 D7 to D0, CPD7 to CPU0 2, 3 (EXPE = 1) T T T T T T kept kept kept kept kept kept kept kept kept kept kept kept I/O port I/O port kept kept kept kept D7 to D0/ CPD7 to CPD0/ I/O port I/O port D7 to D0/ CPD7 to CPD0/ I/O port I/O port 2, 3 (EXPE = 0) Rev. 3.00 Jan 25, 2006 page 861 of 872 REJ09B0286-0300 Appendix MCU Operating Mode 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 8 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 97 WAIT, CPWAIT, CS256 2, 3 (EXPE = 1) T T T/kept T/kept T/kept T/kept WAIT/ CPWAIT/ CS256/ I/O port I/O port EXCL input WAIT/ CPWAIT/ CS256/ I/O port I/O port Clock output/ EXCL input/ Input port T T kept kept kept kept I/O port I/O port Hardware Software Standby Standby Reset Mode Mode T T T Program Execution State Input port Port Name Pin Name Port 7 Watch Mode T Sleep Mode T Subsleep Subactive Mode Mode T Input port 2, 3 (EXPE = 0) Port 96 2, 3 (EXPE = 1) T T kept [DDR = 1] H [DDR = 0] T kept EXCL input kept [DDR = 1] Clock output [DDR = 0] T kept EXCL input , EXCL 2, 3 (EXPE = 0) Port 95 to 93 2, 3 (EXPE = 1) AS, IOS, HWR, CPWE, RD, CPOE 2, 3 (EXPE = 0) Port 92, 91 CPCS1, CPCS2 2, 3 (EXPE = 1) T T H H H H AS/IOS, AS/IOS, HWR/CPWE, HWR/CPWE, RD/CPOE RD/CPOE I/O port CPCS1, CPCS2/ I/O port I/O port I/O port CPCS1, CPCS2/ I/O port I/O port LWR/ I/O port I/O port A17, A16/ I/O port I/O port kept T T kept kept kept kept kept kept kept 2, 3 (EXPE = 0) Port 90 LWR 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port A A17, A16 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) T T T T H/kept kept kept* H/kept kept kept* H/kept kept kept* H/kept kept kept* LWR/ I/O port I/O port A17, A16/ I/O port I/O port Legend: H: High level L: Low level T: High impedance kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up MOS remains on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR. DDR: Data direction register Note: * In the case of address output, the last address accessed is retained. Rev. 3.00 Jan 25, 2006 page 862 of 872 REJ09B0286-0300 Appendix B. Product Lineup Type Code F-ZTAT version HD64F2158 Mark Code F2158VBQ25 Package (Code) 112-pin TFBGA (TBP-112A) Product Type H8S/2158 Rev. 3.00 Jan 25, 2006 page 863 of 872 REJ09B0286-0300 Appendix C. Package Dimensions For package dimensions, dimensions described in Renesas Package Data Book have priority. JEITA Package Code T-TFBGA112-10x10-0.80 RENESAS Code TTBG0112GA-A Previous Code TBP-112A/TBP-112AV MASS[Typ.] 0.2g D wSA wSB x4 v y1 S S A y S e ZD A L K J H e A1 E Reference Symbol Dimension in Millimeters B G F E D C B A Min Nom 10.00 10.00 Max D E v w A ZE 0.20 0.30 1.20 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45 A1 e b x y y1 SD SE ZD ZE 1 2 3 4 5 6 7 8 9 10 11 b xM S A B 1.00 1.00 Figure C.1 Package Dimensions (TBP-112A) Rev. 3.00 Jan 25, 2006 page 864 of 872 REJ09B0286-0300 Index Index 14-Bit PWM Timer (PWMX)................. 273 16-Bit Access Space ............................... 123 16-Bit Count Mode ................................. 335 16-Bit Free-Running Timer (FRT) ......... 287 16-Bit, 2-State Access Space .................. 127 16-Bit, 3-State Access Space .................. 130 256-kbyte Expansion Area...................... 119 8-Bit Access Space ................................. 123 8-Bit PWM Timer (PWM)...................... 261 8-Bit Timer (TMR) ................................. 315 8-Bit, 2-State Access Space .................... 125 8-Bit, 3-State Access Space .................... 126 A/D Conversion Time............................. 706 A/D Converter ........................................ 697 Absolute Address...................................... 46 Acknowledge signal................................ 517 Activation by Interrupt............................ 164 Activation by Software ........................... 164 additional pulse ....................................... 271 Address Map ............................................. 62 Address Ranges and External Address Spaces ..................................................... 115 Address Space........................................... 24 Addressing Modes .................................... 44 Advanced Mode................................ 22, 121 Arithmetic Operations Instructions........... 36 Asynchronous Mode ............................... 417 base cycle................................................ 281 Basic Bus Interface ................................. 123 Basic Expansion Area............................. 118 Basic Operation Timing.......... 125, 135, 138 basic pulse............................................... 270 Bit Manipulation Instructions ................... 39 bit rate ..................................................... 405 blanking waveform ................................. 372 Block Data Transfer Instructions .............. 43 Block Transfer Mode ..............................159 Boot Mode ..............................................728 Boundary overflow..................................202 Boundary Scan ........................................756 Branch Instructions ...................................41 Broadcast Commands..............................656 bulk transfer ............................................603 Burst ROM Interface...............................134 Bus Arbitration........................................142 Bus Control .............................................113 Bus Controller .........................................103 Bus Master ..............................................142 Bus Specifications of Basic Bus Interface ................................................................117 Carrier frequency ....................................264 Cascaded Connection ..............................335 CBLANK Output ....................................372 CF Expansion Area (Memory Card Mode) ................................................................121 Chain Transfer.........................................160 Clamp Waveform....................................359 Clock Pulse Generator.............................761 Clocked Synchronous Mode ...................437 Commands ..............................................634 Commands Not Requiring Command Response .................................................657 Commands with Read Data.............663, 679 Commands with Write Data............669, 683 Commands without Data Transfer ..659, 675 Compare-Match Count Mode .................335 Condition field ..........................................43 Condition-Code Register (CCR) ...............28 Consecutive Data Blocks ........................192 control transfer ........................................602 conversion cycle......................................281 CP Expansion Area (Basic Mode) ..........120 CPU...........................................................17 Rev. 3.00 Jan 25, 2006 page 865 of 872 REJ09B0286-0300 Index CPU Operating Modes.............................. 20 CRC Operation Circuit ........................... 467 Crystal Oscillator .................................... 762 D/A Converter ........................................ 691 data direction register ............................. 205 data register............................................. 205 Data Size and Data Alignment........ 123, 137 Data Transfer Controller (DTC) ............. 145 Data Transfer Instructions ........................ 35 Direct Transitions ................................... 788 Divided Waveform Period Measurement 361 DTC Comparator Scan ........................... 704 DTC Vector Table .................................. 153 Effective Address...................................... 48 Effective address extension ...................... 43 Encryption Operation Circuit (DES and GF) ................................................................ 689 Endpoint.......................................... 557, 622 Erase/Erase-Verify.................................. 735 erasing units............................................ 722 Error Protection ...................................... 737 Exception Handling .................................. 65 Exception Handling Vector Table ............ 66 Extended Control Register........................ 27 External Clock ........................................ 763 External Trigger...................................... 708 FIFO empty............................................. 202 FIFO full ................................................. 202 FIFO overread......................................... 202 FIFO overwrite ....................................... 202 flash memory .......................................... 717 framing error........................................... 427 General Registers...................................... 26 Hardware Protection ............................... 737 Hardware Standby Mode ........................ 784 Rev. 3.00 Jan 25, 2006 page 866 of 872 REJ09B0286-0300 HSYNCO Output .................................... 370 I/O Ports.................................................. 205 I/O Select Signals.................................... 122 I2C Bus Formats ...................................... 516 I2C bus interface...................................... 539 I2C Bus Interface (IIC) ............................ 473 ID code.................................................... 731 ID Numbers............................................. 183 Idle Cycle ................................................ 141 IIC Operation Reservation Adapter ........ 510 Immediate ................................................. 46 IN Token ................................................. 614 Input Capture .......................................... 302 Input Capture Operation.......................... 336 input pull-up MOS control register ......... 205 Instruction Set ........................................... 33 Internal Block Diagram............................... 2 Internal Synchronization Signal.............. 367 Interrupt ADI ..................................................... 708 CMIA .......................................... 338, 339 CMIB .......................................... 338, 339 ERI ...................................................... 460 ICI ....................................................... 339 ICIA .................................................... 308 ICIB .................................................... 308 ICIC .................................................... 308 ICID .................................................... 308 ICRA................................................... 820 IICC .................................................... 540 IICM.................................................... 540 IICR .................................................... 540 IICT..................................................... 540 MMCIA............................................... 687 MMCIB............................................... 687 MMCIC............................................... 687 OVI ..................................................... 339 RXI.............................................. 459, 460 SWDTEND ......................................... 161 Index TEI .............................................. 459, 460 TXI.......................................459, 460. See USBI0 ................................................. 625 USBI1 ................................................. 625 USBI2 ................................................. 625 USBI3 ................................................. 625 WOVI ................................................. 382 WUE15 to WUE8 Interrupts................. 85 Interrupt Control Modes ........................... 90 Interrupt Controller ................................... 73 Interrupt Exception Handling ................... 69 Interrupt Exception Handling Sequence ... 96 Interrupt Exception Handling Vector Table .................................................................. 86 Interrupt Mask Bit..................................... 28 interrupt transfer ..................................... 603 Interval Timer Mode............................... 381 IrDA........................................................ 456 IRQ15 to IRQ0 Interrupts ......................... 84 KIN9 to KIN0 Interrupts........................... 85 Logic Operations Instructions................... 38 LSI Internal States in Each Operating Mode ................................................................ 780 Master Receive Operation....................... 519 Master Transmit Operation ..................... 517 Medium-Speed Mode ............................. 781 Memory Card Interface........................... 137 Memory Indirect ....................................... 47 MMC Mode ............................................ 656 Mode Transition Diagram............... 718, 779 Module Stop Mode ................................. 787 Multimedia Card Interface (MCIF)......... 627 Multiprocessor Communication Function ................................................................ 431 NMI Interrupt............................................ 84 Normal Mode............................ 20, 122, 157 Number of DTC Execution States...........163 Number of FIFO Bytes............................174 On-Board Programming..........................727 Operating Modes.......................................55 Operation field ..........................................43 Operation Reservation Commands..........513 OUT Token .............................................610 Output Compare......................................301 overrun error ...........................................427 parity error ..............................................427 Pin Arrangement .........................................3 Pin Arrangement in Each Operating Mode .4 Pin Functions...............................................8 PLL Circuit .............................................767 pointer sets ..............................................167 Power-Down Modes................................771 Processing States.......................................50 Program Counter .......................................27 Program/Erase Protection........................737 Program/Program-Verify ........................733 Program-Counter Relative ........................47 Programmer Mode ..................................738 programming units ..................................722 PWM conversion period .........................264 PWM Decoding.......................................358 RAM .......................................................715 RAM-FIFO Unit .....................................167 Register Configuration ..............................25 Register Direct ..........................................45 Register field .............................................43 Register Indirect........................................45 Register Indirect with Displacement .........45 Register Indirect with Post-Increment.......45 Register Indirect with Pre-Decrement.......46 Registers ABRKCR ...................... 77, 797, 808, 818 ADCR ......................... 702, 802, 813, 822 Rev. 3.00 Jan 25, 2006 page 867 of 872 REJ09B0286-0300 Index ADCSR....................... 701, 802, 813, 822 ADDR......................... 700, 801, 813, 822 BAR .................................................... 170 BARA ........................... 78, 797, 808, 818 BARB ........................... 78, 797, 808, 818 BARC ........................... 78, 797, 808, 818 BCR ............................ 106, 800, 812, 821 BCR2 .......................... 108, 797, 809, 819 BRR ............................ 405, 801, 812, 822 CLKON ...................... 654, 792, 804, 815 CMDR0 ...................... 637, 792, 804, 815 CMDR1 ...................... 637, 792, 804, 815 CMDR2 ...................... 637, 792, 804, 815 CMDR3 ...................... 637, 792, 804, 815 CMDR4 ...................... 637, 792, 804, 815 CMDR5 ...................... 637, 792, 804, 815 CMDSTRT ......................................... 640 CMDTYR ................... 632, 792, 804, 815 CONFV....................... 597, 793, 805, 816 CRA .................................................... 149 CRB .................................................... 149 CRCCR....................... 468, 796, 808, 818 CRCDIR ..................... 468, 796, 808, 818 CRCDOR.................... 468, 796, 808, 818 CSTR .......................... 645, 792, 804, 815 CTOCR....................... 643, 792, 804, 815 DACNTH.................... 275, 799, 810, 820 DACNTL .................... 275, 799, 810, 820 DACR .........277, 692, 799, 803, 810, 814, .................................................... 820, 823 DADR......................... 692, 803, 814, 823 DADRA ...................... 276, 799, 810, 820 DADRB ...................... 277, 799, 810, 820 DAR.................................................... 149 DATAN .............................................. 172 DEVRSMR ................. 589, 794, 806, 817 DTCERA .................... 150, 797, 808, 818 DTCERB .................... 150, 797, 808, 818 DTCERC .................... 150, 797, 808, 818 DTCERD .................... 150, 797, 808, 818 Rev. 3.00 Jan 25, 2006 page 868 of 872 REJ09B0286-0300 DTCERE ..................... 150, 797, 808, 818 DTCRA ....................... 173, 795, 807, 817 DTCRB ....................... 175, 795, 807, 817 DTCRC ............................................... 180 DTCRD ....................... 181, 795, 807, 817 DTIDR ........................ 178, 795, 807, 817 DTIDSRA ................... 178, 795, 807, 817 DTIDSRB ................... 179, 795, 807, 817 DTIER......................... 181, 795, 807, 817 DTOUTR .................... 644, 793, 805, 816 DTRSR........................ 181, 795, 807, 817 DTSTRA ..................... 179, 795, 807, 817 DTSTRB ..................... 180, 795, 807, 817 DTSTRC ..................... 176, 795, 807, 817 DTVECR..................... 151, 797, 808, 818 EBR1........................... 726, 797, 809, 819 EBR2........................... 726, 797, 809, 819 EP4PKTSZR ............... 598, 793, 805, 816 EPDIR0 ....................... 563, 794, 806, 817 EPDR0I ....................... 560, 794, 806, 816 EPDR0O ..................... 559, 794, 806, 816 EPDR0S ...................... 559, 793, 805, 816 EPDR1 ........................ 560, 794, 806, 816 EPDR2 ........................ 560, 793, 805, 816 EPDR3 ........................ 560, 793, 805, 816 EPRSTR0.................... 587, 794, 806, 817 EPSTLR0 .................... 584, 794, 806, 817 EPSZR1....................... 558, 794, 806, 816 FLMCR1 ..................... 723, 797, 809, 819 FLMCR2 ..................... 725, 797, 809, 819 FRC............................. 290, 798, 809, 819 FREEN................................................ 172 FSTR........................... 169, 794, 806, 817 FVSR0IH .................... 562, 794, 806, 816 FVSR0IL..................... 562, 794, 806, 816 FVSR0OH................... 562, 794, 806, 816 FVSR0OL ................... 562, 794, 806, 816 FVSR0SH ................... 562, 793, 805, 816 FVSR0SL.................... 562, 793, 805, 816 FVSR1H...................... 562, 794, 806, 816 Index FVSR1L...................... 562, 794, 806, 816 FVSR2H ..................... 562, 793, 805, 816 FVSR2L...................... 562, 793, 805, 816 FVSR3H ..................... 562, 793, 805, 816 FVSR3L...................... 562, 793, 805, 816 ICCMD ....................... 510, 795, 807, 817 ICCNT ........................ 508, 795, 807, 817 ICCR ........................... 485, 801, 812, 822 ICCRX ........................ 496, 795, 807, 817 ICDR................................... 477, 801, 822 ICDRS......... 508, 795, 796, 807, 812, 817 ICDRX........................ 507, 795, 807, 817 ICMR .......................... 482, 801, 812, 822 ICR...................................... 290, 798, 810 ICRA............................. 76, 796, 808, 818 ICRB ............................. 76, 796, 808, 818 ICRC ............................. 76, 796, 808, 818 ICRD............................. 76, 796, 808, 818 ICSR ........................... 492, 801, 812, 822 ICSRA......................... 497, 795, 807, 817 ICSRB......................... 499, 795, 807, 817 ICSRC......................... 502, 795, 807, 817 IER................................ 81, 800, 811, 821 IER16............................ 81, 797, 808, 818 INTCR0 ...................... 647, 792, 804, 815 INTCR1 ...................... 648, 792, 804, 815 INTSELR0 .................. 590, 794, 806, 817 INTSTR0 .................... 649, 792, 804, 815 INTSTR1 .................... 652, 792, 804, 815 IOMCR ....................... 653, 792, 804, 815 ISCR16H....................... 79, 797, 808, 819 ISCR16L ....................... 79, 797, 808, 819 ISCRH........................... 80, 796, 808, 818 ISCRL ........................... 80, 796, 808, 818 ISR ................................ 82, 796, 808, 818 ISR16 ............................ 82, 797, 808, 819 ISSR............................ 259, 797, 808, 819 ISSR16........................ 258, 797, 808, 819 KBCOMP ........................... 703, 796, 808 KMIMR6 ...................... 83, 802, 813, 823 KMIMRA...................... 83, 802, 813, 823 KMPCR6..................... 234, 802, 813, 823 LPWRCR .................... 774, 797, 809, 819 MDCR........................... 56, 800, 811, 821 MODER ...................... 631, 792, 804, 815 MRA ...................................................147 MRB....................................................148 MSTPCRH .................. 777, 797, 809, 819 MSTPCRL .................. 777, 797, 809, 819 NRA ....................................................172 NWA ...................................................173 OCRA.......................... 290, 798, 809, 820 OCRAF ....................... 291, 798, 810, 820 OCRAR....................... 291, 798, 810, 820 OCRB.......................... 290, 798, 809, 820 OCRDM ...................... 291, 799, 810, 820 OPCR .......................... 641, 792, 804, 815 P1DDR........................ 209, 800, 811, 821 P1DR........................... 210, 800, 811, 821 P1PCR......................... 210, 799, 811, 821 P2DDR........................ 212, 800, 811, 821 P2DR........................... 213, 800, 811, 821 P2PCR......................... 213, 799, 811, 821 P3DDR........................ 216, 800, 811, 821 P3DR........................... 216, 800, 811, 821 P3PCR......................... 217, 800, 811, 821 P4DDR........................ 223, 800, 811, 821 P4DR........................... 223, 800, 811, 821 P5DDR........................ 228, 800, 811, 821 P5DR........................... 229, 800, 811, 821 P6DDR........................ 233, 800, 811, 821 P6DR........................... 233, 800, 811, 821 P7PIN.......................... 244, 800, 811, 821 P8DDR........................ 245, 800, 811, 821 P8DR........................... 246, 800, 811, 821 P9DDR........................ 250, 800, 811, 821 P9DR........................... 251, 800, 811, 821 PADDR ....................... 254, 799, 811, 821 PAODR ....................... 254, 799, 811, 821 PAPIN ......................... 255, 799, 811, 821 Rev. 3.00 Jan 25, 2006 page 869 of 872 REJ09B0286-0300 Index PCSR .................. 269, 279, 797, 809, 819 PTCNT0 ..................... 260, 797, 808, 819 PTTER0 ...................... 564, 794, 806, 816 PWDPRA.................... 266, 801, 812, 822 PWDPRB.................... 267, 801, 812, 822 PWDR0 to 15.............. 266, 801, 812, 822 PWOERA ................... 267, 801, 812, 822 PWOERB.................... 268, 801, 812, 822 PWSL.......................... 264, 801, 812, 822 RAR .................................................... 170 RDR ............................ 392, 801, 812, 822 RFU .................................................... 167 RSPR .......................... 638, 792, 804, 815 RSPRD................................................ 638 RSPTYR ..................... 633, 792, 804, 815 RSR..................................................... 392 SAR .................... 149, 480, 801, 812, 822 SARX.......................... 481, 801, 812, 822 SBYCR ....................... 772, 797, 809, 819 SCICR......................... 412, 796, 808, 818 SCIDTER.................... 416, 796, 807, 818 SCMR ......................... 404, 801, 812, 822 SCR............................. 396, 801, 812, 822 SDBPR................................................ 746 SDBSR................................................ 746 SDIDR ................................................ 754 SDIR ................................................... 744 SEDGR ....................... 356, 803, 814, 823 SEMR ......................... 412, 796, 807, 818 SMR............................ 393, 801, 812, 822 SSR ............................. 398, 801, 812, 822 STCR ............................ 59, 800, 811, 821 SUBMSTPBH ............ 778, 794, 806, 817 SUBMSTPBL............. 778, 794, 806, 817 SYSCR.......................... 57, 800, 811, 821 SYSCR2.............. 235, 775, 797, 809, 819 TBCR.......................... 636, 792, 804, 815 TBNCR....................... 636, 792, 804, 815 TCNT..........320, 375, 799, 801, 811, 812, 820, 822 Rev. 3.00 Jan 25, 2006 page 870 of 872 REJ09B0286-0300 TCONRI...................... 348, 803, 814, 823 TCONRO .................... 352, 803, 814, 823 TCONRS..................... 354, 803, 814, 823 TCORA ....................... 320, 800, 812, 821 TCORB ....................... 320, 801, 812, 822 TCORC ....................... 328, 803, 813, 823 TCR............ 296, 321, 798, 800, 810, 812, 820, 821 TCSR .......................... 293, 798, 809, 819 TCSR_0 ............. 323, 376, 799, 800, 811, 812, 820, 821 TCSR_1 ............. 324, 378, 800, 802, 812, 813, 821, 822 TCSR_X...................... 326, 802, 813, 823 TCSR_Y...................... 327, 802, 813, 823 TDR ............................ 392, 801, 812, 822 TFFR0 ......................... 576, 794, 806, 817 TICR ................................................... 328 TICRF ......................... 329, 802, 813, 823 TICRR......................... 329, 802, 813, 823 TIER............................ 292, 798, 809, 819 TISR............................ 329, 803, 813, 823 TMP .................................................... 171 TOCR.......................... 297, 798, 810, 820 TSFR0 ......................... 571, 794, 806, 817 TSR ..................................................... 392 UDTRFR..................... 599, 793, 805, 816 UPLLCR ..................... 595, 794, 806, 817 UPRTCR ..................... 601, 793, 805, 816 USBCR0 ..................... 592, 794, 806, 817 USBCR1 ..................... 594, 793, 805, 816 USBCSR0 ................... 581, 794, 806, 817 USBIER0 .................... 566, 794, 806, 817 USBIER1 .................... 567, 793, 805, 816 USBIFR0..................... 568, 794, 806, 817 USBIFR1..................... 571, 793, 805, 816 USBMDCR ................. 600, 793, 805, 816 UTESTR0 ................... 601, 793, 805, 816 UTESTR1 ................... 601, 793, 805, 816 WAR ................................................... 171 Index WSCR ......................... 110, 800, 812, 821 WSCR2 ....................... 112, 797, 809, 819 WUEMR3 ..................... 83, 802, 813, 823 Relative Address Commands.................. 657 Repeat Mode........................................... 158 Reset ......................................................... 67 Reset Exception Handling......................... 68 resolution ........................................ 264, 281 RFU Bus Cycle ............................... 184, 188 RFU Manipulation by MCIF .................. 200 RFU Manipulation by SCI ...................... 197 RFU Manipulation by USB .................... 193 RFU Response Time............................... 189 Scan Mode .............................................. 706 Serial Communication Interface (SCI) ... 387 Serial Data Reception ............. 427, 441, 453 Serial Data Transmission ........ 425, 438, 450 Serial Formats ......................................... 516 SETUP Token......................................... 604 Shift Instructions....................................... 38 Single Data Block ................................... 191 Single Mode............................................ 705 Slave address .......................................... 517 Slave Receive Operation......................... 522 Slave Transmit Operation ....................... 525 Sleep Mode ............................................. 782 Smart Card Interface............................... 445 Software Protection................................. 737 Software Standby Mode.......................... 782 SPI Mode ................................................ 675 stack pointer (SP) ......................................26 Stack Status ...............................................70 Start condition .........................................517 Stop condition .........................................517 Subactive Mode.......................................787 Subsleep Mode........................................786 Suspend/Resume .....................................618 System Control Instructions ......................42 TAP Controller........................................755 Timer Connection ...................................345 Transfer Rate...........................................484 Trap Instruction Exception Handling ........69 TRAPA instruction .............................46, 69 Universal Serial Bus Interface (USB) .....553 USB Data FIFO.......................................557 USB Function Core.................................602 User Debug Interface (H-UDI) ...............741 User Program Mode ................................732 Valid Strobes...................................124, 138 vector number for the software activation interrupt...................................................151 VSYNCO Output ....................................371 Wait Control............................ 133, 136, 140 Watch Mode............................................785 Watchdog Timer (WDT).........................373 Watchdog Timer Mode ...........................379 Rev. 3.00 Jan 25, 2006 page 871 of 872 REJ09B0286-0300 Index Rev. 3.00 Jan 25, 2006 page 872 of 872 REJ09B0286-0300 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2158 Group, H8S/2158 F-ZTATTM Publication Date: 1st Edition, September 2001 Rev.3.00, January 25, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 5.0 H8S/2158 Group, H8S/2158 F-ZTATTM Hardware Manual

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